He is not lucid. I suppose it means the wafers were not ready? Perhaps a "dry wafer" is chip-manufacturing idiom for finished, ready to be cut? We know lots of water is used, so conceivably, wafers are wet at some point?
That’s very interesting. Intel 4 MTL used a tiny little die and still they had a very high defect rate?
Intel never mentioned these issues for the past six months. Why are they coming out all of a sudden?
That is…demonically bad. You only made one tile, Intel. You’ve launched nodes before.
Abundantly clear MTL was so overhyped. Didn’t get a desktop release. Didn’t even satisfy the full notebook market. Battery life was meh. The bottleneck was Intel’s flagship node. Shifted to overseas in Ireland last-minute from Oregon.
And Pat Geisinger wants to fab Apple’s CPUs. I don’t know how anyone still believes this guy.
That's because intel 4 is really 7NM using their EUV (not deep EUV), 7nm is at the edge of what you can do with EUV. being at the edge means high defect rates. This is not something Intel can really fix. The best they can do is go slow reduce the defect rates. But I guess they took a decision that they can get more end result with high rejections being fast than low rejection being slow. They are stuck in this until they get those machines for d-EUV. and those will only trickle in over the period of year or more.
DUV means deep ultra-violet (used by Intel and other Western manufacturers up to 12 nm), EUV means Extreme ultraviolet (used for 10 nm and smaller). There is no "deep EUV"
seems that Intel 4 node is not mature, have low yield (typical for not mature node), and require more wafers for planned output. How mature will be other processes like Intel 3, 20A and 18A. Pat vision 5N4Y is rushed, and may create other problems with CPU reliability.
It isn't bad, just that it isn't good compared to what AMD had with ZEN4. The reason is simple, Zen4 is on 4NM while intel 4 is misleading name as it is really 7nm. There is no way for them to match AMD efficiency with performance per watt with meteor lake. Meteor lake efficiency is closer to 5-3 year old ZEN3 on 7nm-6nm. But lunar lake will change all that. It will be their first chance for their engineering to see its true potential. I am going to bet it will be far ahead of qualcomm and AMD in performance per watt. And even more in battery life for laptops. they should really come close to APPLE with this.
"Decoding Moorhead’s dense tweets, fundamentally, Moorhead is questioning why Intel's Cost of Goods Sold (COGS) – how much the company's chips cost to produce – were on the rise with the launch of Meteor Lake. The analyst surmised that yields and/or some other unexpected production bottleneck must be the case, as these are the typical issues that drive up chip COGS on a short-term basis like Intel has been experiencing."
One question is whether the fabbing of Intel 3 (for Xeons) and Intel 4 (for Meteor Lake CPU tiles) use the same scanners and other equipment in Fab 34 (not at the same time, of course). If Intel had to divert capacity from making Xeons to making more Meteor Lakes, it would have indeed hit their bottom line, as server CPUs are high margin products. The other question is whether the demand from OEMs for Raptor Lake mobile CPUs dropped more precipitously than Intel had predicted. Intuitively, that would make sense to me: if I order an Intel laptop in 2024, I'd want the newest SoC/CPU, not one of the older models. And, unlike the transition from Alder Lake to Raptor Lake, this was not just an evolutionary update. As for what their yield is, there should be a statement of some sort in Intel's quarterly reports, but likely buried in a footnote. Lastly, by simple transistor density per square mm, Intel 4 is about where TSMC 4 is, although those comparisons are tricky, as for example L1 caches (SRAM) are not increasing area density the same way as logic does when moving to a better node.
"Moorhead is questioning why Intel's Cost of Goods Sold (COGS) – how much the company's chips cost to produce – were on the rise with the launch of Meteor Lake."
Isn't this explained by the simple fact that chiplet packaging is not free?
Look, I could be wrong here because no-one outside the relevant companies has access to the pricing and yield data. But the point of chiplets initially was (a) a way to grow beyond the reticle limit (basically how AMD or Apple use them, and what nV will presumably do soon) (b) a way to move functionality that's not much boosted by new process off to a cheaper process (again AMD). This second scheme is finicky in that you won't come out ahead unless either you can charge more for your chiplet product (ie fold in the packaging costs) OR the disaggregation you choose doesn't require that much chiplet-to-chiplet communication, so you can get away with cheaper packaging.
Intels' embrace of chiplets seems to have nothing to do with either of these and 100% to do with "marketing has told us that chiplets are cool, so let's use them everywhere". Technically their chiplet split doesn't make sense, with the consequence that they need very high end packaging to claw back the power/performance losses of how they chose to disaggregate functionality.
I mean, it wouldn't surprise me if they ARE having yield issues -- and learning why no-one in the past ever promised "5 nodes in 4 years".... But my suspicion (suspicion, given that we don't know numbers) is that the unforced (and, oh what a surprise, marketing driven -- because Intel is STILL, even after the disasters of the past ten years, PRIMARILY a marketing company) choice of all chiplets everywhere is driving this increased COGS.
I think Intel is precisely doing (b) - it can use chiplets to move parts of its manufacturing over to TSMC rather than having to produce low-added-value stuff on its highest-end processes. Intel's best is at least as good as TSMC's best, but it's clearly significantly more expensive for Intel.
"Intel's best is at least as good as TSMC's best, but it's clearly significantly more expensive for Intel." unless you consider performance per Watt of course.
The public commentary on Intel feels a lot like the negativity on Boeing at the moment, though it is a lot less deserved. This audience should know better. I will briefly make the case for Intel and give some context.
Dennard scaling basically ended in 2001 at the 130 nm node. After that new nodes got significantly harder and expensive to make. Things continued however and at the 45 nm node we got Hf gates. These were basically made by the method IBM Research figured out. People I know figured out some of the key steps. But the point of mentioning this is a few fold. First no one company does it all, everyone has to share because it is just so expensive to make new nodes. Second, the transistor we all use for digital is a crazy mutant of exotic steps now.
After high-k gates (HfO2) and then fin fets the next big step isn't some marking name for a node. Intel 7++++ can be just as good as 0.0004 what matters is cell density and some of TSMC's appearance of leadership was for a time just marketing. But right now they are in the lead. What is the next big step is Gate all around. Samsung foundry was first to produce this.
Being first isn't the only thing that matters though, the other thing that matters is of course yield. That is why you get 3x, 3y, 3z iterative improvements at places like TSMC and 7++++ from Intel. Changes to design rules, small improvements, better performance higher yield.
Another big thing is power delivery. Backside power. Intel has this first. Ahead of Samsung and TSMC by a few years it looks like with 20A/18A. That's a very very long time in the Semiconductor space. TSMC claims theirs will be better, it could be but really they have to say that.
If you have ever designed an ASIC (I have), then you know who makes the chip does not really matter a lot, as long as the devices and cells in the library deliver on performance you like it. Of course this is the engineer talking not that CFO. That I cannot speak to. So for the technical leadership what will matter is: is this process node good? For the financials it will be does it yield.
Looking in from the outside without any NDA access to the PDKs, it looks like Intel has a winner with 18A.
But the doom mongers will say: Intel is bad. Well AMD was bad at one point. So much so they had to spin off GF. Tons of semiconductor companies have been merged. Intel was terrible with the P4 until they weren't with Core. It is a cyclical business and it would be foolish to count Intel out.
Why? Imagine you are a smart person and you love science and you just got your PhD making cool new transistors. Do you want to work in Korea, Taiwan or the US? That's really your choices, if you are from China you might have a few more. Your standard of living is going to be higher in the US. Guess what you want to work for Intel then. So Intel has this big advantage: better pay, and better talent (in principle). But until recently a much less supportive government policy. It wasn't Intel competing again TSMC or Samsung it was Intel vs the company + government policy. That's kind of a big deal. GF gave up on new nodes. IBM gave up on hardware. There is a pretty easy reason there. It isn't because the US isn't good it is because of national policy.
So on paper 18A is rather good looking in features. PDK wise I have to believe it is good too but I haven't seen it. Everyone still is flush with AI accelerator money. PDK 1.0 is out. You can bet your ass a lot of engineers are studying if they can get any advantage at all from 18A at Amazon, Microsoft and Google; probably at Apple too but maybe not due to the long standing relationship with TSMC and bankrolling the roll out of new nodes.
Lunar Lake is going to be on TSMC nodes in a month. I'm betting it will be pretty damn good. The designer side of Intel isn't dumb. The foundry side has a shot of being the leader and best again by the end of 2025. GF bled money at first horrifically. Pushing for new nodes it just so expensive now. Intel trying to go foundry shows that it is too expensive for just Intel to pay for. It takes Apple and Nvidia and AMD pre-buying supply to justify doing it.
So the question is how many foundries can the world support pushing slight improvements? 1, 2, 3, more?
Your bet is if Intel Foundry will be the next GF or if it will be the next TSMC. Remember those pesky governments. It will take until 2026 to find out. But don't under-rate the clever people Intel has, you don't see those in the quarterly results. They have to be given the resources though. Right now that's a rocky road given the capex burn, and the business need to lay so many off. They don't have anywhere to go really if they want to stay in Semis in the US; the ones that matter in R&D. They can leave the industry though.
Like AMD, I think Intel will recover (Boeing too actually), it will just take a few years.
Risk production data in the first 120 days of Meteor Lake pointed to a yield issue I determined on other components that was likely package related learning curve. I reported on that here at the time which got a laugh on MSI Claw handheld Intel margin sacrifice. When the ramp data shows the cost of a component at risk production (up to 5%) is $227 and does not drop below $100 until passing 23% of the run that is not ideal. Intel aims for $64 down to $53 average marginal cost. mb
As you seem to have cost estimates, how does that compare to, for example, i7 or i9 Raptor Lakes, especially the mobile (HX) variants?
Apart from that, Intel is clearly in high volume production with Meteor Lake for a little while now, and I sometimes wonder if they won't revisit their positioning of Meteor Lake as for mobile devices only.
@eastcoastpete, after reading Anandtech Lunar Lake at B stepping report my Meteor Lake impression on channel available supply doubling +115% from May 25th through July 27th is CEO Gelsinger q2 "made to many" suggests Meteor through q2 was a final validation run like Tiger U quad before moving to Tiger U octa.
There are so many Tiger U quad in the channel, mostly secondary sale now, they may never entirely be sold down but apparently thought necessary when produced before and ensuring how to fabricate a Tiger quad to effectively fabricate a Tiger octa.
Could be similar here for Meteor Lake on run down peak production subject constant learning to resolve all the primarily backend packaging glitches' before moving to Lunar Lake. Lunar I suspect will be a mirror equal distribution; Meteor run up, Lunar run down.
On Raptor desktop S similar HX $36 variable and $60 marginal cost of full run production is my take on RMA replacement cost + handling.
$1K Average Weighed Price for 14S + 13S full line + 14 HX + 13 HX full line is $385 that is an Intel Competitive profit point and the simple rule is $1K and for precision on full line $1K AWP / 8 = marginal cost = $48.
At Marginal Cost = Marginal Revenue = $192 that is gross on INTC 10Q / 4 = $64 so there's a range.
On total revenue total cost assessment from gross $52.39 that is $96 up to 5% of full run that is risk production, up to 23% marginal cost of production drops to $56 but pops to $67 pushing peak surplus volume into 74% of the run dropping to $11.62 run end variable cost of sorting the slack; $52.39 marginal cost. Marginal revenue potential is $139.61except much of that was lost in a wholesale and end sales outlet price war stepping on AMD Ryzen desktop.
Whoops bit error there, $192 / 4 = $48 right stated that paragraph before so / 3 = $64 would suggest issues. Total revenue total cost assessment relies on Intel models so range $48 to $52 to $60.
If a Meteor Lake production surplus gets thrown into sales packages and sent to NUCs? mb
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
28 Comments
Back to Article
heffeque - Thursday, August 1, 2024 - link
Things are looking mighty "high temperature" for Intel... and not in a good way.ballsystemlord - Thursday, August 1, 2024 - link
What exactly does "bone dry" mean in this context?I'm an English native and I've never have known what the heck this guy was saying if it wasn't for a translation.
GeoffreyA - Friday, August 2, 2024 - link
He is not lucid. I suppose it means the wafers were not ready? Perhaps a "dry wafer" is chip-manufacturing idiom for finished, ready to be cut? We know lots of water is used, so conceivably, wafers are wet at some point?Ryan Smith - Friday, August 2, 2024 - link
"Bone dry" in this context would mean that OEMs would not be receiving any MTL chips.The analogy is a water well; if there isn't any water available, it's said to be bone dry.
In this case, the flow of MTL chips was *not* bone dry; hence OEMs got chips. Just not enough of them.
ballsystemlord - Friday, August 2, 2024 - link
Thanks!eastcoast_pete - Friday, August 2, 2024 - link
In industrial gases, bone dry grade means no detectable moisture. So, very dry indeed.ballsystemlord - Friday, August 2, 2024 - link
Thanks for the cross industry interpretation. I found it fascinating.ikjadoon - Thursday, August 1, 2024 - link
That’s very interesting. Intel 4 MTL used a tiny little die and still they had a very high defect rate?Intel never mentioned these issues for the past six months. Why are they coming out all of a sudden?
That is…demonically bad. You only made one tile, Intel. You’ve launched nodes before.
Abundantly clear MTL was so overhyped. Didn’t get a desktop release. Didn’t even satisfy the full notebook market. Battery life was meh. The bottleneck was Intel’s flagship node. Shifted to overseas in Ireland last-minute from Oregon.
And Pat Geisinger wants to fab Apple’s CPUs. I don’t know how anyone still believes this guy.
sharath.naik - Friday, August 2, 2024 - link
That's because intel 4 is really 7NM using their EUV (not deep EUV), 7nm is at the edge of what you can do with EUV. being at the edge means high defect rates. This is not something Intel can really fix. The best they can do is go slow reduce the defect rates. But I guess they took a decision that they can get more end result with high rejections being fast than low rejection being slow.They are stuck in this until they get those machines for d-EUV. and those will only trickle in over the period of year or more.
Bulat Ziganshin - Wednesday, August 7, 2024 - link
DUV means deep ultra-violet (used by Intel and other Western manufacturers up to 12 nm), EUV means Extreme ultraviolet (used for 10 nm and smaller). There is no "deep EUV"Exotica - Thursday, August 1, 2024 - link
So in other words Intel supply of meteor lake couldn’t keep up with demand ? So meteor lake isn’t as bad as some people have made it out to be ?boozed - Thursday, August 1, 2024 - link
Come on you didn't really comment without even reading the headline, surely?TristanSDX - Friday, August 2, 2024 - link
seems that Intel 4 node is not mature, have low yield (typical for not mature node), and require more wafers for planned output. How mature will be other processes like Intel 3, 20A and 18A. Pat vision 5N4Y is rushed, and may create other problems with CPU reliability.sharath.naik - Friday, August 2, 2024 - link
It isn't bad, just that it isn't good compared to what AMD had with ZEN4. The reason is simple, Zen4 is on 4NM while intel 4 is misleading name as it is really 7nm. There is no way for them to match AMD efficiency with performance per watt with meteor lake. Meteor lake efficiency is closer to 5-3 year old ZEN3 on 7nm-6nm.But lunar lake will change all that. It will be their first chance for their engineering to see its true potential. I am going to bet it will be far ahead of qualcomm and AMD in performance per watt. And even more in battery life for laptops. they should really come close to APPLE with this.
name99 - Friday, August 2, 2024 - link
[IMG]https://media.tenor.com/ykSYWwbklz8AAAAM/this-time...
[/IMG]
boozed - Thursday, August 1, 2024 - link
What's the difference in lead time between a "hot lot" and a regular (room temperature?) production run?meacupla - Friday, August 2, 2024 - link
read the 3rd paragraphboozed - Saturday, August 3, 2024 - link
This one?"Decoding Moorhead’s dense tweets, fundamentally, Moorhead is questioning why Intel's Cost of Goods Sold (COGS) – how much the company's chips cost to produce – were on the rise with the launch of Meteor Lake. The analyst surmised that yields and/or some other unexpected production bottleneck must be the case, as these are the typical issues that drive up chip COGS on a short-term basis like Intel has been experiencing."
eastcoast_pete - Friday, August 2, 2024 - link
One question is whether the fabbing of Intel 3 (for Xeons) and Intel 4 (for Meteor Lake CPU tiles) use the same scanners and other equipment in Fab 34 (not at the same time, of course). If Intel had to divert capacity from making Xeons to making more Meteor Lakes, it would have indeed hit their bottom line, as server CPUs are high margin products.The other question is whether the demand from OEMs for Raptor Lake mobile CPUs dropped more precipitously than Intel had predicted. Intuitively, that would make sense to me: if I order an Intel laptop in 2024, I'd want the newest SoC/CPU, not one of the older models. And, unlike the transition from Alder Lake to Raptor Lake, this was not just an evolutionary update.
As for what their yield is, there should be a statement of some sort in Intel's quarterly reports, but likely buried in a footnote.
Lastly, by simple transistor density per square mm, Intel 4 is about where TSMC 4 is, although those comparisons are tricky, as for example L1 caches (SRAM) are not increasing area density the same way as logic does when moving to a better node.
name99 - Friday, August 2, 2024 - link
"Moorhead is questioning why Intel's Cost of Goods Sold (COGS) – how much the company's chips cost to produce – were on the rise with the launch of Meteor Lake."Isn't this explained by the simple fact that chiplet packaging is not free?
Look, I could be wrong here because no-one outside the relevant companies has access to the pricing and yield data. But the point of chiplets initially was
(a) a way to grow beyond the reticle limit (basically how AMD or Apple use them, and what nV will presumably do soon)
(b) a way to move functionality that's not much boosted by new process off to a cheaper process (again AMD). This second scheme is finicky in that you won't come out ahead unless either you can charge more for your chiplet product (ie fold in the packaging costs) OR the disaggregation you choose doesn't require that much chiplet-to-chiplet communication, so you can get away with cheaper packaging.
Intels' embrace of chiplets seems to have nothing to do with either of these and 100% to do with "marketing has told us that chiplets are cool, so let's use them everywhere". Technically their chiplet split doesn't make sense, with the consequence that they need very high end packaging to claw back the power/performance losses of how they chose to disaggregate functionality.
I mean, it wouldn't surprise me if they ARE having yield issues -- and learning why no-one in the past ever promised "5 nodes in 4 years"....
But my suspicion (suspicion, given that we don't know numbers) is that the unforced (and, oh what a surprise, marketing driven -- because Intel is STILL, even after the disasters of the past ten years, PRIMARILY a marketing company) choice of all chiplets everywhere is driving this increased COGS.
TomWomack - Saturday, August 3, 2024 - link
I think Intel is precisely doing (b) - it can use chiplets to move parts of its manufacturing over to TSMC rather than having to produce low-added-value stuff on its highest-end processes. Intel's best is at least as good as TSMC's best, but it's clearly significantly more expensive for Intel.Zoolook13 - Monday, August 12, 2024 - link
"Intel's best is at least as good as TSMC's best, but it's clearly significantly more expensive for Intel." unless you consider performance per Watt of course.drwho9437 - Sunday, August 4, 2024 - link
The public commentary on Intel feels a lot like the negativity on Boeing at the moment, though it is a lot less deserved. This audience should know better. I will briefly make the case for Intel and give some context.Dennard scaling basically ended in 2001 at the 130 nm node. After that new nodes got significantly harder and expensive to make. Things continued however and at the 45 nm node we got Hf gates. These were basically made by the method IBM Research figured out. People I know figured out some of the key steps. But the point of mentioning this is a few fold. First no one company does it all, everyone has to share because it is just so expensive to make new nodes. Second, the transistor we all use for digital is a crazy mutant of exotic steps now.
After high-k gates (HfO2) and then fin fets the next big step isn't some marking name for a node. Intel 7++++ can be just as good as 0.0004 what matters is cell density and some of TSMC's appearance of leadership was for a time just marketing. But right now they are in the lead. What is the next big step is Gate all around. Samsung foundry was first to produce this.
Being first isn't the only thing that matters though, the other thing that matters is of course yield. That is why you get 3x, 3y, 3z iterative improvements at places like TSMC and 7++++ from Intel. Changes to design rules, small improvements, better performance higher yield.
Another big thing is power delivery. Backside power. Intel has this first. Ahead of Samsung and TSMC by a few years it looks like with 20A/18A. That's a very very long time in the Semiconductor space. TSMC claims theirs will be better, it could be but really they have to say that.
If you have ever designed an ASIC (I have), then you know who makes the chip does not really matter a lot, as long as the devices and cells in the library deliver on performance you like it. Of course this is the engineer talking not that CFO. That I cannot speak to. So for the technical leadership what will matter is: is this process node good? For the financials it will be does it yield.
Looking in from the outside without any NDA access to the PDKs, it looks like Intel has a winner with 18A.
But the doom mongers will say: Intel is bad. Well AMD was bad at one point. So much so they had to spin off GF. Tons of semiconductor companies have been merged. Intel was terrible with the P4 until they weren't with Core. It is a cyclical business and it would be foolish to count Intel out.
Why? Imagine you are a smart person and you love science and you just got your PhD making cool new transistors. Do you want to work in Korea, Taiwan or the US? That's really your choices, if you are from China you might have a few more. Your standard of living is going to be higher in the US. Guess what you want to work for Intel then. So Intel has this big advantage: better pay, and better talent (in principle). But until recently a much less supportive government policy. It wasn't Intel competing again TSMC or Samsung it was Intel vs the company + government policy. That's kind of a big deal. GF gave up on new nodes. IBM gave up on hardware. There is a pretty easy reason there. It isn't because the US isn't good it is because of national policy.
So on paper 18A is rather good looking in features. PDK wise I have to believe it is good too but I haven't seen it. Everyone still is flush with AI accelerator money. PDK 1.0 is out. You can bet your ass a lot of engineers are studying if they can get any advantage at all from 18A at Amazon, Microsoft and Google; probably at Apple too but maybe not due to the long standing relationship with TSMC and bankrolling the roll out of new nodes.
Lunar Lake is going to be on TSMC nodes in a month. I'm betting it will be pretty damn good. The designer side of Intel isn't dumb. The foundry side has a shot of being the leader and best again by the end of 2025. GF bled money at first horrifically. Pushing for new nodes it just so expensive now. Intel trying to go foundry shows that it is too expensive for just Intel to pay for. It takes Apple and Nvidia and AMD pre-buying supply to justify doing it.
So the question is how many foundries can the world support pushing slight improvements? 1, 2, 3, more?
Your bet is if Intel Foundry will be the next GF or if it will be the next TSMC. Remember those pesky governments. It will take until 2026 to find out. But don't under-rate the clever people Intel has, you don't see those in the quarterly results. They have to be given the resources though. Right now that's a rocky road given the capex burn, and the business need to lay so many off. They don't have anywhere to go really if they want to stay in Semis in the US; the ones that matter in R&D. They can leave the industry though.
Like AMD, I think Intel will recover (Boeing too actually), it will just take a few years.
Bruzzone - Monday, August 5, 2024 - link
Risk production data in the first 120 days of Meteor Lake pointed to a yield issue I determined on other components that was likely package related learning curve. I reported on that here at the time which got a laugh on MSI Claw handheld Intel margin sacrifice. When the ramp data shows the cost of a component at risk production (up to 5%) is $227 and does not drop below $100 until passing 23% of the run that is not ideal. Intel aims for $64 down to $53 average marginal cost. mbBruzzone - Monday, August 5, 2024 - link
I'd say Meteor is just now dropping under $80 marginal cost to produce per unit of production. mbeastcoast_pete - Monday, August 5, 2024 - link
As you seem to have cost estimates, how does that compare to, for example, i7 or i9 Raptor Lakes, especially the mobile (HX) variants?Apart from that, Intel is clearly in high volume production with Meteor Lake for a little while now, and I sometimes wonder if they won't revisit their positioning of Meteor Lake as for mobile devices only.
Bruzzone - Tuesday, August 6, 2024 - link
@eastcoastpete, after reading Anandtech Lunar Lake at B stepping report my Meteor Lake impression on channel available supply doubling +115% from May 25th through July 27th is CEO Gelsinger q2 "made to many" suggests Meteor through q2 was a final validation run like Tiger U quad before moving to Tiger U octa.There are so many Tiger U quad in the channel, mostly secondary sale now, they may never entirely be sold down but apparently thought necessary when produced before and ensuring how to fabricate a Tiger quad to effectively fabricate a Tiger octa.
Could be similar here for Meteor Lake on run down peak production subject constant learning to resolve all the primarily backend packaging glitches' before moving to Lunar Lake. Lunar I suspect will be a mirror equal distribution; Meteor run up, Lunar run down.
On Raptor desktop S similar HX $36 variable and $60 marginal cost of full run production is my take on RMA replacement cost + handling.
$1K Average Weighed Price for 14S + 13S full line + 14 HX + 13 HX full line is $385 that is an Intel Competitive profit point and the simple rule is $1K and for precision on full line $1K AWP / 8 = marginal cost = $48.
At Marginal Cost = Marginal Revenue = $192 that is gross on INTC 10Q / 4 = $64 so there's a range.
On total revenue total cost assessment from gross $52.39 that is $96 up to 5% of full run that is risk production, up to 23% marginal cost of production drops to $56 but pops to $67 pushing peak surplus volume into 74% of the run dropping to $11.62 run end variable cost of sorting the slack; $52.39 marginal cost. Marginal revenue potential is $139.61except much of that was lost in a wholesale and end sales outlet price war stepping on AMD Ryzen desktop.
mb
Bruzzone - Tuesday, August 6, 2024 - link
Whoops bit error there, $192 / 4 = $48 right stated that paragraph before so / 3 = $64 would suggest issues. Total revenue total cost assessment relies on Intel models so range $48 to $52 to $60.If a Meteor Lake production surplus gets thrown into sales packages and sent to NUCs? mb