I take issue with using an FPGA to demonstrate a PHY. A phy is a digital to analog (and the reverse) type of device. The FPGA is just a digital device. If it has some kind of D/A in it, then this is more a demonstration of the FPGAs PHY abilities. So looking at they eye diagram tells us little about the Asmedia design. (Okay, if clocked poorly by their digital design, the horizintal width of the eye can be lower due to increased jitter), but the vertical SNR aspect of it will not be effected as that's a pure analog part of the design.
The take away is that this demonstration--if it is as has been described--is pretty meaningless.
Also, thank you for explaining to people how to read an eye diagram. Very few people--even those in the industry--know how to read one. Good job!
The FPGA certainly has SerDes hardware capable of 100Gbps per lane with multiple lanes per device. But I suspect they aren't using those SerDes transceivers directly as no FPGA supports PAM3.
It's easier to design a PAM3 SerDes PHY than the complete controller that has to account for power management, link negotiation, maybe tunneling, etc.
With PAM3, you should have two eye openings which is shown in the picture. PAM4 would have three eye openings. The number of openings is tied to the number of possible state transitions possible in the system. For PAM3, you have + to -, + to 0, - to 0 and then those again in the opposite direction.
Not to undermine Asmedia's here at getting 40 Gbit rates over a single lane (the 160 Gbit transfer figures is across four lanes for reference) is still an accomplishment. However, the image isn't perfect as the two eyes are not perfectly aligned nor symmetrical which would indicate a cleaner signal. What they have presented should work fine but more of a nitpick that this is not a textbook perfect signal example.
The article says "the relatively narrow horizontal spread of the eye opening suggests that there is minimal jitter, meaning the signal transitions are consistent and predictable"
Shouldn't wider horizontal openings represent less jitter?
It's nice to see USB Next, but like any first generation hardware, few if any people are going to care much until it's integrated and just ships as a mundane feature that doesn't demand an AIB or kludge-fest primitive mess to just work and for USB4, that'll be a while.
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
8 Comments
Back to Article
ballsystemlord - Wednesday, June 12, 2024 - link
That is one powerful oscilloscope. 33Ghz!The ASMedia USB controller is cool too, of course.
juancn - Wednesday, July 3, 2024 - link
Talk about a flex! Those go for 250k and above.dwillmore - Wednesday, June 12, 2024 - link
I take issue with using an FPGA to demonstrate a PHY. A phy is a digital to analog (and the reverse) type of device. The FPGA is just a digital device. If it has some kind of D/A in it, then this is more a demonstration of the FPGAs PHY abilities. So looking at they eye diagram tells us little about the Asmedia design. (Okay, if clocked poorly by their digital design, the horizintal width of the eye can be lower due to increased jitter), but the vertical SNR aspect of it will not be effected as that's a pure analog part of the design.The take away is that this demonstration--if it is as has been described--is pretty meaningless.
Also, thank you for explaining to people how to read an eye diagram. Very few people--even those in the industry--know how to read one. Good job!
The Von Matrices - Wednesday, June 12, 2024 - link
I am surprised about the use of an FPGA primarily because I did not know that any FPGA had SerDes hardware that could operate at these speeds.erinadreno - Friday, June 14, 2024 - link
The FPGA certainly has SerDes hardware capable of 100Gbps per lane with multiple lanes per device. But I suspect they aren't using those SerDes transceivers directly as no FPGA supports PAM3.It's easier to design a PAM3 SerDes PHY than the complete controller that has to account for power management, link negotiation, maybe tunneling, etc.
Kevin G - Wednesday, June 12, 2024 - link
With PAM3, you should have two eye openings which is shown in the picture. PAM4 would have three eye openings. The number of openings is tied to the number of possible state transitions possible in the system. For PAM3, you have + to -, + to 0, - to 0 and then those again in the opposite direction.Not to undermine Asmedia's here at getting 40 Gbit rates over a single lane (the 160 Gbit transfer figures is across four lanes for reference) is still an accomplishment. However, the image isn't perfect as the two eyes are not perfectly aligned nor symmetrical which would indicate a cleaner signal. What they have presented should work fine but more of a nitpick that this is not a textbook perfect signal example.
The Von Matrices - Wednesday, June 12, 2024 - link
The article says "the relatively narrow horizontal spread of the eye opening suggests that there is minimal jitter, meaning the signal transitions are consistent and predictable"Shouldn't wider horizontal openings represent less jitter?
PeachNCream - Wednesday, June 12, 2024 - link
It's nice to see USB Next, but like any first generation hardware, few if any people are going to care much until it's integrated and just ships as a mundane feature that doesn't demand an AIB or kludge-fest primitive mess to just work and for USB4, that'll be a while.