Samsung still has DRAM, NAND, and HBM they can count on. There are also rumors that AMD will use Samsung for their low end Ryzen and Radeon chips. TSMC has limited capacity being bought by Apple and Nvidia, so it would make sense to buy from cheaper Samsung. Kind of like what Nvidia did with RTX 3000 series.
Intel on tthe otoher hand... all they have is brand name recognition momentum carrying them.
Point 1, "2nm" according to who? How does this compare to the competition in scale, price, and yield? Point 2, when did Intel say something in the last few years and deliver?
Actually they have been getting much closer in delivering what they promised. Intel 2 Lunar Lake will be here in the second half. Considering we are already in May it is very unlikely that gets delayed. Do you even follow the news or do you only resort to add uninformed snarky remarks?
News = Useless announcements/ads from the company that continually lies and fails to deliver for half a decade, if there's no product on the market, there's nothing to talk about*
do you know that intel can't scale Meteor Lake volume because of yields and packing problems ? Intel has all the problems in the world falling on its head.
You are mistaken, TMSC is simply a factory floor, the machines are built by ASML. Intel buys from ASML too, for what ever reason they delayed buying the EUV machines from them. So Intel will catch up in a couple of years. So it comes down to if intel's chip packaging can make the difference. In my opinion starting with lunar lake, Intel will retake the lead from AMD on mobile processors.
And the award for the most pointless comment of all time goes to... Yeah, You're clueless, guy. Machines are just one part of the equation, having them won't magically make the process better than the competition.
You must be paid by TSMC, just a couple of PR/IR slide, a couple of meaningless % of improvement, suddenly there are ** *** all over N3P, what that meant, why other node don't have ** ***
It is intended to be look like this because the original comment also sound like a been paid by TSMC
Where specifically lithography with say 3nm is needed if each transistor has *at least* whopping 40x40 nm in size on the surface (despite all interconnects are typically below it and helping to keep the overall size smaller) and even with 1.6nm will be still not substantially different? The numbers like 40x40nm to 50x50nm you get for 3-5nm technologies dividing the chip area by number of transistors
[ and density progress mainly occurs within logic section (*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.), means only about 50% of that area is highly optimizable with shrinking&density efforts (since SRAM and analog for peripherals have different requirements on distances for capacitors or higher voltage requirements, but 'What's the potential for density optimization on these area sections?') ? ]
There is potential for a more-or-less 1-time jump in SRAM density with BSPD. (Whether it will be one time, or spread over two or three nodes depends on how aggressively clocks and signals are moved to backside along with power). But after that back to slow grind.
On the other hand, for designs that aren't power-insane, there's the potential to start moving SRAM onto a second layer. (Yeah, yeah, we all know about V-Cache, calm down!) Existing packaging for this sort of thing is sub-optimal, but obviously will be improved constantly over the next few years. So point is, with a split between ever more local logic on one layer, and SRAM on a second layer, the party can keep going for at least a few more years.
The main culprit is SRAM with signal lines not far behind. Once feature sizes got down to where they are a few years ago, the physical space that the capacitance of an SRAM cell requires became an intractable problem. You just can't shrink them much more and have them continue to function properly. As for signal lines, there has to be physically a minimum amount of material to move the signals between individual transistors, and as transistors have shrunk, the signal lines have had to remain roughly the same. SRAM and signal lines are taking up greater and greater proportions of the physical area of logic chips, and it doesn't appear that it's going to get much better anytime soon. BPD does help to some extent in that it moves some of the power lines to the back side of the transistors, but that only saves you a couple nodes worth of scaling and complicates chip lithography processing.
It would be interesting to see Zen 6 or 7 take L3 cache off the core die entirely, and move to all 3D cache on an older node, and differing amounts of layers to differentiate the product stack.
Samsung should get a move on with their own version: "X-Cube" announced in 2020, nowhere to be found since.
The problem with SRAM is the density of wiring. We can make the SRA transistors smaller, but then we can't pack all the wiring required to power and control them into the available space.
BTW DRAM (after a long long hiatus) is exploring ways of effectively stacking the (very long skinny) cylindrical capacitors. Samsung suggests it might have product by around 2031 (which, admittedly, is far enough away that I wouldn't take the exact date too seriously).
I was under the impression that backside power was supposed to alleviate SRAM wiring to some extent, but A16's density over N2 seems quite modest to say the least.
It's obviously bad, but if the SRAM scaling is nearly zero, and analog is also close to zero, then 1.15x would be more like 1.3x for logic.
The missing number is wafer price. A lot of customers could tolerate the stagnation in density scaling for the other benefits like performance and power efficiency, but if the wafer costs are skyrocketing, that could be a problem for some products.
Though there are still gains, I think the industry needs to look to technology beyond electrons and semiconductors, perhaps photons or something more radical.
Rest assured that they're looking at everything. Also while density gains are slowing there's still other innovations, PowerVIA, advanced packaging, etc.
[ Graphene is told getting into 100s GHz clock speeds, maybe even THz, but this theoretical advantage for ( that time new material 2008/2009, 2010, IBM transistor ~10-100GHz, 2013 '2013 researchers created transistors printed on flexible plastic that operate at 25 gigahertz' ) Graphene has been known for almost 1 1/2 decades. ]
So N2P is almost 40% more power efficient than already crazy efficient N3E and A16 is another 15-20% better. By the time Apple is on A16, they will have a 12-wide core running at 6ghz. Oryon 3rd gen also would be crazy and x86 would be dead at that point.
How are performance numbers to be interpreted then? Moving from N3E to A16 should gain 24.2% performance at the same power. Something that was running at 4 GHz should be hitting about 5 GHz.
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Terry_Craig - Wednesday, May 22, 2024 - link
Intel and Samsung are so done. *Just like consumers with no competition for TSMC.meacupla - Wednesday, May 22, 2024 - link
Samsung still has DRAM, NAND, and HBM they can count on.There are also rumors that AMD will use Samsung for their low end Ryzen and Radeon chips. TSMC has limited capacity being bought by Apple and Nvidia, so it would make sense to buy from cheaper Samsung. Kind of like what Nvidia did with RTX 3000 series.
Intel on tthe otoher hand... all they have is brand name recognition momentum carrying them.
shabby - Thursday, May 23, 2024 - link
Intel has 10nm...Turbofrog - Thursday, May 23, 2024 - link
This is a super weird take given that Intel will be delivering 2nm to OEMs at the end of 2024, potentially 6 months before TSMC.Terry_Craig - Thursday, May 23, 2024 - link
Point 1, "2nm" according to who? How does this compare to the competition in scale, price, and yield?Point 2, when did Intel say something in the last few years and deliver?
mattbe - Thursday, May 23, 2024 - link
Actually they have been getting much closer in delivering what they promised. Intel 2 Lunar Lake will be here in the second half. Considering we are already in May it is very unlikely that gets delayed. Do you even follow the news or do you only resort to add uninformed snarky remarks?Dante Verizon - Friday, May 24, 2024 - link
News = Useless announcements/ads from the company that continually lies and fails to deliver for half a decade, if there's no product on the market, there's nothing to talk about*do you know that intel can't scale Meteor Lake volume because of yields and packing problems ? Intel has all the problems in the world falling on its head.
my_wing - Thursday, May 23, 2024 - link
TSMC is done, Intel King of the world in 2024 onward, TSMC clearly on the tail.Not competition for TSMC for the next 10 years ha ha.
TSMC Die in water
Terry_Craig - Monday, June 10, 2024 - link
Here's a cookie, Pat's lackey.sharath.naik - Friday, May 24, 2024 - link
You are mistaken, TMSC is simply a factory floor, the machines are built by ASML. Intel buys from ASML too, for what ever reason they delayed buying the EUV machines from them. So Intel will catch up in a couple of years. So it comes down to if intel's chip packaging can make the difference.In my opinion starting with lunar lake, Intel will retake the lead from AMD on mobile processors.
Dante Verizon - Friday, May 24, 2024 - link
And the award for the most pointless comment of all time goes to... Yeah, You're clueless, guy. Machines are just one part of the equation, having them won't magically make the process better than the competition.Terry_Craig - Friday, May 24, 2024 - link
They must be paid by intel. It's not possible for someone to be so layman.my_wing - Sunday, May 26, 2024 - link
You must be paid by TSMC, just a couple of PR/IR slide, a couple of meaningless % of improvement, suddenly there are ** *** all over N3P, what that meant, why other node don't have ** ***It is intended to be look like this because the original comment also sound like a been paid by TSMC
Terry_Craig - Monday, May 27, 2024 - link
The company that beats intel with one hand behind its back doesn't need to pay anyone, the results speak for themselves.SanX - Wednesday, May 22, 2024 - link
Where specifically lithography with say 3nm is needed if each transistor has *at least* whopping 40x40 nm in size on the surface (despite all interconnects are typically below it and helping to keep the overall size smaller) and even with 1.6nm will be still not substantially different? The numbers like 40x40nm to 50x50nm you get for 3-5nm technologies dividing the chip area by number of transistorsnandnandnand - Wednesday, May 22, 2024 - link
The "nm" labels are purely marketing names now, no need to overthink it.All that matters is those PPA numbers. Density has cratered but we're seeing nice power efficiency increases.
name99 - Thursday, May 23, 2024 - link
Oh wow! Do other people know this????Inform the presses.
You have discovered a scandal that NO-ONE has realized in the past ten years!!!!
lemurbutton - Thursday, May 23, 2024 - link
Has density stopped scalling?7nm to 5nm = 1.8x density
5nm to 3nm is only 1.3x density
3nm to 2nm is only 1.15x
2nm to 1.6nm (A16) is only 1.10x.
That is a very very worrying trend.
back2future - Thursday, May 23, 2024 - link
[ diameter of a silicon atom is ~0.22-0.26nm, carbon atoms ~0.154nm, hydrogen atom ~0.1nm ]back2future - Thursday, May 23, 2024 - link
[ and density progress mainly occurs within logic section (*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.), means only about 50% of that area is highly optimizable with shrinking&density efforts (since SRAM and analog for peripherals have different requirements on distances for capacitors or higher voltage requirements, but 'What's the potential for density optimization on these area sections?') ? ]name99 - Thursday, May 23, 2024 - link
There is potential for a more-or-less 1-time jump in SRAM density with BSPD. (Whether it will be one time, or spread over two or three nodes depends on how aggressively clocks and signals are moved to backside along with power). But after that back to slow grind.On the other hand, for designs that aren't power-insane, there's the potential to start moving SRAM onto a second layer. (Yeah, yeah, we all know about V-Cache, calm down!) Existing packaging for this sort of thing is sub-optimal, but obviously will be improved constantly over the next few years.
So point is, with a split between ever more local logic on one layer, and SRAM on a second layer, the party can keep going for at least a few more years.
mattbe - Thursday, May 23, 2024 - link
You can't just look at the diameter of the silicone atom. The crystal lattice of a silicone atom is 0.543 nm......Dante Verizon - Thursday, May 23, 2024 - link
Almost... The cache is practically stagnant...Dante Verizon - Thursday, May 23, 2024 - link
3nm = 1.4x (See the progress of interactions.)lightningz71 - Thursday, May 23, 2024 - link
The main culprit is SRAM with signal lines not far behind. Once feature sizes got down to where they are a few years ago, the physical space that the capacitance of an SRAM cell requires became an intractable problem. You just can't shrink them much more and have them continue to function properly. As for signal lines, there has to be physically a minimum amount of material to move the signals between individual transistors, and as transistors have shrunk, the signal lines have had to remain roughly the same. SRAM and signal lines are taking up greater and greater proportions of the physical area of logic chips, and it doesn't appear that it's going to get much better anytime soon. BPD does help to some extent in that it moves some of the power lines to the back side of the transistors, but that only saves you a couple nodes worth of scaling and complicates chip lithography processing.Dante Verizon - Thursday, May 23, 2024 - link
SRAM needs to take the 3D route.nandnandnand - Thursday, May 23, 2024 - link
It would be interesting to see Zen 6 or 7 take L3 cache off the core die entirely, and move to all 3D cache on an older node, and differing amounts of layers to differentiate the product stack.Samsung should get a move on with their own version: "X-Cube" announced in 2020, nowhere to be found since.
name99 - Thursday, May 23, 2024 - link
SRAM doesn't rely on capacitance, that's DRAM.The problem with SRAM is the density of wiring. We can make the SRA transistors smaller, but then we can't pack all the wiring required to power and control them into the available space.
BTW DRAM (after a long long hiatus) is exploring ways of effectively stacking the (very long skinny) cylindrical capacitors. Samsung suggests it might have product by around 2031 (which, admittedly, is far enough away that I wouldn't take the exact date too seriously).
Dolda2000 - Thursday, May 23, 2024 - link
I was under the impression that backside power was supposed to alleviate SRAM wiring to some extent, but A16's density over N2 seems quite modest to say the least.nandnandnand - Thursday, May 23, 2024 - link
It's obviously bad, but if the SRAM scaling is nearly zero, and analog is also close to zero, then 1.15x would be more like 1.3x for logic.The missing number is wafer price. A lot of customers could tolerate the stagnation in density scaling for the other benefits like performance and power efficiency, but if the wafer costs are skyrocketing, that could be a problem for some products.
GeoffreyA - Thursday, May 23, 2024 - link
Though there are still gains, I think the industry needs to look to technology beyond electrons and semiconductors, perhaps photons or something more radical.Threska - Thursday, May 23, 2024 - link
Muons sounds like a zen approach.GeoffreyA - Thursday, May 23, 2024 - link
Undoubtedly, the use of the gluon will lead to the most Zen-like effects.tipoo - Thursday, May 23, 2024 - link
Rest assured that they're looking at everything. Also while density gains are slowing there's still other innovations, PowerVIA, advanced packaging, etc.GeoffreyA - Friday, May 24, 2024 - link
I think it's high time for a breakthrough in computing. Where are the THz processors?back2future - Friday, May 24, 2024 - link
[ Graphene is told getting into 100s GHz clock speeds, maybe even THz, but this theoretical advantage for ( that time new material 2008/2009, 2010, IBM transistor ~10-100GHz, 2013 '2013 researchers created transistors printed on flexible plastic that operate at 25 gigahertz' ) Graphene has been known for almost 1 1/2 decades. ]GeoffreyA - Saturday, May 25, 2024 - link
Thanks!Threska - Saturday, May 25, 2024 - link
The vacuum is everything.https://opg.optica.org/oe/fulltext.cfm?uri=oe-29-2...
GeoffreyA - Sunday, May 26, 2024 - link
That is quite interesting. Thanks.Threska - Saturday, May 25, 2024 - link
Vacuum-channel transistors.https://spectrum.ieee.org/introducing-the-vacuum-t...
GeoffreyA - Sunday, May 26, 2024 - link
It's ironic that the transistor generally replaced the vacuum tube, but to advance the transistor, we may need to go back to the tube.trivik12 - Thursday, May 23, 2024 - link
So N2P is almost 40% more power efficient than already crazy efficient N3E and A16 is another 15-20% better. By the time Apple is on A16, they will have a 12-wide core running at 6ghz. Oryon 3rd gen also would be crazy and x86 would be dead at that point.Terry_Craig - Thursday, May 23, 2024 - link
6Ghz? It doesn't work like that, little grasshopper.nandnandnand - Sunday, May 26, 2024 - link
How are performance numbers to be interpreted then? Moving from N3E to A16 should gain 24.2% performance at the same power. Something that was running at 4 GHz should be hitting about 5 GHz.tipoo - Thursday, May 23, 2024 - link
I'm trying to find the decode width on Oryon. Seems 14-issue, but unclear on the decode. M4 is 16 issue and 10-wide decode now.Dolda2000 - Thursday, May 23, 2024 - link
Since it's Qualcomm, we'll have to be happy if they even deign to tell us the cache sizes.my_wing - Thursday, May 23, 2024 - link
By the time A16 is there that will be the 2nd generation of Intel having GAA and PSDP.By the time A16 is out, it is a 2nd to the competition only. Back to the good old days, Intel always ahead.