What little info is there suggests it's not really different from the N5's. Which is a tad embarrassing given the rather relatively large step in node numbering.
I guess they're already up against the wall without high-NA equipment. That doesn't bode well.
Speaking of, 100% of all High-NA shipments are destined for USA this year. Line #2 already went to an unnamed recipient, speculated to be an IBM affiliated research facility. Speculating ... Maybe next year's batch goes to US based new fabs for TSMC, Samsung and co ... EU might get a look in since they're building the stuff ... nothing for Japan, Taiwan or Korea.
No TSMC will not install its first EUV High NA machine in the US, it has to be in Taiwan, they build a billion dollar research lab there, just like what Intel is doing.
EU is not might get a look, EU is going to get one in 2027, that is Intel Germany, it takes 3 months to set the machine up (although is the new one i.e. take longer but the machine arrived in the US in Dec 2023 and only in weeks time that first lights-on), the schedule is that Q4 2027 Germany online i.e. the machine needed to be there Q1 2027, assuming there isn't just 1 EUV machine.
The TSMC density count is based on a ratio of transistor, so Apple M3 or so did not come with the ration that TSMC specify therefore they said they don't know.
N5/N3ABCXYZ they all just marketing name, basically is optimized FinFET, N2ABCXYZ is just the segment that will be GAA, A123789 will be BSPD. It did not link to anything from other manufacturer, so the financial fools out there comparing Intel 18A to TSMC A16, the number is meaningless, once the true number coming from the transistor.
Some other TSMC PR researcher also mentioned that TSMC N3P better than Intel 18A, but from the leak clock of Arrow Lake (20A) and with a true increase of silicone area utilization of 6%, these fact/ PR Research Paper make me believes that Intel 20A better than N3P, because these TSMC IR/PR information is not scientific at all, I am treating this as an IR tricks to pop up share price.
If you are saying single patterning yes, it hit the wall, but multi-pattering No. In answering the density issues, on the transistor layer they anyway needed multiple steps / patterning as it needed to build the structure of the transistor i.e. GAA.
The Wall issues is that TSMC felt like they can get away with it with AI (CuLitho), I am not sure, but it is not just High NA we are talking about Applied Materials Sculpta will also help to extend "the wall" mentioned. But TSMC is doing neither of those i.e. No High NA No Sculpta.
"The TSMC density count is based on a ratio of transistor, so Apple M3 or so did not come with the ration that TSMC specify therefore they said they don't know."
I was of the understanding that TSMC used test wafers to determine node density. Others have speculated that it's an ARM design which the calculation is based off of. In any case, we all know that these node numbers are just numbers. It's what the density improvement is that makes a new node new, as opposed to a "+" node like Intel kept doing with 14nm.
Every process node has three orthogonal performance vectors: density, power, and frequency. Various nodes are intentionally developed to optimize one of these, usually at the expense of the others. While Intel took years to get it's "10 nm" node to acceptable yield levels, they still had to ship successive generations of products with at least incremental frequency improvements on the 14 nm process which did yield well. No surprise that they continued to refine the 14 nm process with +, ++, and +++, and took much grief for it. But they did wind up with the world's most speed performant 14 nm process node, although it was too late to be relevant or appreciated.
So, TSMC has assigned new numbers relative to its own numbering, 5 down to 3. That's a 40% smaller dimension. Where in that selection of four already is there an actual density to match? N3-plain looks to be the best at just 5% reduction.
+43% transistor density according to slides and estimates, maybe lower. At least one slide looks obsolete because we know SRAM is not gaining +20%.
SRAM's lack of improvement should be ignored because it has apparently hit a scaling wall and won't shrink much more. Maybe that changes with GAAFETs (N2). If it doesn't, 3D stacking of SRAM is the obvious way forward.
Even if density improvements are slowing, these new nodes can still be valuable, mostly for the power savings. A 35% reduction in power consumption can be very helpful.
Another aspect ist that price is often not included in “better”. Intel's 10 nm node was far from profitable, and this wasn't just a function of yield. If you need more steps to produce said product, you decrease overall throughput. At what point are Intel's nodes profitable? And at what point does Intel get the margins it would like.
Intel is taking more risks than TSMC at the moment, because they have to. Technology-wise, this is pretty cool, their push for BSPDN is particularly important not just for what it is, but what technologies that manufacturing capability will enable in the future. Intel will have to be significantly better and/or cheaper than TSMC to attract volume customers.
Look at how TSMC has ALWAYS done things. They progress slowly, one big step at a time. Coming up, the big steps that matter are - GAA - BSPD - THEN finer lithography via high-HA EUV.
They don't need to get those high-NA EUV machines right now.
Intel is trying to short-circuit the process but look at the details. They claim GAA and BSPD together in 20A, (this year!) followed by 18A (also this year!) Will that happen? Supposedly Arrow Lake will be released before the end of the year on 20A. But already rumors are that most Arrow Lake compute tiles will not be on 20A. so ???
Will Lunar Lake ship in 2025 on 18A? Well, lets start by seeing what happens with Arrow Lake.
Meanwhile even the optimistic Intel roadmaps only put high-NA EUV as 14A at-risk in 2027. So TSMC is (probably) 2025 GAA, so maybe an Apple product SHIPPING in 2025 (probably) 2026 BSPD in TSMC A16 node. Again maybe an Apple product w BSPD in 2026 (maybe) 2028 TSMC A14 w/ high-NA EUV? Again maybe an Apple product w A14 in 2028
These timelines are just not that different, especially if you go by "When can I buy the product in Best Buy?" (one week after Apple announcement, often one year after Intel announcement).
Yes, agreed, TSMC is taking a more cautious approach, introducing one key new tech per node if they can. Intel is pushing hard to make up lost ground. Then you have projects like Rapidus that have a low probability of success, but too much talent and funding to ignore and dismiss outright. IMHO it is an exciting time to be in the semiconductor industry.
Regarding high-NA EUV, according to Semianalysis' cost model, it will be more expensive than if you used NA = 0.33 steppers instead. Some products like nVidia's compute dies (which almost fills the entire reticle) would either require stitching or a rethink of the architecture to allow for chiplets.
He claims to see parts of the Apple A17 LOGIC that are 217 to 227 MTr/mm^2. This is about 65% over N5. That's also about what TSMC predicted which was around 1.7x
He also has numbers for SRAM density, and various asides about parts of the die that are unused, providing the seal ring, scribe crack isolation, or voltage block isolation (which are all relevant if you want to generate a ballpark number by dividing number of transistors (usually known, since Apple usually tells us that) by chip "area" (the relevant area is rather less than the height*width you see when you decap the chip...)
Of course SRAM has moved much less; we all knew this was coming before N3, we all know it after N3. That doesn't stop the usual idiots from making claims about how N3 buys you zero improved transistor density, TSMC lying, blah blah.
The thing you have to look at whenever you see these claims is - are they talking about TRANSISTOR density or LOGIC density? - are they comparing to what TSMC said about TRANSISTOR density or about LOGIC density?
But those Fake News media i.e. MLID mentioned that Intel Lunar Lake is based on N3B, if Intel Lunar Lake / part of Lunar Lake is N3B then it is not an Apple specific node, although in my mind this is still a failed Node. Is your article and using some logics can conclude that MLID is fake new media, Intel Lunar Lake will not be based on TSMC N3 (Compute Tile)
This is why I commented on the other post saying that "ha TSMC is slow but we are okay we gain Qualcomm as the customer"
As you mentioned EDA compatible, because 2-3 years ago, Intel did mentioned that Qualcomm is special, they will co-develop using 20A, then if you look forward to now, Intel 20A is already is (if not already) pre-ramping. So if Qualcomm stuck with Intel, they already having a better node than its competitor i.e. TSMC N3E Vs Intel 20A. But Qualcomm do not want to invest, and please do not blame on Pat and Intel, they delivery but Qualcomm don't know what they sign up for, they don't want PSPD and GAA in 2024, they want FinEFT, they should have sign up for Intel 3.
Intel 20A is not for foundry business, it is just an internal node. It lacks a lot of IP and stuff. You can't make a whole mobile SoC using a half backed node.
How do we know that 20A is a better node than N3E? And by what criteria? Intel's first 10 nm products showed clock speed regressions compared with 14++(+). A new transistor type does not necessarily mean better performance in its initial incarnation (vs. a highly-optimized FinFET design).
I'd reserve judgement until we see products on the market, and we get yield numbers.
From now on, designs will have to be more exotic. Caches still do not shrink with new nodes. AMD should continue applying its strategy with 6nm chiplets for caches.
I wonder if adding Samsung to the equation would be viable at this point.
I'm not sure SRAM shrinks between N7 which it's on now and N6. But they could end up on N6 if N7 production winds down.
What I want to see next is multiple layers. The 3D V-Cache chiplets are currently one single layer consisting of 64 MiB, but it's known they could stack additional layers. That comes at a greater cost, but it could become a good way to upsell to a flagship.
AFAIK scaling of memory cells is limited by scaling the capacitors. Simply put, they are very, very tall and have a very narrow base (they have a high aspect ratio). Increasing the aspect ratio (height-to-width) is difficult to impossible.
That is why memory manufacturers have their own process nodes with their own naming conventions, which typically make no reference to some size.
Let me put it this way. It's known that SRAM scaling has almost completely halted at around 0.02 µm² (SRAM bitcell size) as of N5/N3, with TSMC even choosing to regress slightly (around 5%) on some of the sub-nodes.
What I don't know is if there is any difference between N7 and N6, which shrinks logic by 18%. I think the answer is no, so what is the benefit making cache chiplets on N6 instead of N7? Probably nothing. So I'm not sure why Terry is talking about N6 cache chiplets. Both 5800X3D and 7000X3D use N7 for V-Cache.
N7 is at 0.027 µm², so there would be a scaling benefit from moving to any of the N5/N4/N3 nodes. But the capacity might not be available and it might not be worth the cost.
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ballsystemlord - Wednesday, May 15, 2024 - link
I'm kinda surprised that the chip density numbers for N3 and N3E are still not known despite being in mass production for some time now.evanh - Wednesday, May 15, 2024 - link
What little info is there suggests it's not really different from the N5's. Which is a tad embarrassing given the rather relatively large step in node numbering.I guess they're already up against the wall without high-NA equipment. That doesn't bode well.
evanh - Wednesday, May 15, 2024 - link
Speaking of, 100% of all High-NA shipments are destined for USA this year. Line #2 already went to an unnamed recipient, speculated to be an IBM affiliated research facility. Speculating ... Maybe next year's batch goes to US based new fabs for TSMC, Samsung and co ... EU might get a look in since they're building the stuff ... nothing for Japan, Taiwan or Korea.my_wing - Wednesday, May 15, 2024 - link
No TSMC will not install its first EUV High NA machine in the US, it has to be in Taiwan, they build a billion dollar research lab there, just like what Intel is doing.EU is not might get a look, EU is going to get one in 2027, that is Intel Germany, it takes 3 months to set the machine up (although is the new one i.e. take longer but the machine arrived in the US in Dec 2023 and only in weeks time that first lights-on), the schedule is that Q4 2027 Germany online i.e. the machine needed to be there Q1 2027, assuming there isn't just 1 EUV machine.
The TSMC density count is based on a ratio of transistor, so Apple M3 or so did not come with the ration that TSMC specify therefore they said they don't know.
N5/N3ABCXYZ they all just marketing name, basically is optimized FinFET, N2ABCXYZ is just the segment that will be GAA, A123789 will be BSPD. It did not link to anything from other manufacturer, so the financial fools out there comparing Intel 18A to TSMC A16, the number is meaningless, once the true number coming from the transistor.
Some other TSMC PR researcher also mentioned that TSMC N3P better than Intel 18A, but from the leak clock of Arrow Lake (20A) and with a true increase of silicone area utilization of 6%, these fact/ PR Research Paper make me believes that Intel 20A better than N3P, because these TSMC IR/PR information is not scientific at all, I am treating this as an IR tricks to pop up share price.
If you are saying single patterning yes, it hit the wall, but multi-pattering No. In answering the density issues, on the transistor layer they anyway needed multiple steps / patterning as it needed to build the structure of the transistor i.e. GAA.
The Wall issues is that TSMC felt like they can get away with it with AI (CuLitho), I am not sure, but it is not just High NA we are talking about Applied Materials Sculpta will also help to extend "the wall" mentioned. But TSMC is doing neither of those i.e. No High NA No Sculpta.
ballsystemlord - Wednesday, May 15, 2024 - link
"The TSMC density count is based on a ratio of transistor, so Apple M3 or so did not come with the ration that TSMC specify therefore they said they don't know."I was of the understanding that TSMC used test wafers to determine node density. Others have speculated that it's an ARM design which the calculation is based off of. In any case, we all know that these node numbers are just numbers. It's what the density improvement is that makes a new node new, as opposed to a "+" node like Intel kept doing with 14nm.
dwbogardus - Thursday, May 16, 2024 - link
Every process node has three orthogonal performance vectors: density, power, and frequency. Various nodes are intentionally developed to optimize one of these, usually at the expense of the others. While Intel took years to get it's "10 nm" node to acceptable yield levels, they still had to ship successive generations of products with at least incremental frequency improvements on the 14 nm process which did yield well. No surprise that they continued to refine the 14 nm process with +, ++, and +++, and took much grief for it. But they did wind up with the world's most speed performant 14 nm process node, although it was too late to be relevant or appreciated.evanh - Thursday, May 16, 2024 - link
So, TSMC has assigned new numbers relative to its own numbering, 5 down to 3. That's a 40% smaller dimension. Where in that selection of four already is there an actual density to match? N3-plain looks to be the best at just 5% reduction.nandnandnand - Thursday, May 16, 2024 - link
https://fuse.wikichip.org/news/7048/n3e-replaces-n...https://en.wikipedia.org/wiki/5_nm_process
https://en.wikipedia.org/wiki/3_nm_process
+43% transistor density according to slides and estimates, maybe lower. At least one slide looks obsolete because we know SRAM is not gaining +20%.
SRAM's lack of improvement should be ignored because it has apparently hit a scaling wall and won't shrink much more. Maybe that changes with GAAFETs (N2). If it doesn't, 3D stacking of SRAM is the obvious way forward.
Even if density improvements are slowing, these new nodes can still be valuable, mostly for the power savings. A 35% reduction in power consumption can be very helpful.
Terry_Craig - Thursday, May 16, 2024 - link
Yeah, It's a bit unrealistic, CPU and GPUs currently have large amounts of cache: https://locuza.substack.com/p/nvidias-ada-lineup-c...https://cdn.wccftech.com/wp-content/uploads/2020/1...
In certain cases, cache occupies more than 50% of the die.
OreoCookie - Saturday, May 18, 2024 - link
Another aspect ist that price is often not included in “better”. Intel's 10 nm node was far from profitable, and this wasn't just a function of yield. If you need more steps to produce said product, you decrease overall throughput. At what point are Intel's nodes profitable? And at what point does Intel get the margins it would like.Intel is taking more risks than TSMC at the moment, because they have to. Technology-wise, this is pretty cool, their push for BSPDN is particularly important not just for what it is, but what technologies that manufacturing capability will enable in the future. Intel will have to be significantly better and/or cheaper than TSMC to attract volume customers.
OreoCookie - Saturday, May 18, 2024 - link
If true, that does not bode well for Rapidus and their, hmmm, ambitious timeline.name99 - Thursday, May 16, 2024 - link
Look at how TSMC has ALWAYS done things. They progress slowly, one big step at a time.Coming up, the big steps that matter are
- GAA
- BSPD
- THEN finer lithography via high-HA EUV.
They don't need to get those high-NA EUV machines right now.
Intel is trying to short-circuit the process but look at the details.
They claim GAA and BSPD together in 20A, (this year!) followed by 18A (also this year!)
Will that happen? Supposedly Arrow Lake will be released before the end of the year on 20A. But already rumors are that most Arrow Lake compute tiles will not be on 20A. so ???
Will Lunar Lake ship in 2025 on 18A? Well, lets start by seeing what happens with Arrow Lake.
Meanwhile even the optimistic Intel roadmaps only put high-NA EUV as 14A at-risk in 2027.
So TSMC is
(probably) 2025 GAA, so maybe an Apple product SHIPPING in 2025
(probably) 2026 BSPD in TSMC A16 node. Again maybe an Apple product w BSPD in 2026
(maybe) 2028 TSMC A14 w/ high-NA EUV? Again maybe an Apple product w A14 in 2028
These timelines are just not that different, especially if you go by "When can I buy the product in Best Buy?" (one week after Apple announcement, often one year after Intel announcement).
OreoCookie - Sunday, May 19, 2024 - link
Yes, agreed, TSMC is taking a more cautious approach, introducing one key new tech per node if they can. Intel is pushing hard to make up lost ground. Then you have projects like Rapidus that have a low probability of success, but too much talent and funding to ignore and dismiss outright. IMHO it is an exciting time to be in the semiconductor industry.Regarding high-NA EUV, according to Semianalysis' cost model, it will be more expensive than if you used NA = 0.33 steppers instead. Some products like nVidia's compute dies (which almost fills the entire reticle) would either require stitching or a rethink of the architecture to allow for chiplets.
name99 - Thursday, May 16, 2024 - link
https://www.youtube.com/watch?v=veikj5uvAc8(Chinese, but with subtitles) gives some numbers.
He claims to see parts of the Apple A17 LOGIC that are 217 to 227 MTr/mm^2. This is about 65% over N5. That's also about what TSMC predicted which was around 1.7x
He also has numbers for SRAM density, and various asides about parts of the die that are unused, providing the seal ring, scribe crack isolation, or voltage block isolation (which are all relevant if you want to generate a ballpark number by dividing number of transistors (usually known, since Apple usually tells us that) by chip "area" (the relevant area is rather less than the height*width you see when you decap the chip...)
Of course SRAM has moved much less; we all knew this was coming before N3, we all know it after N3. That doesn't stop the usual idiots from making claims about how N3 buys you zero improved transistor density, TSMC lying, blah blah.
The thing you have to look at whenever you see these claims is
- are they talking about TRANSISTOR density or LOGIC density?
- are they comparing to what TSMC said about TRANSISTOR density or about LOGIC density?
my_wing - Wednesday, May 15, 2024 - link
Just a food for though from this article.TSMC N3B to N3E need a redesign.
But those Fake News media i.e. MLID mentioned that Intel Lunar Lake is based on N3B, if Intel Lunar Lake / part of Lunar Lake is N3B then it is not an Apple specific node, although in my mind this is still a failed Node. Is your article and using some logics can conclude that MLID is fake new media, Intel Lunar Lake will not be based on TSMC N3 (Compute Tile)
This is why I commented on the other post saying that "ha TSMC is slow but we are okay we gain Qualcomm as the customer"
As you mentioned EDA compatible, because 2-3 years ago, Intel did mentioned that Qualcomm is special, they will co-develop using 20A, then if you look forward to now, Intel 20A is already is (if not already) pre-ramping. So if Qualcomm stuck with Intel, they already having a better node than its competitor i.e. TSMC N3E Vs Intel 20A. But Qualcomm do not want to invest, and please do not blame on Pat and Intel, they delivery but Qualcomm don't know what they sign up for, they don't want PSPD and GAA in 2024, they want FinEFT, they should have sign up for Intel 3.
Lodix - Thursday, May 16, 2024 - link
Intel 20A is not for foundry business, it is just an internal node. It lacks a lot of IP and stuff. You can't make a whole mobile SoC using a half backed node.OreoCookie - Saturday, May 18, 2024 - link
How do we know that 20A is a better node than N3E? And by what criteria? Intel's first 10 nm products showed clock speed regressions compared with 14++(+). A new transistor type does not necessarily mean better performance in its initial incarnation (vs. a highly-optimized FinFET design).I'd reserve judgement until we see products on the market, and we get yield numbers.
Terry_Craig - Thursday, May 16, 2024 - link
From now on, designs will have to be more exotic. Caches still do not shrink with new nodes. AMD should continue applying its strategy with 6nm chiplets for caches.I wonder if adding Samsung to the equation would be viable at this point.
nandnandnand - Saturday, May 18, 2024 - link
I'm not sure SRAM shrinks between N7 which it's on now and N6. But they could end up on N6 if N7 production winds down.What I want to see next is multiple layers. The 3D V-Cache chiplets are currently one single layer consisting of 64 MiB, but it's known they could stack additional layers. That comes at a greater cost, but it could become a good way to upsell to a flagship.
OreoCookie - Sunday, May 19, 2024 - link
AFAIK scaling of memory cells is limited by scaling the capacitors. Simply put, they are very, very tall and have a very narrow base (they have a high aspect ratio). Increasing the aspect ratio (height-to-width) is difficult to impossible.That is why memory manufacturers have their own process nodes with their own naming conventions, which typically make no reference to some size.
nandnandnand - Monday, May 20, 2024 - link
Let me put it this way. It's known that SRAM scaling has almost completely halted at around 0.02 µm² (SRAM bitcell size) as of N5/N3, with TSMC even choosing to regress slightly (around 5%) on some of the sub-nodes.What I don't know is if there is any difference between N7 and N6, which shrinks logic by 18%. I think the answer is no, so what is the benefit making cache chiplets on N6 instead of N7? Probably nothing. So I'm not sure why Terry is talking about N6 cache chiplets. Both 5800X3D and 7000X3D use N7 for V-Cache.
N7 is at 0.027 µm², so there would be a scaling benefit from moving to any of the N5/N4/N3 nodes. But the capacity might not be available and it might not be worth the cost.
https://fuse.wikichip.org/news/7343/iedm-2022-did-...
https://www.tomshardware.com/news/amd-shares-new-s...