I have read that thin but solid glass substrates are being considered for the structural support as opposed to the polymer (fiberglass) materials used for many years. They are quite dimensionally stable, and have a TCE similar to silicon. They will need "through-glass vias" for I/O and power to get from the chip to the socket.
according to Applied Materials presentation the connection point of BSPD is using Tungsten / Cobalt as Cobalt is more rare and from Intel 10nm experience quiet difficult to master, Tungsten as a change is most likely.
"But at the same time, it's important to underscore that A16 isn't just N2P renamed, but rather it will be a distinct technology from N2P."
I think the elements of this explain what happened.
BSPD requires somewhat more rethinking of chip layout than many previous node improvements (for example I've seen some Apple patents for alternative SRAM cache layouts that exploit BSPD). My guess is that some customers told TSMC that, rather than having the next upgrade to N2 (ie N2P) based on BSPD, they'd prefer an "easy" optical-shrink-style upgraded node, with BSPD placed on a different track, one that requires a new design rather than a slightly updated design. ie this is not about "failure" or "slowing down", it's about TSMC being responsive to customers, the same attitude that got them to number one, and that keeps them there. Same reason that there's a "Mainstream" TSMC track with nodes like N4P and N3P that are "easy" upgrades for existing customer designs.
What they (CC Wei@TSMC) actually painting the picture is that: TSMC version of BSPD is better than PowerVia@Intel. "Super" In layman's term BSPD connect power from the backside to 1 of the 3 layers and/or location. (order in terms of performance / complexity) On top of the silicon i.e. M0 Metal Layer Same layer of the silicon i.e. PowerVIA On the bottom of the Silicon i.e. TSMC "Super"
They trying to tell us that because they are "Super" then is Okay, we are "In CC Wei@TSMC" mouth as we are paperly and PowerPoint wise ahead of Intel.
Then they say because we are slow, we gain Qualcomm as their customer. Is okay. From the Intel point of view, Intel actual silver bullet is Intel ARC, as battlemage is coming to launching cycle, Celestial should be is full steam development, if battlemage successfully captured a significant low end market with 10% GP, i.e. my take is that the top battlemage will be 10-15% more expensive as current ARC is losing money, but the driver and everything is going to be improving continuously (Pat was the CEO of VMware, no doubt he can execute here). Then Celestial will be based on Intel 3 E and the SoC will also be based on Intel 3 E, then Intel will leave TSMC (effectively). As an Intel Watcher and as an qualified accountant, I can tell you is that Intel earning estimate always is conservative, take a gain of salt when they say Intel foundry will be money losing for 3 years, more likely in 2026 will breakeven as Celestial Ramp.
What TSMC is saying is that they are implementing the "Backside Contact to S/D", what CC Wei@TSMC did is that he copy Page 32 of the Applied Material PowerPoint and owned it by comparing the performance of A16 to N2P, which now most of the people outside TSMC thinks N2P will have have any sort of BSPD. And there is no data (technical) to verify what is told.
On the other hand, it is little to no surprise if you signed a non-disclose agreement, you will gain access to Arrow Lake as of now. As they try to paper launch it in Dec 2024.
TSMC@Chang is not suck, it is the best managed company, I personally invested into it and earned 400% return, I also really hope that TSMC will make it. For the greater the love comes with greater the anger. I think, please let Chang come back, take CC Wei Off, as there is none that CC Wei done was really going well, TSMC N3B technically late/failure (off by year), now TSMC "True" N2P is become A16 and push out for another year.
The point is that Bob Swan@Intel, already given you the golden opportunities, not like from 70s to 10s where Intel is always 1-2 nodes ahead, it is good for competition and customer.
CC Wei needed to answer a couple of question to justify his move, the (new) CEO of ASML and CEO of Applied Materials should asked the questions to CC Wei (if not already). How is your CULitho works, is AI the silver bullet to be the next best thing in Litho? What is your plan to continuously scale down if CULitho is working? Will it be better you allow another foundry (except Intel) so that we can work the High EUV NA in, isn't 2030 is just too unreal? What is your manufacturing plan in Germany, because you suffer so much in the US, do you think that you can handle the added regulation of the EU, e.g. the new Intel German Fab hit ruins site and had to delay until the site is become suitable for construction, does TSMC have the planning as a package to operate outside of Asia?
Each of those is a multi-Billion dollar questions, I don't think CC Wei and the Management of TSMC is answering these.
So it is not TSMC sucks and Intel rules, be honest, I see something, it make sense, the market not make sense, at the end, the market will balance itself out, for those can see a clear picture, will be rewarded, I remember when I invest in TSMC, every big banks is downgrading like crazy in my mind, and at the end, I make 400% profit (ex div), with the company for 5-6 years, not bad.
This *could* provide a small opening for Intel. Intel has BSPD in their 2nm-class node, and if they can get some foundry customers now based on the improvements due to that, it will provide those customers an easy migration to their "14A" node which presumably has the same features. On the other hand, now that TSMC has bailed on BSPD for 2nm, it provides THEIR customers an easier path from 4/3 to 2, so they are less likely to lose those customers to Intel. It's very interesting.
A16 *is* N2P-SPR renamed (to match Intel?), with the schedule brought in. The transistor and topside metal design rules are the same as N2P. The area and speed improvements are for HPC chips with dense power grids.
<blockquote>The company was initially slated to offer BSPDN technology with N2P in 2026, but for reasons that aren't entirely clear, the tech has been punted from N2P and moved to A16.</blockquote> Well, it seems quite easy to understand what they did. They planned a new PP they name N2 with Back Side Power which was going to be available in 2026 as for their roadmap. They thought that being so ahead of Intel that was still stuck with their disastrous 10nm class PP would have given them enough advantage to slip a new PP with advanced features up to that date. They thought that a year late N3 was not a problem so a further year late N2 (with proper new techs) would also not be. So Back Side Power delivery has been adopted to be ready not earlier than 2026 (engineering generally needs its own time even if you put 10.000 men doing the job) and that is the date (at best, anything may always go not as planned).
Unfortunately for them, once Intel got rid of that catastrophic PP and started investing in the new advanced PP with a step by step method (like TSMC had done) they have shown an acceleration that could not be foresaw. In less that 3 year Intel has almost closed the gap and is now launched to surpass TSMC with High NA-EUV, PowerVia and more advanced packaging (High NA-EUV is another thing TSMC is going to be left behind). TSMC has foreseen that in 2025/2026 some customer may find Intel PPs much better for them, both under the point of technology but also availability, when Apple constantly usurps TSMC top node just for itself leaving almost nothing to others. So what they did just not to be without anything new for almost 2 years? They simply created an intermediary PP which is now called N2 and renamed the old N2 in A16 (how original!). The new N2 is simply a small optical shrink (maybe achieved by adding more and more multi patterning layer) with no other particular innovations which is just there to attract customers that do not want to completely redesign a chip for the new technologies available by the competitor. Will they succeed in that? Well, if Intel is able to offer a PP which is even similar to that offered by TSMC but with the production capabilities that TSMC cannot provide (due to Apple, as already said), I think many current customers will migrate to Intel PP to be able to advance to the latest nodes. One of them may be Nvidia, that had to release Blackwell with N4 instead of N3 because TSMC cannot offer it to anyone but Apple (and it seems it is not going that well in terms of yields with Apple now paying only the good chips). Qualcomm, Mediatek and others could follow.
No, N2 is NOT a "simply a small optical shrink" which shows your analysis is utterly worthless. The point of N2, the tech that it will prototype, is GAA.
TSMC is doing what they ALWAYS do, introducing a new technology in the context of an otherwise mostly unchanged stack, so as to minimize risk. Same way they introduced finFET as "N16", on top of what was mostly the N20 technology stack. Same reason they are not introducing BSPD in the same process that they introduce GAA.
They need to anticipate part of the innovations they wanted to offer together in the same original N2 which they wanted to offer in 2026 (as of old roadmap). But as said Intel is advancing too fast even for them, so they need to provide something meanwhile the BDPD becomes available. Also, their original numbers with respect to N3 were very different (much worse) while now without BSPD they are giving better relative enhancements. I suppose this move is just for trying to keep customers but in reality they will not achieve them initially. It is all in the same information TSMC just gave themselves. Ignoring one part to accept the other is just cherry picking what we want to believe to.
Facts are that TSMC changed its plans to offer less technology earlier but incredibly with better enhancements than they announced with the PP with all new technologies together. This shows something is amiss, be it the sudden change of date for a different PP with the same name or for the data provided. At the end it seems Intel is really scaring TSMC which is now late on many crucial new technologies.
Apart from the switch to GAAFETs, which name_99 has already mentioned, you wrote that Intel is ahead of TSMC when it comes to high-NA EUV. I think we need to consider cost here, adoption of high-NA EUV will lead to much higher cost and e. g. Semianalysis’ cost analysis states that high-NA EUV becomes economically viable much later than when it is slated for HV production at Intel. Maybe Intel is right and TSMC wrong, but it isn’t as clear cut. What use is a technologically superior but financially ruinous node to Intel? It also would most likely mean that designs need to fit in half a pre-high-NA reticle. Apple’s Max-series chips would be too large, for instance. A chip with the same (or larger) total area would need chiplets connected by EMIB or an interposer.
Intel is making a bet, because they have to, while TSMC is playing it safer. Or perhaps Intel wants to attract customers like Apple that are willing and able to pay extra. I like the added competition. Intel is hungry and ambitious. Success is not guaranteed, but I think they are playing their cards well. But so is TSMC.
High NA EUV is suffered by the same thing when EUV started "Light source" i.e. the increase power to Light source to make the through put faster.
The point is that the High NA EUV machine Intel is having now is not a production lab, what is doing is that they "Intel and ASML" try to test all the system settings and as the Late Paul Otellini (Tick Tok@intel) copy exact to production sites.
I saw what you say i.e. the SemiAnalysis, that website to me sound too much like an TSMC PR. They can even say that TSMC N3P is better than Intel 18A. I am speechless, the most speechless is that Intel arrow lake should be in the Non Disclose Agreement Channel before the article written. Now that Rumor and "leaked" benchmark indicate that Arrow Lake Clock @ 5.5 GHz, sorry, where is TSMC lead, Size (remember BSPD lead to Gain of 6-10% so I don't see N3P can be denser than 18A).
Back to the point High-NA EUV, ASML (new) CEO already mentioned that their machine ever produce 80% still in production. The most critical point of economics here is throughput, ASML mentioned that they will continuous support and upgrade i.e. light source; in these world there are too many people going for hypes, even Bloomberg "Oh the US surrender the EUV opportunities La La La, but the US is still the supplier of the EUV light source to ASML.
I am a qualified accountant, when talk about EUV cost I am also an expert, the EUV machine at Intel should not be more than and Developmental machines, testing our processes, introducing 14A, 10A, etc etc. testing out new customer mask etc etc. even the throughput is slow, it just not that matter.
The report ignore the fact that the Light source will be continuously upgrade and the module will be replace (light source I think is similar to light bulb needed to replace after useful life), then the new upgraded module will be install and the through put is going to be higher.
Next bit is High EUV NA and the size of the mask, that Intel is carry on hoping ASML can address.
Overall because light source is modular, the author in SemiAnalysis do not take it into account and based on current throughput, that is a big mistake.
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Threska - Thursday, April 25, 2024 - link
Backside Power Delivery is the future although I suspect manufacturing will have to change quite a bit with silicon no longer in the support role.https://youtu.be/hyZlQY2xmWQ
dwbogardus - Friday, April 26, 2024 - link
I have read that thin but solid glass substrates are being considered for the structural support as opposed to the polymer (fiberglass) materials used for many years. They are quite dimensionally stable, and have a TCE similar to silicon. They will need "through-glass vias" for I/O and power to get from the chip to the socket.my_wing - Monday, April 29, 2024 - link
Don't Mix packing to on die with BSPDaccording to Applied Materials presentation the connection point of BSPD is using Tungsten / Cobalt as Cobalt is more rare and from Intel 10nm experience quiet difficult to master, Tungsten as a change is most likely.
https://ir.appliedmaterials.com/static-files/b418f...
name99 - Thursday, April 25, 2024 - link
"But at the same time, it's important to underscore that A16 isn't just N2P renamed, but rather it will be a distinct technology from N2P."I think the elements of this explain what happened.
BSPD requires somewhat more rethinking of chip layout than many previous node improvements (for example I've seen some Apple patents for alternative SRAM cache layouts that exploit BSPD).
My guess is that some customers told TSMC that, rather than having the next upgrade to N2 (ie N2P) based on BSPD, they'd prefer an "easy" optical-shrink-style upgraded node, with BSPD placed on a different track, one that requires a new design rather than a slightly updated design.
ie this is not about "failure" or "slowing down", it's about TSMC being responsive to customers, the same attitude that got them to number one, and that keeps them there. Same reason that there's a "Mainstream" TSMC track with nodes like N4P and N3P that are "easy" upgrades for existing customer designs.
my_wing - Monday, April 29, 2024 - link
What they (CC Wei@TSMC) actually painting the picture is that:TSMC version of BSPD is better than PowerVia@Intel. "Super"
In layman's term BSPD connect power from the backside to 1 of the 3 layers and/or location. (order in terms of performance / complexity)
On top of the silicon i.e. M0 Metal Layer
Same layer of the silicon i.e. PowerVIA
On the bottom of the Silicon i.e. TSMC "Super"
They trying to tell us that because they are "Super" then is Okay, we are "In CC Wei@TSMC" mouth as we are paperly and PowerPoint wise ahead of Intel.
Then they say because we are slow, we gain Qualcomm as their customer. Is okay. From the Intel point of view, Intel actual silver bullet is Intel ARC, as battlemage is coming to launching cycle, Celestial should be is full steam development, if battlemage successfully captured a significant low end market with 10% GP, i.e. my take is that the top battlemage will be 10-15% more expensive as current ARC is losing money, but the driver and everything is going to be improving continuously (Pat was the CEO of VMware, no doubt he can execute here). Then Celestial will be based on Intel 3 E and the SoC will also be based on Intel 3 E, then Intel will leave TSMC (effectively). As an Intel Watcher and as an qualified accountant, I can tell you is that Intel earning estimate always is conservative, take a gain of salt when they say Intel foundry will be money losing for 3 years, more likely in 2026 will breakeven as Celestial Ramp.
name99 - Tuesday, April 30, 2024 - link
Does anyone have a clue what the above is supposed to mean?I think the message is "TSMC sucks, Intel rules", but beyond that I am lost.
my_wing - Wednesday, May 1, 2024 - link
Don't just come in with simple things, like Oh Fanboy, Bias La La La.I already provide with a very simple explanation, where 90% of us is, we are not all earning a living from making semi-conductor.
https://ir.appliedmaterials.com/static-files/b418f...
The presentation is already shared above, should I needed to repeat that and if you look at page 32, to sum it in short is what I have said.
What TSMC is saying is that they are implementing the "Backside Contact to S/D", what CC Wei@TSMC did is that he copy Page 32 of the Applied Material PowerPoint and owned it by comparing the performance of A16 to N2P, which now most of the people outside TSMC thinks N2P will have have any sort of BSPD. And there is no data (technical) to verify what is told.
On the other hand, it is little to no surprise if you signed a non-disclose agreement, you will gain access to Arrow Lake as of now. As they try to paper launch it in Dec 2024.
TSMC@Chang is not suck, it is the best managed company, I personally invested into it and earned 400% return, I also really hope that TSMC will make it. For the greater the love comes with greater the anger. I think, please let Chang come back, take CC Wei Off, as there is none that CC Wei done was really going well, TSMC N3B technically late/failure (off by year), now TSMC "True" N2P is become A16 and push out for another year.
The point is that Bob Swan@Intel, already given you the golden opportunities, not like from 70s to 10s where Intel is always 1-2 nodes ahead, it is good for competition and customer.
CC Wei needed to answer a couple of question to justify his move, the (new) CEO of ASML and CEO of Applied Materials should asked the questions to CC Wei (if not already).
How is your CULitho works, is AI the silver bullet to be the next best thing in Litho?
What is your plan to continuously scale down if CULitho is working?
Will it be better you allow another foundry (except Intel) so that we can work the High EUV NA in, isn't 2030 is just too unreal?
What is your manufacturing plan in Germany, because you suffer so much in the US, do you think that you can handle the added regulation of the EU, e.g. the new Intel German Fab hit ruins site and had to delay until the site is become suitable for construction, does TSMC have the planning as a package to operate outside of Asia?
Each of those is a multi-Billion dollar questions, I don't think CC Wei and the Management of TSMC is answering these.
So it is not TSMC sucks and Intel rules, be honest, I see something, it make sense, the market not make sense, at the end, the market will balance itself out, for those can see a clear picture, will be rewarded, I remember when I invest in TSMC, every big banks is downgrading like crazy in my mind, and at the end, I make 400% profit (ex div), with the company for 5-6 years, not bad.
do_not_arrest - Friday, April 26, 2024 - link
This *could* provide a small opening for Intel. Intel has BSPD in their 2nm-class node, and if they can get some foundry customers now based on the improvements due to that, it will provide those customers an easy migration to their "14A" node which presumably has the same features. On the other hand, now that TSMC has bailed on BSPD for 2nm, it provides THEIR customers an easier path from 4/3 to 2, so they are less likely to lose those customers to Intel. It's very interesting.nandnandnand - Friday, April 26, 2024 - link
Slow and steady vs. Steady delaysmy_wing - Monday, April 29, 2024 - link
Slow and Steady (Pat@Intel) Vs Steady delays (CC Wei@TSMC)Slow and Steday (Chang@TSMC) Vs Steady delay (Bob Swan@Intel)
ijdat - Saturday, April 27, 2024 - link
A16 *is* N2P-SPR renamed (to match Intel?), with the schedule brought in. The transistor and topside metal design rules are the same as N2P. The area and speed improvements are for HPC chips with dense power grids.Rudde - Monday, April 29, 2024 - link
Yeah, it feels like a response to Intel renaming nodes. Essentially, A16 is a half-node to compete with Intel's 18A and 14A (half-)nodes.CiccioB - Tuesday, April 30, 2024 - link
<blockquote>The company was initially slated to offer BSPDN technology with N2P in 2026, but for reasons that aren't entirely clear, the tech has been punted from N2P and moved to A16.</blockquote>Well, it seems quite easy to understand what they did.
They planned a new PP they name N2 with Back Side Power which was going to be available in 2026 as for their roadmap.
They thought that being so ahead of Intel that was still stuck with their disastrous 10nm class PP would have given them enough advantage to slip a new PP with advanced features up to that date. They thought that a year late N3 was not a problem so a further year late N2 (with proper new techs) would also not be. So Back Side Power delivery has been adopted to be ready not earlier than 2026 (engineering generally needs its own time even if you put 10.000 men doing the job) and that is the date (at best, anything may always go not as planned).
Unfortunately for them, once Intel got rid of that catastrophic PP and started investing in the new advanced PP with a step by step method (like TSMC had done) they have shown an acceleration that could not be foresaw.
In less that 3 year Intel has almost closed the gap and is now launched to surpass TSMC with High NA-EUV, PowerVia and more advanced packaging (High NA-EUV is another thing TSMC is going to be left behind).
TSMC has foreseen that in 2025/2026 some customer may find Intel PPs much better for them, both under the point of technology but also availability, when Apple constantly usurps TSMC top node just for itself leaving almost nothing to others.
So what they did just not to be without anything new for almost 2 years?
They simply created an intermediary PP which is now called N2 and renamed the old N2 in A16 (how original!).
The new N2 is simply a small optical shrink (maybe achieved by adding more and more multi patterning layer) with no other particular innovations which is just there to attract customers that do not want to completely redesign a chip for the new technologies available by the competitor.
Will they succeed in that? Well, if Intel is able to offer a PP which is even similar to that offered by TSMC but with the production capabilities that TSMC cannot provide (due to Apple, as already said), I think many current customers will migrate to Intel PP to be able to advance to the latest nodes. One of them may be Nvidia, that had to release Blackwell with N4 instead of N3 because TSMC cannot offer it to anyone but Apple (and it seems it is not going that well in terms of yields with Apple now paying only the good chips). Qualcomm, Mediatek and others could follow.
name99 - Tuesday, April 30, 2024 - link
No, N2 is NOT a "simply a small optical shrink" which shows your analysis is utterly worthless.The point of N2, the tech that it will prototype, is GAA.
TSMC is doing what they ALWAYS do, introducing a new technology in the context of an otherwise mostly unchanged stack, so as to minimize risk. Same way they introduced finFET as "N16", on top of what was mostly the N20 technology stack. Same reason they are not introducing BSPD in the same process that they introduce GAA.
CiccioB - Tuesday, April 30, 2024 - link
They need to anticipate part of the innovations they wanted to offer together in the same original N2 which they wanted to offer in 2026 (as of old roadmap).But as said Intel is advancing too fast even for them, so they need to provide something meanwhile the BDPD becomes available.
Also, their original numbers with respect to N3 were very different (much worse) while now without BSPD they are giving better relative enhancements.
I suppose this move is just for trying to keep customers but in reality they will not achieve them initially.
It is all in the same information TSMC just gave themselves. Ignoring one part to accept the other is just cherry picking what we want to believe to.
Facts are that TSMC changed its plans to offer less technology earlier but incredibly with better enhancements than they announced with the PP with all new technologies together. This shows something is amiss, be it the sudden change of date for a different PP with the same name or for the data provided.
At the end it seems Intel is really scaring TSMC which is now late on many crucial new technologies.
OreoCookie - Saturday, May 4, 2024 - link
Apart from the switch to GAAFETs, which name_99 has already mentioned, you wrote that Intel is ahead of TSMC when it comes to high-NA EUV. I think we need to consider cost here, adoption of high-NA EUV will lead to much higher cost and e. g. Semianalysis’ cost analysis states that high-NA EUV becomes economically viable much later than when it is slated for HV production at Intel. Maybe Intel is right and TSMC wrong, but it isn’t as clear cut. What use is a technologically superior but financially ruinous node to Intel? It also would most likely mean that designs need to fit in half a pre-high-NA reticle. Apple’s Max-series chips would be too large, for instance. A chip with the same (or larger) total area would need chiplets connected by EMIB or an interposer.Intel is making a bet, because they have to, while TSMC is playing it safer. Or perhaps Intel wants to attract customers like Apple that are willing and able to pay extra. I like the added competition. Intel is hungry and ambitious. Success is not guaranteed, but I think they are playing their cards well. But so is TSMC.
my_wing - Wednesday, May 8, 2024 - link
As you guys said, do some more research.High NA EUV is suffered by the same thing when EUV started "Light source" i.e. the increase power to Light source to make the through put faster.
The point is that the High NA EUV machine Intel is having now is not a production lab, what is doing is that they "Intel and ASML" try to test all the system settings and as the Late Paul Otellini (Tick Tok@intel) copy exact to production sites.
I saw what you say i.e. the SemiAnalysis, that website to me sound too much like an TSMC PR. They can even say that TSMC N3P is better than Intel 18A. I am speechless, the most speechless is that Intel arrow lake should be in the Non Disclose Agreement Channel before the article written. Now that Rumor and "leaked" benchmark indicate that Arrow Lake Clock @ 5.5 GHz, sorry, where is TSMC lead, Size (remember BSPD lead to Gain of 6-10% so I don't see N3P can be denser than 18A).
Back to the point High-NA EUV, ASML (new) CEO already mentioned that their machine ever produce 80% still in production. The most critical point of economics here is throughput, ASML mentioned that they will continuous support and upgrade i.e. light source; in these world there are too many people going for hypes, even Bloomberg "Oh the US surrender the EUV opportunities La La La, but the US is still the supplier of the EUV light source to ASML.
I am a qualified accountant, when talk about EUV cost I am also an expert, the EUV machine at Intel should not be more than and Developmental machines, testing our processes, introducing 14A, 10A, etc etc. testing out new customer mask etc etc. even the throughput is slow, it just not that matter.
The report ignore the fact that the Light source will be continuously upgrade and the module will be replace (light source I think is similar to light bulb needed to replace after useful life), then the new upgraded module will be install and the through put is going to be higher.
Next bit is High EUV NA and the size of the mask, that Intel is carry on hoping ASML can address.
Overall because light source is modular, the author in SemiAnalysis do not take it into account and based on current throughput, that is a big mistake.
ironargonaut - Friday, May 10, 2024 - link
What is the difference between "transistor contact" and "transistor's source and drain"? I am not familiar with the term "transistor contact".