I believe highest was 10k on air, and above is with some chiller. Not sure, maybe I overslept something, but ddr5 is much better than ddr4 in that manner.
looks like splitting tht e 64/72-bit bus to a pair of 32/40-bit busses and moving power to the DIMMs are paying back quite major dividends. I like this.
"Using this information, memory controllers can then determine if a memory row has been excessively activated and is at risk of having its bits flipped, at which point they can back off to let the row properly refresh and the data re-stabilize."
This statement should be "Using this information, memory controllers can then determine if a memory row has been excessively activated and is at risk of having its NEIGHBOR'S bits flipped, at which point they can back off to let the NEIGHBOR row properly refresh and the data re-stabilize."
Access a row (doing an activate, read or write command, precharge) refreshes the row being accessed very reliably (which has always been the case for DRAM). However, activating row N can bleed/inject charge from bits stored in the surrounding rows (row N-1 and row N+1) and rowhammer is attacking those neighboring rows. The extra refreshes are not for row N but rows N-1 and N+1.
The bumpiness in latency is mostly down to requirements for integer latencies (everything has to be aligned to clock transitions) and wanting nice overall clock numbers. Other than looking gross to marketing people there's no reason they couldn't have done 8857 CL62 and 14.00 ns latency.
That said, I'm wondering if there's also a technical requirement for the latency to be even. (I don't have any DDR5 systems to poke in the BIOS of.) If not, 8400 CL 59 (one less than JDEC) would be 14.04ns. I haven't calculated them, but it looks like the same would be true for a lot of the other modes with higher latency numbers.
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DougMcC - Monday, April 22, 2024 - link
Gotta get your rowhammer AI protection in asap. Otherwise skynet.erotomania - Monday, April 22, 2024 - link
This is an informative news article. Thanks AT and A.S.Igor_Kavinski - Monday, April 22, 2024 - link
YESS!!!Progress!
Threska - Tuesday, April 23, 2024 - link
DDR6 should already have it.sheh - Monday, April 22, 2024 - link
"depreciate" should be "deprecate".Oxford Guy - Monday, April 22, 2024 - link
'Extreme overclockers are already hitting speeds as high as 11,240 MT/s with current-generation DRAM chips'With actual stability and without goofy things like nitrogen?
deil - Tuesday, April 23, 2024 - link
I believe highest was 10k on air, and above is with some chiller. Not sure, maybe I overslept something, but ddr5 is much better than ddr4 in that manner.ZeDestructor - Tuesday, April 23, 2024 - link
looks like splitting tht e 64/72-bit bus to a pair of 32/40-bit busses and moving power to the DIMMs are paying back quite major dividends. I like this.relaxedjeff - Tuesday, April 23, 2024 - link
"Using this information, memory controllers can then determine if a memory row has been excessively activated and is at risk of having its bits flipped, at which point they can back off to let the row properly refresh and the data re-stabilize."This statement should be
"Using this information, memory controllers can then determine if a memory row has been excessively activated and is at risk of having its NEIGHBOR'S bits flipped, at which point they can back off to let the NEIGHBOR row properly refresh and the data re-stabilize."
Access a row (doing an activate, read or write command, precharge) refreshes the row being accessed very reliably (which has always been the case for DRAM). However, activating row N can bleed/inject charge from bits stored in the surrounding rows (row N-1 and row N+1) and rowhammer is attacking those neighboring rows. The extra refreshes are not for row N but rows N-1 and N+1.
Ryan Smith - Tuesday, April 23, 2024 - link
You are correct, sir! That was a silly error on our part. Thank you!nandnandnand - Tuesday, April 23, 2024 - link
Sweet spot every 2000 MT/s? Let's get that DDR5-10000.deil - Tuesday, April 23, 2024 - link
I would want to see 64GB sticks size first.if they would do tick/tock in size/speeds/size/speed, I would be in heaven.
nandnandnand - Tuesday, April 23, 2024 - link
We're going to see 64 GB sticks first. Support is already being added to motherboard firmware. I guess it will be around within a year.https://www.anandtech.com/show/21302/asus-confirms...
DanNeely - Tuesday, April 23, 2024 - link
The bumpiness in latency is mostly down to requirements for integer latencies (everything has to be aligned to clock transitions) and wanting nice overall clock numbers. Other than looking gross to marketing people there's no reason they couldn't have done 8857 CL62 and 14.00 ns latency.That said, I'm wondering if there's also a technical requirement for the latency to be even. (I don't have any DDR5 systems to poke in the BIOS of.) If not, 8400 CL 59 (one less than JDEC) would be 14.04ns. I haven't calculated them, but it looks like the same would be true for a lot of the other modes with higher latency numbers.