Honestly, yes, fingers crossed. Same for Intel's foundry business. TSMC has been rocking it, for sure, but because they have been consistently delivering great nodes with great yields, they also know they can charge a fortune for them. To have some real competition in the area would force TSMC to be competitive on wafer prices as well, which directly leads to lower prices for consumers.
Well, cache is SRAM whereas NAND and HBM are flash memory and DRAM, respectively. Two (three) different animals. Anyhow, AMD's X3D CPUs have stacked SRAM but it's not all that easy to implement - nor is it reliable, if 5800X3D's various problems are any indicator.
The lower clock rate is a small issue compared to the gain in performance and success of the x3D models. Anyway, the X3D is two different dies connected to each other later.
I thought about doing the stacking directly in the design process on a single die/chip like with Nand. After all, is there another solution to the problem of SRAM not shrinking significantly with each new node?
the gain in performance is extremely application specific and mainly due to slow improvements to DRAM. in overall application performance it is actually slower than a normal 5800x. it's a success because gaming is crippled severely when reaching for system memory, not because its a general purpose success.
but yes stacking 2.5D/3D memory (SRAM or otherwise near-die) may eventually become the norm as nodes continue to struggle shrinking down memory and IO.
The problem with SRAM is that the wiring is extremely dense, and wiring has not been shrinking as rapidly as transistors. You can't just blindly say "go to 3D"! That is a long term aspiration, but there are many steps required to get there. The first step in alleviating wiring congestion is BSPD (back side power delivery) which will arrive over the next few years. Then the current way wires are fabricated (so called Dual Damascene process) will be replaced by the Semi Damascene process, along with changing the metals uses at the smallest pitches. Once this stuff is stabilized, along with the matching changes on the transistor side (replace GAA with fork-sheets, then with CFETs) we have to recalibrate seeing how all these changes work together. Forksheet and then CFET again require dense wiring to get all the power/signals in, along with very high aspect ratio via's. We of course have simulations and expectations as to how it will all work, but no certainties. Anyway at that point, once we have completed "3D in the small" we'll start looking at "3D in the large".
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Dante Verizon - Friday, November 3, 2023 - link
Fingers crossed for them.NextGen_Gamer - Friday, November 3, 2023 - link
Honestly, yes, fingers crossed. Same for Intel's foundry business. TSMC has been rocking it, for sure, but because they have been consistently delivering great nodes with great yields, they also know they can charge a fortune for them. To have some real competition in the area would force TSMC to be competitive on wafer prices as well, which directly leads to lower prices for consumers.Dante Verizon - Friday, November 3, 2023 - link
One question is if it's so hard to shrink caches, why don't they use 3D stacking like in nand and HBM?SiliconJock - Friday, November 3, 2023 - link
Well, cache is SRAM whereas NAND and HBM are flash memory and DRAM, respectively.Two (three) different animals.
Anyhow, AMD's X3D CPUs have stacked SRAM but it's not all that easy to implement - nor is it reliable, if 5800X3D's various problems are any indicator.
Dante Verizon - Friday, November 3, 2023 - link
The lower clock rate is a small issue compared to the gain in performance and success of the x3D models. Anyway, the X3D is two different dies connected to each other later.I thought about doing the stacking directly in the design process on a single die/chip like with Nand. After all, is there another solution to the problem of SRAM not shrinking significantly with each new node?
whatthe123 - Friday, November 3, 2023 - link
the gain in performance is extremely application specific and mainly due to slow improvements to DRAM. in overall application performance it is actually slower than a normal 5800x. it's a success because gaming is crippled severely when reaching for system memory, not because its a general purpose success.but yes stacking 2.5D/3D memory (SRAM or otherwise near-die) may eventually become the norm as nodes continue to struggle shrinking down memory and IO.
dotjaz - Friday, November 3, 2023 - link
Exactly, if you can't afford bread, why not just eat cake?ballsystemlord - Friday, November 3, 2023 - link
Because cake isn't good for you. ;)name99 - Saturday, November 4, 2023 - link
The problem with SRAM is that the wiring is extremely dense, and wiring has not been shrinking as rapidly as transistors.You can't just blindly say "go to 3D"! That is a long term aspiration, but there are many steps required to get there. The first step in alleviating wiring congestion is BSPD (back side power delivery) which will arrive over the next few years. Then the current way wires are fabricated (so called Dual Damascene process) will be replaced by the Semi Damascene process, along with changing the metals uses at the smallest pitches.
Once this stuff is stabilized, along with the matching changes on the transistor side (replace GAA with fork-sheets, then with CFETs) we have to recalibrate seeing how all these changes work together. Forksheet and then CFET again require dense wiring to get all the power/signals in, along with very high aspect ratio via's. We of course have simulations and expectations as to how it will all work, but no certainties. Anyway at that point, once we have completed "3D in the small" we'll start looking at "3D in the large".
https://www.imec-int.com/en/articles/imec-demonstr...