DRAM stores bit state in a capacitor. The smaller (physically) you make the capacitor, the less capacitance it has and the quicker it drains out and needs refreshing. And when you keep scaling down, eventually you have never time to actually read / write data as all you do is refresh the bits.
In typical DRAM the density is limited by a layer of hexagonally stored capacitances and the transistors are then manufactured to a separate layer. Increasing density of transistors in the bit-lane layer doesn't really help, because capacitors still need to be kept more or less same size.
That is why DRAM doesn't really scale down with manufacturing process the same way as logic does. Logic chips like CPU's/GPU's are made of (mostly) transistors that don't need to store charge -> can be made infinitely small as long as they act as transistors.
I hope so, I would like to see an RX nano 2, or some other compact high-end model. It's a shame HBM never became popular or dropped in price, in terms of efficiency, bandwidth and size it's an incredible solution.
"PAM3 allows for 1.5 bits to be transferred per cycle (or rather 3 bits over two cycles), opening the door to improving memory transfer rates"
I'm clearly missing something obvious here. How does going from GDDR6X's PAM4 to GDDR7's PAM3 improve transfer rates (ignoring the clock speed differences)?
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Dante Verizon - Friday, October 20, 2023 - link
Why doesn't the chip density increase...meacupla - Saturday, October 21, 2023 - link
probably because it's new technology.Hopefully we get to see 3GB and 4GB densities down the line.
deil - Tuesday, October 24, 2023 - link
stability is an issue at start, going up instantly is unwise. best method we have is tick tock, migrate -> upgrade -> migrate -> upgrade.zepi - Saturday, October 21, 2023 - link
DRAM stores bit state in a capacitor. The smaller (physically) you make the capacitor, the less capacitance it has and the quicker it drains out and needs refreshing. And when you keep scaling down, eventually you have never time to actually read / write data as all you do is refresh the bits.In typical DRAM the density is limited by a layer of hexagonally stored capacitances and the transistors are then manufactured to a separate layer. Increasing density of transistors in the bit-lane layer doesn't really help, because capacitors still need to be kept more or less same size.
That is why DRAM doesn't really scale down with manufacturing process the same way as logic does. Logic chips like CPU's/GPU's are made of (mostly) transistors that don't need to store charge -> can be made infinitely small as long as they act as transistors.
meacupla - Saturday, October 21, 2023 - link
Chip density is not the same as node/capacitor size.For instance, Micron/Crucial has 3Gb density DDR5 and are working on 4Gb. That's how you get their 12GB and 24GB sticks.
Dante Verizon - Saturday, October 21, 2023 - link
I hope so, I would like to see an RX nano 2, or some other compact high-end model. It's a shame HBM never became popular or dropped in price, in terms of efficiency, bandwidth and size it's an incredible solution.Threska - Sunday, October 22, 2023 - link
Maybe nanoimprint may be the solution.https://youtu.be/8UdNB3ZY4Ks
Threska - Friday, October 20, 2023 - link
Interesting although AI may take a different approach.https://www.nature.com/articles/d41586-023-03267-0
rpg1966 - Sunday, October 22, 2023 - link
"PAM3 allows for 1.5 bits to be transferred per cycle (or rather 3 bits over two cycles), opening the door to improving memory transfer rates"I'm clearly missing something obvious here. How does going from GDDR6X's PAM4 to GDDR7's PAM3 improve transfer rates (ignoring the clock speed differences)?
Ryan Smith - Sunday, October 22, 2023 - link
GDDR6X isn't a JEDEC standard, so it's not what's being compared here. Samsung is going from G6 to G7.G7's PAM3 encoding has a lower density than G6X's PAM 4 (1.5b vs 2b). But it'll hit higher clockspeeds and be less complex to implement.