There isn't discrimination here but please list the vendor that will use TSMC N2 before 2027.
Apple, Intel, nVidia, AMD, Qualcomm, MediaTek, Samsung, Amazon, Google, Microsoft, (smaller one from now on) Lockhead Martin, Ericsson, Nokia (But OpenRAN is current 90%+ held by Intel),
This is more a paper launch then anything.
I am now laughing those in MLID that saying Intel Arrow Lake is moving to TSMC N3E, now with this information, it is proven that GAA and FinFET is totally different, how is Arrow Lake design on GAA + Backside Power Delivery can fit back to FinFET. Arrow Lake Lion Cove is different to Redwood Cove, this prove that MLID is fake news media with no connection to Intel Staff. Just milling idea inside his bedroom without the internet.
This also shows that why Qualcomm did not go with Intel 18A, because the cost of redesign is too much.
If this is the case, I think it will not before (or just before) 2030 that Infineon, Renesa, TI, Broadcom to start using TSMC N2 / Intel 18A / Samsung 3nm, until EUV High-NA got a good depreciation by the high end application, meaning that even initial GAA is build by Intel and Samsung using non High-NA machine, there might be a need to move to High-NA to reduce cost.
Even Intel does not know always what process or specs they are going to end up with on different lines of products and they change it on-the-go, for example they marketed 192 EUs (VEs now) on Meteor Lake iGPU and ended up on 128 EUs. In addition, initial 320 EUs (VEs now) on Arrow Lake became 192 EUs. So, Tom from MLID is fed by whatever current information is available. This information sometimes changes. It's not written in stone like 10 Commandments. Also, not everyone in Intel knows what's going on on all fronts. That's impossible.
Sorry your comment make no sense, I am talking about the CPU that MLID was talking about, now you move to ARC/GPU, if you look at SemiAccurate, you understand that iGPU tile actually held back by TSMC, we know way ahead (at least in 2022 Q1) that intel can't be using TSMC N3 on GPU, it was likely that when Meteor Lake is plan that it will be the case and it might be in TSMC N3B, but the more into the development, the more unlikely that TSMC will met it's deadline show Intel will stay with TSMC N5/N6.
Yes not written in stone like 10 Commandments, but anyone with a brain will know that TSMC N3E without GAA+PowerVia will not be able to move (backward) to FinFET, there is no way Intel will make this investment, is not 10 Commandments but it is the rules of Economic, So it is just as strong, except the 10 Commandments is from God. So MLID is Fake news media with no connection to Intel Staff directly working with CPU. Else no one even a junior intern will think that arrow lake CPU title will be made by TSMC.
I don't know what you're expecting, these new process announcements are not really for consumers. TSMC announces this stuff to stir up interest from their customers, who will build on the process and then announce their new chips. Those new chips will then get integrated into products and then those product-makers will announce those.
For a consumer perspective any TSMC announcement is going to be a "paper launch". So I'm not sure why you're seemingly surprised by this.
Not sure you know what you are talking about. Moving a die from one technology to another does not have the implications you think ("can fit back to FinFet"). That's not the way it works. You don't fit anything back to anything else. Intel would simply design a new CPU chiplet on another technology. In this case the reports are that some of the cores change from Redwood->Lion and Crest->Sky. The WHOLE idea of 3D die stacking and segregating the die into basic functional blocks is to allow this kind of modularity when designing a system.
If the future follows the past, I would imagine that Apple would be the first vendor to use the technology. If it’s true that TSMC is on track to have mass production 2H 2025, as they say, then certainly 2027 is very likely, even if they get pushed back by a quarter or two.
Yes unless TSMC's N2 rollout is seriously delayed Apple will be using N2 for iPhone 18 in 2026. If they could somehow pull that H2 date forward to Q2 Apple would be able to use it for iPhone 17, but I'm gonna assume "H2" means December like it did for N3 meaning iPhone 17 gets N3P.
I have serious doubt about this, be honestly, if you know Chinese, you can watch some finance youtube talk bashing USA that Taiwan can build and USA can't they are flexible la la la. Be very honest, the flip side of the coin is that Taiwanese builder will request work to move on else will go online and blame TSMC for delay and this is what they did, and of course TSMC will go out there is silent it in a CCP fashion. This is what they did and try to claim down things.
Then you see Intel mentioned ASML will received High-NA in Dec 2023, as TSMC and ASML relationship is very good, we can assume that TSMC will get High-NA no later than April 2024, then TSMC will use High-NA for N2, look at how difficult TSMC achieve N3B (rumor but too many of them to be ignored), the best bet for TSMC to have a reasonable N2 is through High-NA.
This is not the same story for Intel, remember PowerVIA, that meant that Intel M0 is going to be simpler than TSMC N2 as cables runs from the back.
Whether TSMC will delay or not depends on ASML, and you know ASML delay history.
Because TSMC can't even make me feels like they can make N3B properly, i.e. rumors, iPhone 15 Pro Max Pan Fry Egg, introducing N3E, how am I going to have confidence that multi patterning on EUV works in TSMC. So the best bet is TSMC wait for high na then move to N2.
Whether 2027 is very likely, it can be just as easy to say 2027 is very unlikely, and move to 2028 is more likely, then Intel will be what 4 years ahead because 20A is TSMC N2P not TSMC N2.
I think you don't understand how much work goes into rolling out a new process if you think receiving their first high NA scanner in early 2024 would allow them to use it for N2.
First of all they need way more than one for mass production at their scale, second of all they have already frozen N2's characteristics. They have the fab space built out and exactly planned where every piece of hardware goes - there is no room for the far larger high NA scanners, no power budget for them, and nothing in N2's specs that requires them.
Maybe they will slot in high NA scanners 2-3 years down the road when the N2 family has reached the end of the line and is on its final long life iteration, like N6 was for the N7 family.
But other than that - which won't concern Apple or others who following the leading edge train - high NA will be reserved whatever they call the "N1.4" node that comes after N2 late this decade.
Do you know Maths you mentioned 2 years, if ASML provided a High NA scanner to TSMC Q1 2024, then use your primary school Maths, Q2 2024, Q3 2024, Q4 2024, Q1 2025, Q2 2025, Q3 2025, Q4 2026 (test production 1 and half year), then missed iPhone deadline, then Q1 2026, Q2 2026 (ramp) i.e. 2 years, use your figure and count properly.
This meant that the contractor is not happy and why delay ??? 1) Apple did not want their N2 capacity or delay it's requirement. 2) Change the plan and want to switch to high na, remember ASML already promised.
"Meanwhile, Samsung Foundry and TSMC are slated to start production of chips on their 2 nm-class nodes (SF2, N2) in late 2025. Though just how High-NA machines factor into their plans remains equally up in the air."
What I am saying is so possible what your 1.4 nm stories is not. Look at fact. There is no love, only money in running a company.
N2 isn't a mere node shrink, they're changing the fundamental transistor architecture. They're probably already more than busy enough refining the GAAFET-specific process changes, techniques, design, integration, possibly tooling, etc... where also trying to integrate High-NA into the workflow would end up being counterproductive.
Remember that trying to take two steps at a time was how Intel tripped themselves in their 10nm business.
"Remember that trying to take two steps at a time was how Intel tripped themselves in their 10nm business."
Which makes it interesting that TSMC is doing GAAFET alone in N2, and saving backside power for its second iteration (N2P or whatever they call it) Intel meanwhile is attempting GAAFET / "ribbonFET" and backside power at the same time in 20A. If that fails there will be a lot of "I told you sos" from people remembering the 10nm debacle.
Even if they succeed that doesn't mean TSMC should have done both. They have always been conservative - they rolled out N7 without EUV, then a year later introduced N7+ with four EUV layers alongside N7P without EUV, then a year after that introduced N5 with many EUV layers. Doing it that way essentially de-risked the introduction of EUV - if they ran into issues they were still pumping out N7P wafers so they didn't have all their eggs in the EUV basket. But easing into it that way gave them mass production experience with EUV that made N5 their most successful node N5 rollout ever.
I really don't see that is the case because I felt like TSMC didn't mastered double patterning using EUV, if yes then iPhone 15 will use N3B, now only pro max, it was also rumor that Apple will only take good chip (due to low yield) as oppose to taking the whole waffle, then TSMC effort is to reduced EUV exposure in N3E, more like they admit defeat, going forward, TSMC N2 has to use double patterning, it deeply depended on what they learned in N3B experience, but the answer seems to be not a lot.
I don't see this is that difficult to switch from EUV to EUV NA, it is like I am using Canon then suddenly there is a Hasselblad, or I am driving a Toyota and suddenly there is a Mclaren.
As I mentioned before, the modular Fab building which the Taiwanese so proud of will take care of it then yes they delay the building of Fab in Taiwan is most likely that they change the design (modular) now they just need the time to redesign some aspect to fit the larger EUV NA machine.
At this moment in time they will use EUV to build test chip and once High NA is install they can switch the process using lesser.
The Taiwanese were so proud that they can build a FAB in 18 months, so so so there is no issues to even start a brand new fab for EUV NA today and still meet the Q4 2025 N2 roadmap.
You think that my moving to EUV High-NA meant that the whole chip i.e M0-Mx layer all will be EUV High-NA, no way the cost will be insane.
My switching to EUV High-NA knowledgeable person will know that switching to EUV High-NA will meant that M0-M1 will be in High-NA and the rest of the other layer will continue with EUV or even DUV. The cost of exposure is different (power/electricity/depreciation/CAPEX) all different EUV High-NA vs EUV vs DUV.
Yes M0 is the most complex and critical and meant a lot of resource and money is put there, but from a building point of view, you build an extra room right next to the FAB currently build/plan/design to be EUV only, and that extra room like a garage and link the main facility with a rail system that is it. This is what by meant of modular, that garage/module is for M0 so to speak, it done all the nice work in EUV High-NA, then transport to the "older" section of the fab to complete the rest of the layer.
Just a like liver Operation (Brain, heart and liver operation have longer operation hours), the junior doctor is going to perform the opening up of the area, clearing the necessary organ, then the senior doctor (main doctor) going to cut the liver, perform the blood vessel reconstruction, etc. the junior doctor come back to perform the closing up. No only the junior team can learn, but the senior team is not over exhausted on aspect that can be performed by junior. (we are talking about 3-10 hours operation).
Similarly no Fab will use a EUV High NA for work that can be performed by EUV or DUV. Your impossible meant that you think not in the same way as it should be.
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my_wing - Thursday, October 12, 2023 - link
There isn't discrimination here but please list the vendor that will use TSMC N2 before 2027.Apple, Intel, nVidia, AMD, Qualcomm, MediaTek, Samsung, Amazon, Google, Microsoft, (smaller one from now on) Lockhead Martin, Ericsson, Nokia (But OpenRAN is current 90%+ held by Intel),
This is more a paper launch then anything.
I am now laughing those in MLID that saying Intel Arrow Lake is moving to TSMC N3E, now with this information, it is proven that GAA and FinFET is totally different, how is Arrow Lake design on GAA + Backside Power Delivery can fit back to FinFET. Arrow Lake Lion Cove is different to Redwood Cove, this prove that MLID is fake news media with no connection to Intel Staff. Just milling idea inside his bedroom without the internet.
This also shows that why Qualcomm did not go with Intel 18A, because the cost of redesign is too much.
If this is the case, I think it will not before (or just before) 2030 that Infineon, Renesa, TI, Broadcom to start using TSMC N2 / Intel 18A / Samsung 3nm, until EUV High-NA got a good depreciation by the high end application, meaning that even initial GAA is build by Intel and Samsung using non High-NA machine, there might be a need to move to High-NA to reduce cost.
TekCheck - Friday, October 13, 2023 - link
Even Intel does not know always what process or specs they are going to end up with on different lines of products and they change it on-the-go, for example they marketed 192 EUs (VEs now) on Meteor Lake iGPU and ended up on 128 EUs. In addition, initial 320 EUs (VEs now) on Arrow Lake became 192 EUs. So, Tom from MLID is fed by whatever current information is available. This information sometimes changes. It's not written in stone like 10 Commandments. Also, not everyone in Intel knows what's going on on all fronts. That's impossible.my_wing - Friday, October 13, 2023 - link
Sorry your comment make no sense, I am talking about the CPU that MLID was talking about, now you move to ARC/GPU, if you look at SemiAccurate, you understand that iGPU tile actually held back by TSMC, we know way ahead (at least in 2022 Q1) that intel can't be using TSMC N3 on GPU, it was likely that when Meteor Lake is plan that it will be the case and it might be in TSMC N3B, but the more into the development, the more unlikely that TSMC will met it's deadline show Intel will stay with TSMC N5/N6.Yes not written in stone like 10 Commandments, but anyone with a brain will know that TSMC N3E without GAA+PowerVia will not be able to move (backward) to FinFET, there is no way Intel will make this investment, is not 10 Commandments but it is the rules of Economic, So it is just as strong, except the 10 Commandments is from God. So MLID is Fake news media with no connection to Intel Staff directly working with CPU. Else no one even a junior intern will think that arrow lake CPU title will be made by TSMC.
Dante Verizon - Saturday, October 14, 2023 - link
If TSMC doesn't succeed, Intel won't come close to achieving it in processes below 3nm.Flunk - Monday, October 16, 2023 - link
I don't know what you're expecting, these new process announcements are not really for consumers. TSMC announces this stuff to stir up interest from their customers, who will build on the process and then announce their new chips. Those new chips will then get integrated into products and then those product-makers will announce those.For a consumer perspective any TSMC announcement is going to be a "paper launch". So I'm not sure why you're seemingly surprised by this.
do_not_arrest - Monday, October 16, 2023 - link
Not sure you know what you are talking about. Moving a die from one technology to another does not have the implications you think ("can fit back to FinFet"). That's not the way it works. You don't fit anything back to anything else. Intel would simply design a new CPU chiplet on another technology. In this case the reports are that some of the cores change from Redwood->Lion and Crest->Sky. The WHOLE idea of 3D die stacking and segregating the die into basic functional blocks is to allow this kind of modularity when designing a system.melgross - Friday, October 13, 2023 - link
If the future follows the past, I would imagine that Apple would be the first vendor to use the technology. If it’s true that TSMC is on track to have mass production 2H 2025, as they say, then certainly 2027 is very likely, even if they get pushed back by a quarter or two.Doug_S - Friday, October 13, 2023 - link
Yes unless TSMC's N2 rollout is seriously delayed Apple will be using N2 for iPhone 18 in 2026. If they could somehow pull that H2 date forward to Q2 Apple would be able to use it for iPhone 17, but I'm gonna assume "H2" means December like it did for N3 meaning iPhone 17 gets N3P.my_wing - Sunday, October 15, 2023 - link
I have serious doubt about this, be honestly, if you know Chinese, you can watch some finance youtube talk bashing USA that Taiwan can build and USA can't they are flexible la la la. Be very honest, the flip side of the coin is that Taiwanese builder will request work to move on else will go online and blame TSMC for delay and this is what they did, and of course TSMC will go out there is silent it in a CCP fashion. This is what they did and try to claim down things.Then you see Intel mentioned ASML will received High-NA in Dec 2023, as TSMC and ASML relationship is very good, we can assume that TSMC will get High-NA no later than April 2024, then TSMC will use High-NA for N2, look at how difficult TSMC achieve N3B (rumor but too many of them to be ignored), the best bet for TSMC to have a reasonable N2 is through High-NA.
This is not the same story for Intel, remember PowerVIA, that meant that Intel M0 is going to be simpler than TSMC N2 as cables runs from the back.
Whether TSMC will delay or not depends on ASML, and you know ASML delay history.
Because TSMC can't even make me feels like they can make N3B properly, i.e. rumors, iPhone 15 Pro Max Pan Fry Egg, introducing N3E, how am I going to have confidence that multi patterning on EUV works in TSMC. So the best bet is TSMC wait for high na then move to N2.
Whether 2027 is very likely, it can be just as easy to say 2027 is very unlikely, and move to 2028 is more likely, then Intel will be what 4 years ahead because 20A is TSMC N2P not TSMC N2.
Doug_S - Sunday, October 15, 2023 - link
I think you don't understand how much work goes into rolling out a new process if you think receiving their first high NA scanner in early 2024 would allow them to use it for N2.First of all they need way more than one for mass production at their scale, second of all they have already frozen N2's characteristics. They have the fab space built out and exactly planned where every piece of hardware goes - there is no room for the far larger high NA scanners, no power budget for them, and nothing in N2's specs that requires them.
Maybe they will slot in high NA scanners 2-3 years down the road when the N2 family has reached the end of the line and is on its final long life iteration, like N6 was for the N7 family.
But other than that - which won't concern Apple or others who following the leading edge train - high NA will be reserved whatever they call the "N1.4" node that comes after N2 late this decade.
my_wing - Sunday, October 15, 2023 - link
Do you know Maths you mentioned 2 years, if ASML provided a High NA scanner to TSMC Q1 2024, then use your primary school Maths, Q2 2024, Q3 2024, Q4 2024, Q1 2025, Q2 2025, Q3 2025, Q4 2026 (test production 1 and half year), then missed iPhone deadline, then Q1 2026, Q2 2026 (ramp) i.e. 2 years, use your figure and count properly.Doug_S - Monday, October 16, 2023 - link
I meant 2-3 years after the initial N2, not 2-3 years from now.my_wing - Monday, October 16, 2023 - link
I can't find the actual link but it was the lady analyst on this showhttps://www.youtube.com/watch?v=CmkUmRM-_uI
She mentioned that TSMC advantage is modular Fab budling, there is no plan, they change when they build, and because
https://technews.tw/2023/09/18/tsmc-n2-gaafet-nano...
This meant that the contractor is not happy and why delay ???
1) Apple did not want their N2 capacity or delay it's requirement.
2) Change the plan and want to switch to high na, remember ASML already promised.
Look at what the news said.
https://www.anandtech.com/show/20044/asml-to-deliv...
"Meanwhile, Samsung Foundry and TSMC are slated to start production of chips on their 2 nm-class nodes (SF2, N2) in late 2025. Though just how High-NA machines factor into their plans remains equally up in the air."
What I am saying is so possible what your 1.4 nm stories is not. Look at fact. There is no love, only money in running a company.
Wereweeb - Sunday, October 15, 2023 - link
N2 isn't a mere node shrink, they're changing the fundamental transistor architecture. They're probably already more than busy enough refining the GAAFET-specific process changes, techniques, design, integration, possibly tooling, etc... where also trying to integrate High-NA into the workflow would end up being counterproductive.Remember that trying to take two steps at a time was how Intel tripped themselves in their 10nm business.
Doug_S - Sunday, October 15, 2023 - link
"Remember that trying to take two steps at a time was how Intel tripped themselves in their 10nm business."Which makes it interesting that TSMC is doing GAAFET alone in N2, and saving backside power for its second iteration (N2P or whatever they call it) Intel meanwhile is attempting GAAFET / "ribbonFET" and backside power at the same time in 20A. If that fails there will be a lot of "I told you sos" from people remembering the 10nm debacle.
Even if they succeed that doesn't mean TSMC should have done both. They have always been conservative - they rolled out N7 without EUV, then a year later introduced N7+ with four EUV layers alongside N7P without EUV, then a year after that introduced N5 with many EUV layers. Doing it that way essentially de-risked the introduction of EUV - if they ran into issues they were still pumping out N7P wafers so they didn't have all their eggs in the EUV basket. But easing into it that way gave them mass production experience with EUV that made N5 their most successful node N5 rollout ever.
my_wing - Monday, October 16, 2023 - link
I really don't see that is the case because I felt like TSMC didn't mastered double patterning using EUV, if yes then iPhone 15 will use N3B, now only pro max, it was also rumor that Apple will only take good chip (due to low yield) as oppose to taking the whole waffle, then TSMC effort is to reduced EUV exposure in N3E, more like they admit defeat, going forward, TSMC N2 has to use double patterning, it deeply depended on what they learned in N3B experience, but the answer seems to be not a lot.I don't see this is that difficult to switch from EUV to EUV NA, it is like I am using Canon then suddenly there is a Hasselblad, or I am driving a Toyota and suddenly there is a Mclaren.
As I mentioned before, the modular Fab building which the Taiwanese so proud of will take care of it then yes they delay the building of Fab in Taiwan is most likely that they change the design (modular) now they just need the time to redesign some aspect to fit the larger EUV NA machine.
At this moment in time they will use EUV to build test chip and once High NA is install they can switch the process using lesser.
The Taiwanese were so proud that they can build a FAB in 18 months, so so so there is no issues to even start a brand new fab for EUV NA today and still meet the Q4 2025 N2 roadmap.
Doug_S - Monday, October 16, 2023 - link
"I don't see this is that difficult to switch from EUV to EUV NA" -- someone with absolutely zero knowledge about how foundries operate.my_wing - Monday, October 16, 2023 - link
You are getting too personal.Reuter don't know, AnandTech don't know so why you come here????
Stop milling idea out of thin air.
https://www.anandtech.com/show/20044/asml-to-deliv...
my_wing - Monday, October 16, 2023 - link
You have no idea as well.You think that my moving to EUV High-NA meant that the whole chip i.e M0-Mx layer all will be EUV High-NA, no way the cost will be insane.
My switching to EUV High-NA knowledgeable person will know that switching to EUV High-NA will meant that M0-M1 will be in High-NA and the rest of the other layer will continue with EUV or even DUV. The cost of exposure is different (power/electricity/depreciation/CAPEX) all different EUV High-NA vs EUV vs DUV.
Yes M0 is the most complex and critical and meant a lot of resource and money is put there, but from a building point of view, you build an extra room right next to the FAB currently build/plan/design to be EUV only, and that extra room like a garage and link the main facility with a rail system that is it. This is what by meant of modular, that garage/module is for M0 so to speak, it done all the nice work in EUV High-NA, then transport to the "older" section of the fab to complete the rest of the layer.
Just a like liver Operation (Brain, heart and liver operation have longer operation hours), the junior doctor is going to perform the opening up of the area, clearing the necessary organ, then the senior doctor (main doctor) going to cut the liver, perform the blood vessel reconstruction, etc. the junior doctor come back to perform the closing up. No only the junior team can learn, but the senior team is not over exhausted on aspect that can be performed by junior. (we are talking about 3-10 hours operation).
Similarly no Fab will use a EUV High NA for work that can be performed by EUV or DUV. Your impossible meant that you think not in the same way as it should be.
ballsystemlord - Thursday, October 26, 2023 - link
@Anton , Don't you have a number by now for chip density of N5 vs N7? N5 has been out for some time now.