In other words, if NA-EUV is not being used by 18A, then WHAT is it that defines 18A? Earlier nodes are defined by GAA and BSPD, but 18A without NA-EUV seems a pure marketing node. Or will we see a crazy reach for density that fails, like I10?
What is left that has been publicly announced: (1) Ribbon Innovation (whatever that may end up being is not defined) and (2) Line width reduction. That line width reduction could give higher densities or might just be used for a bit less power charging and draining the lines.
...refinement, obviously. 20A being the jump to GAAFETs, I bet they'll have to use relatively lax tolerances at first, to get it working on a commercial scale. After the experience with 20A, they'll set new goals for feature sizes and work hard on getting there within a commercially viable amount of defects. They can do a lot of work, even without any big updates to their tooling. You know, like all foundries do.
This is especially true if their switch to GAAFET isn't going well and they need to be extra lax with tolerances at first to not pull a Samsung and pump out the kind of wafers where instead of finding the defects you search for the rare usable die. Taking it slow and steady is the very opposite approach to the one which led to the Intel 10nm/7 debacle.
It'll be Oregon first, as always. Since they need an 18A line to play with the High-NA machine, it'll be D1X, which was specifically upgraded earlier in the decade to house those machines. (They're 3 stories tall!)
The number of people just dismissing Intel is baffling. Is it really that improbable that the semiconductor process leader for most of the history can take back the lead again. It's not that TSMC never had process issues.
It may be attributed in part to shady anti-competition tactics by Intel. But this is a single case, Intel, being much larger, failed countless times and in several markets (GPU, Memory, Nand, Smartphones, etc.), and ended up losing tens of billions in the process.
Skepticism is justifiable, especially when Intel intends to continue manufacturing GPUs at TSMC.
bulldozer wasn't because of intel. they got a huge cash injection from the global foundries spinoff to design bulldozer, all thanks to the antitrust win.
Intel broke the record for failures among all large corporations.
well... this dispute comes down to tooling, which is ASML sole sourced for this step (much of the rest from other vendors as well). to put the blame on Intel's tooling assumes that a significant %-age of said tooling is made by Intel. any notion how much of such tooling is bespoke to Intel, or TSMC, or etc.? and how much is just bad arch and micro-arch? a craftsman never blames his tools.
Intel propaganda: unquestioned leadership, process / cpu ahead of shedule, PDK almost ready, better than expected, no roadblocks ahead... Then they release Raptor Lake Refresh
Intel had said they could only do pitches > 30 nm with 0.33 NA. So does this mean Intel 18A has same design rules as Intel 4? Seems that way, for all four nodes to be ready at the same time.
No because Intel will utilize double exposure on few layers, so both 20A and 18A will are finer in metallization. Also looks like there are some new sw tools that help a lot the DUV double exposure. After all TSMC not even think to High-NA, the cost of machines is crazy (2X), they can not afford an high number of them, simple and plain. They go to Double exposure stright. However Intel have a niche where these crazy scanners have an economic sense: server SKUs.
It's great to see Intel's commitment to advancing semiconductor technology with their work on the 18A production node. Keeping pace with ever-shrinking lithography is crucial for the industry's progress. I'm looking forward to the innovations and improved performance this node will bring to future Intel products. Kudos to their dedication to pushing the boundaries of technology.
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
24 Comments
Back to Article
Dante Verizon - Thursday, September 21, 2023 - link
What a strange excess of propaganda in order to show some progress...ballsystemlord - Thursday, September 21, 2023 - link
At least they're not calling it "Intel Superfin eXtreme."name99 - Thursday, September 21, 2023 - link
In other words, if NA-EUV is not being used by 18A, then WHAT is it that defines 18A?Earlier nodes are defined by GAA and BSPD, but 18A without NA-EUV seems a pure marketing node. Or will we see a crazy reach for density that fails, like I10?
dullard - Thursday, September 21, 2023 - link
What is left that has been publicly announced: (1) Ribbon Innovation (whatever that may end up being is not defined) and (2) Line width reduction. That line width reduction could give higher densities or might just be used for a bit less power charging and draining the lines.TristanSDX - Thursday, September 21, 2023 - link
18A is just new name for 20A++stephenbrooks - Thursday, September 21, 2023 - link
These nodes are in pairs I think:4 and 3 are the old 7nm and 7+
20A and 18A are the old 5nm and 5+
In other words, 18A is an "optimisation" node, not a major shake-up.
Wereweeb - Thursday, September 21, 2023 - link
...refinement, obviously. 20A being the jump to GAAFETs, I bet they'll have to use relatively lax tolerances at first, to get it working on a commercial scale. After the experience with 20A, they'll set new goals for feature sizes and work hard on getting there within a commercially viable amount of defects. They can do a lot of work, even without any big updates to their tooling. You know, like all foundries do.This is especially true if their switch to GAAFET isn't going well and they need to be extra lax with tolerances at first to not pull a Samsung and pump out the kind of wafers where instead of finding the defects you search for the rare usable die. Taking it slow and steady is the very opposite approach to the one which led to the Intel 10nm/7 debacle.
AJL - Thursday, September 21, 2023 - link
So, which Fab will be ready in 2024 to ramp up 18A?Ryan Smith - Thursday, September 21, 2023 - link
It'll be Oregon first, as always. Since they need an 18A line to play with the High-NA machine, it'll be D1X, which was specifically upgraded earlier in the decade to house those machines. (They're 3 stories tall!)https://www.anandtech.com/show/17344/intel-opens-d...
AJL - Friday, September 22, 2023 - link
Thanks Ryan! I probably read that article back then, but the old grey matter isn't what it used to be ;-)FunBunny2 - Sunday, September 24, 2023 - link
house those machines. (They're 3 stories tall!)wait... so industry needs ever huger machines to make ever smaller chips? Kafka should sue for copyright infringement.
m53 - Thursday, September 21, 2023 - link
The number of people just dismissing Intel is baffling. Is it really that improbable that the semiconductor process leader for most of the history can take back the lead again. It's not that TSMC never had process issues.Dante Verizon - Friday, September 22, 2023 - link
Intel broke the record for failures among all large corporations.Jorgp2 - Friday, September 22, 2023 - link
Huh?AMD was on bulldozer for nearly 7 years, and it almost bankrupted them
Dante Verizon - Saturday, September 23, 2023 - link
It may be attributed in part to shady anti-competition tactics by Intel. But this is a single case, Intel, being much larger, failed countless times and in several markets (GPU, Memory, Nand, Smartphones, etc.), and ended up losing tens of billions in the process.Skepticism is justifiable, especially when Intel intends to continue manufacturing GPUs at TSMC.
whatthe123 - Saturday, September 23, 2023 - link
bulldozer wasn't because of intel. they got a huge cash injection from the global foundries spinoff to design bulldozer, all thanks to the antitrust win.opteron failing was because of intel.
FunBunny2 - Sunday, September 24, 2023 - link
Intel broke the record for failures among all large corporations.well... this dispute comes down to tooling, which is ASML sole sourced for this step (much of the rest from other vendors as well). to put the blame on Intel's tooling assumes that a significant %-age of said tooling is made by Intel. any notion how much of such tooling is bespoke to Intel, or TSMC, or etc.? and how much is just bad arch and micro-arch? a craftsman never blames his tools.
JKflipflop98 - Friday, September 22, 2023 - link
Indeed. It's like these kids forgot the last 50 years.TristanSDX - Thursday, September 21, 2023 - link
Intel propaganda: unquestioned leadership, process / cpu ahead of shedule, PDK almost ready, better than expected, no roadblocks ahead...Then they release Raptor Lake Refresh
Anymoore - Friday, September 22, 2023 - link
One logistic issue with High-NA EUV is stitching; some lines may be exposed in two parts, with breaks or shifts across boundaries.Thinner resists are needed.
And there's a hole in one of the mirrors (troublesome for light to avoid).
Anymoore - Friday, September 22, 2023 - link
Intel had said they could only do pitches > 30 nm with 0.33 NA. So does this mean Intel 18A has same design rules as Intel 4? Seems that way, for all four nodes to be ready at the same time.Gondalf - Friday, September 22, 2023 - link
No because Intel will utilize double exposure on few layers, so both 20A and 18A will are finer in metallization. Also looks like there are some new sw tools that help a lot the DUV double exposure.After all TSMC not even think to High-NA, the cost of machines is crazy (2X), they can not afford an high number of them, simple and plain. They go to Double exposure stright.
However Intel have a niche where these crazy scanners have an economic sense: server SKUs.
Mantion - Wednesday, September 27, 2023 - link
I don't think the current leadership at Intel working. The board needs to demand results and hold leaders accountable.purohitsforpooja - Wednesday, October 11, 2023 - link
It's great to see Intel's commitment to advancing semiconductor technology with their work on the 18A production node. Keeping pace with ever-shrinking lithography is crucial for the industry's progress. I'm looking forward to the innovations and improved performance this node will bring to future Intel products. Kudos to their dedication to pushing the boundaries of technology.