Why should it? Fully amortized foundry with no EUV equipment required, no multiple exposures required = extremely cheap production cost. Fully mature process node = very low rate of faulty chips. For a class of simple chips that don't need to cram in lots of transistors or need the lowest possible power draw, there's no benefit from going smaller.
I read here some time ago that making any/most/all embedded processor chips (in the xxK transistor count class) on 'current' nodes would yield a chip that was near microscopic. I think, but not sure, that mounting such in a package was said to be really difficult, since the wiring points would be so close together.
The lithography mechanics at 65 nm are very mature but Intel does need to adapter a bit to SOI. There is likely going to be a small learning curve and ramp up before things resume. However with the high yields expected of 65 nm today, their is still going to be a slight premium invoked for using SOI wafers. Still cheap, just not as cheap as one would initially expect.
Anyone who knows/has worked for Russel Ellwanger (pronounced El-vonger) knows he’s kind of a pompous a-hole. Told me once that nobody helped him get to where he is today. That’s right, Russel Ellwanger invented it all.
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Calabros - Wednesday, September 6, 2023 - link
65nm just never dies.Glaurung - Wednesday, September 6, 2023 - link
Why should it? Fully amortized foundry with no EUV equipment required, no multiple exposures required = extremely cheap production cost. Fully mature process node = very low rate of faulty chips. For a class of simple chips that don't need to cram in lots of transistors or need the lowest possible power draw, there's no benefit from going smaller.FunBunny2 - Wednesday, September 6, 2023 - link
I read here some time ago that making any/most/all embedded processor chips (in the xxK transistor count class) on 'current' nodes would yield a chip that was near microscopic. I think, but not sure, that mounting such in a package was said to be really difficult, since the wiring points would be so close together.Threska - Wednesday, September 6, 2023 - link
Makes for a move from "system on a chip" to "car on a chip". At least a leg up in autonomous vehicles.Kevin G - Wednesday, September 6, 2023 - link
The lithography mechanics at 65 nm are very mature but Intel does need to adapter a bit to SOI. There is likely going to be a small learning curve and ramp up before things resume. However with the high yields expected of 65 nm today, their is still going to be a slight premium invoked for using SOI wafers. Still cheap, just not as cheap as one would initially expect.shing3232 - Wednesday, September 6, 2023 - link
anything lower than 65nm is undesirable for CMOS.Samus - Monday, September 11, 2023 - link
Exactly this. And CMOS isn't going anywhere. There are so many conditions where the integrity offered by 65nm is critical, especially outer space.StevoLincolnite - Wednesday, September 13, 2023 - link
And you can still make fairly decent chips on 65nm. I.E. 1 Billion transistors at 400mm2.RicksCollege - Wednesday, September 6, 2023 - link
Anyone who knows/has worked for Russel Ellwanger (pronounced El-vonger) knows he’s kind of a pompous a-hole. Told me once that nobody helped him get to where he is today. That’s right, Russel Ellwanger invented it all.