The DRAM "1a" minimum pitch is around 28nm; that might be the same as the "4nm" node, despite their different node names. But yeah, I've always wondered if the DRAM and foundry lines were separate. If so, they may have always had limited foundry capacity, just enough for their own Exynos, and not much more.
DRAM fabs and Foundry (LSI) are generally outfitted with different tool sets having worked in both types of them. The processes are dramatically different. Doubtful that they would run DRAM wafers in same line as Foundry wafers. DRAM and NAND are similar so I could see that though.
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Anymoore - Tuesday, July 18, 2023 - link
Do they put DRAM work on the Foundry lines? That could increase utilization artificially. Or maybe more R&D, just to prevent idle time.meacupla - Tuesday, July 18, 2023 - link
Currently DRAM doesn't use such a small (5-7nm) node.Anymoore - Wednesday, July 19, 2023 - link
The DRAM "1a" minimum pitch is around 28nm; that might be the same as the "4nm" node, despite their different node names. But yeah, I've always wondered if the DRAM and foundry lines were separate. If so, they may have always had limited foundry capacity, just enough for their own Exynos, and not much more.dotjaz - Wednesday, August 23, 2023 - link
Except D1α is the first generation EUV. 4nm logic is more than 2 generations in.Eskimou - Monday, July 24, 2023 - link
DRAM fabs and Foundry (LSI) are generally outfitted with different tool sets having worked in both types of them. The processes are dramatically different. Doubtful that they would run DRAM wafers in same line as Foundry wafers. DRAM and NAND are similar so I could see that though.