Interesting that the feature size for Samsung memory (12nm) is so much larger than for Samsung logic (3nm). Is there really such a big difference? Or does the 12nm figure still actually refer to some real physical characteristic of the memory cells, unlike logic 'nm' fantasy units?
That's not really answering my question. I know about the marketing nm issue. I'm asking why the big difference (12nm vs 3nm) and if they are really different process sizes underneath or if there is another reason for the gap.
I would guess the biggest factor here is cost. Ram is mostly a commodity product, so unlike with cpu's having a bit faster / efficient memory chips is not worth a cost increase, besides that it just doesn't scale as well as logic anymore. This is also why AMD produces it's cache dies at a larger node than it's core on rdna3.
Logic and dram processes are completely different, so the numbers are not comparable. In dram it's about the ability to make narrow but extremely tall capacitors. In logic it's about making transistors and wires. Asking why the feature sizes are different is like asking why horses are smaller than airplanes.
The numbers are literally nonsense. Almost 10 years ago Samsung started making what they branded as 10nm DRAM. This year they switched to denser 12nn DRAM, presumably because marketing likes that 12 was bigger than 10.
Sigh. Does nobody read questions before answering? I am not asking why the feature sizes are different. Of course they are different. I am asking is 12nm actually represents any physical feature size on a DRAM chip.
And no, Samsung never had branded 10nm DRAM. They had 10nm-class DRAM. That "class" word is doing a lot of heavy lifting here, and readers often skip over it. It is really just saying the first digit is a 1. So 10nm class is anywhere between 10nm and 19nm. 10 years ago it was nearer to 19nm. Now it is 12nm. But they certainly didn't "increase the number because marketing likes that 12 is bigger than 10"!
I have a lot of respect for Samsung .. as they can build laptops which can shame 1U servers... by outpacing CAMM mumbo-jumbo through creating densest RAM / SODIMM instead of current direction of fastest ... capacitance on say 4nm could be issue but Samsung has to realize this era of AI, ML, LLM ... these projects should be doable by students and professionals on the go... CPUs are there but RAMs are falling behind cuz of giants to pin hopes in this aspect e.g. MS indulged in matching surface laptops with lipstick shades, Google having no direction except chromebooks, DELL/HP instead of working with SKHynix, Crucial, Samsung spewing own wheel reinventions, and Lenovo despite most democratic is juggling with who to stab with just 1 mem-bank and whom to bless with 4 mem-banks .. MSI, Gigabyte, Acer, Asus and custom xeon laptop makers are etc are just creating skins (think nokia phones) ... Out of System76 and Framework i think Framework is most promising but i dont know what is holding them to enable 256gb+ RAM laptops while avoiding CAMM way
The information you want is all there in the article.
- Samsung is getting 20% more production per wafer, so that should give you a hint as to if this is really a die shrink or not. - Capacitors are very difficult to shrink, which is why they lag behind processors
Now as for why you need capacitors in DRAM: How do you think DRAM holds its data? The capacitors provide energy to the DRAM cell. DRAM has to do this over many clock cycles. Processors do not.
The tricky part is shrinking a capacitor without reducing its effectiveness. To get the same amount of energy from a smaller volume, you would need more energy density. And it would seem Samsung has found a material that allows more density than the previous best that was used in DDR5-4800 chips.
DDR5-4800 chips from Samsung use 17nm, and have a slightly larger die size than Micron DDR5-4800 fabricated on 16nm. SK Hynix uses a 16.5nm node, but it's essentially the same die size, and bit density as Samsung 17nm
"The capacitors provide energy to the DRAM cell" capacitors are what stores the actual data. Capacitors might power everything but that's not relevant to this story nor what anyone is talking about.
"DRAM is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor" - Wikipedia
The capacitors are made in/on the silicon/layers not separate components. The capacitors will leak & the more you shrink them, the higher rate of leakage in proportion to capacity. You can shrink the logic but the capacitors won't shrink linearly with transistor size. Higher voltage & current of signalling to interface with CPU via long tracks need larger transistors than other logic. So you can use a smaller fab node but not all features can be shrunk at the same rate. Analogy: So instead of colouring a large area with a broad brush, color the same area with a smaller brush but you get no benefits except it costs more per m^2. YMMV.
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martinw - Thursday, May 18, 2023 - link
Interesting that the feature size for Samsung memory (12nm) is so much larger than for Samsung logic (3nm). Is there really such a big difference? Or does the 12nm figure still actually refer to some real physical characteristic of the memory cells, unlike logic 'nm' fantasy units?III-V - Thursday, May 18, 2023 - link
12nm, 3nm -- they no longer point to any actual dimension. They're now just marketing numbers, essentially.martinw - Thursday, May 18, 2023 - link
That's not really answering my question. I know about the marketing nm issue. I'm asking why the big difference (12nm vs 3nm) and if they are really different process sizes underneath or if there is another reason for the gap.qlum - Friday, May 19, 2023 - link
I would guess the biggest factor here is cost. Ram is mostly a commodity product, so unlike with cpu's having a bit faster / efficient memory chips is not worth a cost increase, besides that it just doesn't scale as well as logic anymore. This is also why AMD produces it's cache dies at a larger node than it's core on rdna3.shing3232 - Saturday, May 20, 2023 - link
because you are compare apple to orange.you are compare size of transistor to size of capacitors. Why orange is bigger than apple？
saratoga4 - Sunday, May 21, 2023 - link
Two things:Logic and dram processes are completely different, so the numbers are not comparable. In dram it's about the ability to make narrow but extremely tall capacitors. In logic it's about making transistors and wires. Asking why the feature sizes are different is like asking why horses are smaller than airplanes.
The numbers are literally nonsense. Almost 10 years ago Samsung started making what they branded as 10nm DRAM. This year they switched to denser 12nn DRAM, presumably because marketing likes that 12 was bigger than 10.
martinw - Monday, May 22, 2023 - link
Sigh. Does nobody read questions before answering? I am not asking why the feature sizes are different. Of course they are different. I am asking is 12nm actually represents any physical feature size on a DRAM chip.And no, Samsung never had branded 10nm DRAM. They had 10nm-class DRAM. That "class" word is doing a lot of heavy lifting here, and readers often skip over it. It is really just saying the first digit is a 1. So 10nm class is anywhere between 10nm and 19nm. 10 years ago it was nearer to 19nm. Now it is 12nm. But they certainly didn't "increase the number because marketing likes that 12 is bigger than 10"!
Yongsta - Friday, May 26, 2023 - link
Because it's almost impossible to make DRAM work at smaller sizes. Hence they're stuck at 12nm right now.mi1400 - Thursday, July 20, 2023 - link
I have a lot of respect for Samsung .. as they can build laptops which can shame 1U servers... by outpacing CAMM mumbo-jumbo through creating densest RAM / SODIMM instead of current direction of fastest ... capacitance on say 4nm could be issue but Samsung has to realize this era of AI, ML, LLM ... these projects should be doable by students and professionals on the go... CPUs are there but RAMs are falling behind cuz of giants to pin hopes in this aspect e.g. MS indulged in matching surface laptops with lipstick shades, Google having no direction except chromebooks, DELL/HP instead of working with SKHynix, Crucial, Samsung spewing own wheel reinventions, and Lenovo despite most democratic is juggling with who to stab with just 1 mem-bank and whom to bless with 4 mem-banks .. MSI, Gigabyte, Acer, Asus and custom xeon laptop makers are etc are just creating skins (think nokia phones) ... Out of System76 and Framework i think Framework is most promising but i dont know what is holding them to enable 256gb+ RAM laptops while avoiding CAMM wayAdramtech - Friday, May 19, 2023 - link
DRAM is really difficult to make smaller without capacitance issues.meacupla - Thursday, May 18, 2023 - link
The information you want is all there in the article.- Samsung is getting 20% more production per wafer, so that should give you a hint as to if this is really a die shrink or not.
- Capacitors are very difficult to shrink, which is why they lag behind processors
Now as for why you need capacitors in DRAM: How do you think DRAM holds its data? The capacitors provide energy to the DRAM cell. DRAM has to do this over many clock cycles. Processors do not.
The tricky part is shrinking a capacitor without reducing its effectiveness. To get the same amount of energy from a smaller volume, you would need more energy density.
And it would seem Samsung has found a material that allows more density than the previous best that was used in DDR5-4800 chips.
DDR5-4800 chips from Samsung use 17nm, and have a slightly larger die size than Micron DDR5-4800 fabricated on 16nm. SK Hynix uses a 16.5nm node, but it's essentially the same die size, and bit density as Samsung 17nm
Skeptical123 - Friday, May 19, 2023 - link
"The capacitors provide energy to the DRAM cell" capacitors are what stores the actual data. Capacitors might power everything but that's not relevant to this story nor what anyone is talking about."DRAM is a type of random-access semiconductor memory that stores each bit of data in a memory cell, usually consisting of a tiny capacitor and a transistor" - Wikipedia
meacupla - Friday, May 19, 2023 - link
Capacitors are difficult to shrink without reducing their effectiveness, and processors don't use capacitors.How is that not relevant?
tygrus - Monday, May 22, 2023 - link
The capacitors are made in/on the silicon/layers not separate components. The capacitors will leak & the more you shrink them, the higher rate of leakage in proportion to capacity. You can shrink the logic but the capacitors won't shrink linearly with transistor size. Higher voltage & current of signalling to interface with CPU via long tracks need larger transistors than other logic. So you can use a smaller fab node but not all features can be shrunk at the same rate.Analogy: So instead of colouring a large area with a broad brush, color the same area with a smaller brush but you get no benefits except it costs more per m^2. YMMV.
Pneumothorax - Sunday, May 21, 2023 - link
Any insight on why Micron is the worst at DDR5 speed scaling, Samsung is a bit better, while SK Hynix is the undisputed speed king in this gen?meacupla - Monday, May 22, 2023 - link
My best guess is SK hynix has the better, or more robust design when overclocking.you can see the memory die here, although the pictures are a bit small.
https://www.techinsights.com/blog/industry-leading...
nandnandnand - Saturday, May 20, 2023 - link
It's time for 3D DRAM.Anymoore - Tuesday, August 1, 2023 - link
At 1a, EUV use did not provide any advantages as far as final density concerned.