very nice coverage. I wonder if CXL 3.0 features will first be implemented over UCIE, with the system on chip roadmaps and 3d fab capabilities emerging.
I see that hotchips is going to have a day of cxl 3.0 sessions this month.
Anyone have numbers for latency? All I see are words like the same or reduced latency, for either CXL 3.0 or PCIe 6.0.
I like OpenCAPI a whole lot because it has much lower latency than PCIe. Intel was very confused and incompetent in touting Optane's latency and bandwidth if they were just going to attach it to PCIe, wiping out its advantages. They needed a new interface for Optane to really add value, and that was OpenCAPI. I never heard of CXL having any latency advantages – it always seemed inferior, and for memory it adds latency, which is a waste. We need to reduce the latency of our computing systems at this point.
very nice coverage. I wonder if CXL 3.0 features will first be implemented over UCIE, with the system on chip roadmaps and 3d fab capabilities emerging.
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JayNor - Saturday, August 6, 2022 - link
very nice coverage. I wonder if CXL 3.0 features will first be implemented over UCIE, with the system on chip roadmaps and 3d fab capabilities emerging.I see that hotchips is going to have a day of cxl 3.0 sessions this month.
JoeDuarte - Wednesday, August 24, 2022 - link
Anyone have numbers for latency? All I see are words like the same or reduced latency, for either CXL 3.0 or PCIe 6.0.I like OpenCAPI a whole lot because it has much lower latency than PCIe. Intel was very confused and incompetent in touting Optane's latency and bandwidth if they were just going to attach it to PCIe, wiping out its advantages. They needed a new interface for Optane to really add value, and that was OpenCAPI. I never heard of CXL having any latency advantages – it always seemed inferior, and for memory it adds latency, which is a waste. We need to reduce the latency of our computing systems at this point.
Priscillaarrison - Tuesday, October 4, 2022 - link
very nice coverage. I wonder if CXL 3.0 features will first be implemented over UCIE, with the system on chip roadmaps and 3d fab capabilities emerging.