Can CXL even match OMI for near-memory applications? (In terms of latency, naturally)
I know IBM claims OMI's on-DIMM controller only adds some 4ns of latency vs your typical DDR (5?) DIMM. What about CXL? I'd really like to see a standard that could in the future help replace serial DDR.
If they made DRAM that uses the PCIe phy to communicate with the CPU, we could see much more flexible setups where the same CPU can be set up either for many accelerators or just a ridiculous amount of memory bandwidth - without having to rely on HBM. More I/O per dollar as less pins are required for most consumers. PCIe 6.0 is expensive but if you're already making motherboards that support it you might as well go all out.
Good observations Wereweeb. I gave a presentation, link below, titled "Power and Latency Analysis of the Memory Tiering Pyramid" at FMS yesterday that clearly articulates how our industry now has the potential significantly benefit from OMI & CXL being under one roof!
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Kamen Rider Blade - Tuesday, August 2, 2022 - link
"There can be only one!"domboy - Tuesday, August 2, 2022 - link
"And he does not share power."samlebon2306 - Thursday, August 4, 2022 - link
Yep, the Oracle was rightWereweeb - Tuesday, August 2, 2022 - link
Can CXL even match OMI for near-memory applications? (In terms of latency, naturally)I know IBM claims OMI's on-DIMM controller only adds some 4ns of latency vs your typical DDR (5?) DIMM. What about CXL? I'd really like to see a standard that could in the future help replace serial DDR.
If they made DRAM that uses the PCIe phy to communicate with the CPU, we could see much more flexible setups where the same CPU can be set up either for many accelerators or just a ridiculous amount of memory bandwidth - without having to rely on HBM. More I/O per dollar as less pins are required for most consumers. PCIe 6.0 is expensive but if you're already making motherboards that support it you might as well go all out.
Kamen Rider Blade - Wednesday, August 3, 2022 - link
I don't think CXL was designed for DIMM's.That's why I'm excited that OMI connected to a On-DIMM controller has a chance to be pushed to JEDEC for standardization.
acantle - Wednesday, August 3, 2022 - link
Good observations Wereweeb. I gave a presentation, link below, titled "Power and Latency Analysis of the Memory Tiering Pyramid" at FMS yesterday that clearly articulates how our industry now has the potential significantly benefit from OMI & CXL being under one roof!https://youtu.be/Qc1BVlsYwvM
avariciousafrican - Thursday, August 4, 2022 - link
Good observations Wereweeb.