Intel's current plans are still very aggressive. In the end, they did not even achieve the PPA that they expected to get from 10nm. (Sorry I couldn't find the article about that.) Now currently, they're having problems with their drives for their GPUs...
So, don't count them out, but it's not looking good -- unless you believe their marketing team (Hint: Don't believe marketing.)
Are we talking about the same ADL? The one that beats AMD in performance by using double the power? I get that the 12900 is faster than the 5950, but more efficient? This very website shows the 5950x at 137w and the 12900k at 271w.
Apparently to some numbnuts on this site. INTEL throwing efficiency out of the window to improve performance means they are better than what AMD is able to produce. It's actually kind of hilarious.
I mean around 30-40W power alder lake is slightly faster no? In gaming and lightly threaded tasks? 12400 is slightly faster than 5600 at same power. Doesn't that make it more efficient? 12700H is faster than 5900HX at the same power. Intel doesn't scale well but because alder lake has higher IPC than Zen 3 it makes it more efficient for certain tasks. Also I specifically said expect 5950X and you still put 5950X on your message. You guys aren't even able to read properly and I'm the numbnut.
It's you who aren't able to read properly. 5900HX isn't 5900X. It's trivial to get more performance out of same power if you add low power cores. Mobile ADL has more cores than 5900HX. Similarly, I recently replaced the i7-6800K in my NAS with a Haswell Xeon with 12 cores. Result: More multi threaded performance, power draw halved (*measured*, not just TDP).
12400 may have the same TDP as a 5600. In reality it will suck more power because AMD's boost works differently.
TSMC is ahead and tends to deliver on their roadmaps. Intel is behind and tends not to. There's no reason to believe Intel will be ahead of TSMC in the next five years.
You children and your short memories. Intel started the game. They dominated for decades. One little misstep and you kids start rooting for the underdog.
Well get your yucks in now squiddo. TSMC's little time in the sun is quickly coming to a close.
The issue with Intel is whether it can deliver and deliver *on time*. Intel has had persistent problems with both for years, including its next-gen chips. Until Intel starts executing like TSMC does, I don’t think it’ll be competitive.
The mixed density number is not that helpful, would rather see separate numbers. Looks like a nice efficiency gain, although it's a completely new transistor type.
They did the same thing when they rolled out finfets. 20nn did the shrink, then 16FF rolled out FinFETs at similar density. The idea was that changing transistor technologies is really hard so they would do it separately from the shrink. Probably similar here since GAAFETs will be a similarly complex change.
Because nodes are not measurements, they are “significant technology improvements”. In this case, the improvements are in transistor (GAA) and metal (backside power delivery). The process MAY get improved lithography (and thus higher density), but that depends on ASML delivering enough high NA EUV machines on time, and TSMC don’t want to promise what they can;t be sure of, or delay GAA and backside power waiting for those machines.
N3 nodes are focused on getting the smallest FinFETs possible, an art that TSMC seems to have mastered, while N2 is likely focused on getting GAAFETs working with good yields to start with.
It's a significantly different process, and there's no reason for them to rush it and risk crashing into a wall like Intel did with their "10nm/7". In the follow up "sub-nodes" and in the next nodes they can focus on shrinking the transistors and then rearchitecting GAAFETs to be more dense.
I wonder if N2 will be a node like TSMC's 10nm and 20nm where it is specifically indicated not to be a long lived node, and will have only a few customers (i.e. Apple and a few others) and most will wait for N2P or N2E or whatever they call the tweaked version.
TSMC did sort of the same thing in reverse with N7, where that early version was made without EUV to remove risk but pointed most customers towards N7+ which was the less expensive version of N7 that used EUV for a few critical layers instead of SAQP.
I actually can't even think of any chips that used N7+ because the design rules weren't compatible with N7/N7P/N6. Maybe there were some in datacenter, but in consumer products, I'm drawing a blank.
I'd guess that "phase 1" 2nm isn't a die shrink as such as is just a technology change to Nanosheet at similar dimensions.. and expect a potential shrink later on. A but like how 16nm was same size as 20nm but changed from planar to finFET (in this case shrink came first then technology change) .. someone else commented on the 16.20nm thing elsewhere in these comments
Even with a less than stellar density improvement, it's still a significant advancement. Having a power reduction of around 30% coupled even with modest density improvements makes higher chip stacks at higher performance as compared to the preceding process more achievable. This could give you a stack of, for example, a cache chiplet, a CPU chiplet, an iGPU chiplet, and finally, a high speed memory chiplet for the iGPU. With reasonable power budgets, that could be a staggering amount of performance in something that's no more than two inches in both dimensions.
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Exotica - Thursday, June 16, 2022 - link
So does intel have a shot (if it doesn’t get delayed along the way) to regain process leadership with 20a and 18a in 2024-25?ballsystemlord - Thursday, June 16, 2022 - link
Intel's current plans are still very aggressive. In the end, they did not even achieve the PPA that they expected to get from 10nm. (Sorry I couldn't find the article about that.)Now currently, they're having problems with their drives for their GPUs...
So, don't count them out, but it's not looking good -- unless you believe their marketing team (Hint: Don't believe marketing.)
ddhelmet - Friday, June 17, 2022 - link
I mean Alder Lake is more efficient than zen 3 and zen 3+ on desktop and mobile. Excluding the beast that is 5950X.Daeros - Friday, June 17, 2022 - link
Are we talking about the same ADL? The one that beats AMD in performance by using double the power? I get that the 12900 is faster than the 5950, but more efficient? This very website shows the 5950x at 137w and the 12900k at 271w.NeuralNexus - Friday, June 17, 2022 - link
Apparently to some numbnuts on this site. INTEL throwing efficiency out of the window to improve performance means they are better than what AMD is able to produce. It's actually kind of hilarious.ddhelmet - Saturday, June 18, 2022 - link
I mean around 30-40W power alder lake is slightly faster no? In gaming and lightly threaded tasks? 12400 is slightly faster than 5600 at same power. Doesn't that make it more efficient? 12700H is faster than 5900HX at the same power. Intel doesn't scale well but because alder lake has higher IPC than Zen 3 it makes it more efficient for certain tasks. Also I specifically said expect 5950X and you still put 5950X on your message. You guys aren't even able to read properly and I'm the numbnut.Soyuzu - Sunday, June 19, 2022 - link
You know that 12700H has 1.75x the core count of 5900HX, and 8 of which are PPA-optimized, right?bananaforscale - Saturday, July 2, 2022 - link
It's you who aren't able to read properly. 5900HX isn't 5900X. It's trivial to get more performance out of same power if you add low power cores. Mobile ADL has more cores than 5900HX. Similarly, I recently replaced the i7-6800K in my NAS with a Haswell Xeon with 12 cores. Result: More multi threaded performance, power draw halved (*measured*, not just TDP).12400 may have the same TDP as a 5600. In reality it will suck more power because AMD's boost works differently.
Wereweeb - Friday, June 17, 2022 - link
TSMC is ahead and tends to deliver on their roadmaps. Intel is behind and tends not to. There's no reason to believe Intel will be ahead of TSMC in the next five years.JKflipflop98 - Thursday, July 7, 2022 - link
You children and your short memories. Intel started the game. They dominated for decades. One little misstep and you kids start rooting for the underdog.Well get your yucks in now squiddo. TSMC's little time in the sun is quickly coming to a close.
OreoCookie - Wednesday, June 29, 2022 - link
The issue with Intel is whether it can deliver and deliver *on time*. Intel has had persistent problems with both for years, including its next-gen chips. Until Intel starts executing like TSMC does, I don’t think it’ll be competitive.nandnandnand - Thursday, June 16, 2022 - link
Finally, some good effing food.The mixed density number is not that helpful, would rather see separate numbers. Looks like a nice efficiency gain, although it's a completely new transistor type.
lemurbutton - Thursday, June 16, 2022 - link
Why is the density increase only 1.1x compared to N3E? This seems extremely small for a full node.nandnandnand - Thursday, June 16, 2022 - link
It's an average that includes SRAM and analog scaling, so that dragged it down. Maybe they'll break it down more later.ballsystemlord - Thursday, June 16, 2022 - link
Actually, it says *greater than* 1.1. The exact scaling might not be known yet so it could grow.saratoga4 - Thursday, June 16, 2022 - link
They did the same thing when they rolled out finfets. 20nn did the shrink, then 16FF rolled out FinFETs at similar density. The idea was that changing transistor technologies is really hard so they would do it separately from the shrink. Probably similar here since GAAFETs will be a similarly complex change.name99 - Friday, June 17, 2022 - link
Because nodes are not measurements, they are “significant technology improvements”.In this case, the improvements are in transistor (GAA) and metal (backside power delivery).
The process MAY get improved lithography (and thus higher density), but that depends on ASML delivering enough high NA EUV machines on time, and TSMC don’t want to promise what they can;t be sure of, or delay GAA and backside power waiting for those machines.
Wereweeb - Friday, June 17, 2022 - link
N3 nodes are focused on getting the smallest FinFETs possible, an art that TSMC seems to have mastered, while N2 is likely focused on getting GAAFETs working with good yields to start with.It's a significantly different process, and there's no reason for them to rush it and risk crashing into a wall like Intel did with their "10nm/7". In the follow up "sub-nodes" and in the next nodes they can focus on shrinking the transistors and then rearchitecting GAAFETs to be more dense.
Doug_S - Saturday, June 18, 2022 - link
I wonder if N2 will be a node like TSMC's 10nm and 20nm where it is specifically indicated not to be a long lived node, and will have only a few customers (i.e. Apple and a few others) and most will wait for N2P or N2E or whatever they call the tweaked version.TSMC did sort of the same thing in reverse with N7, where that early version was made without EUV to remove risk but pointed most customers towards N7+ which was the less expensive version of N7 that used EUV for a few critical layers instead of SAQP.
JasonMZW20 - Tuesday, July 19, 2022 - link
I actually can't even think of any chips that used N7+ because the design rules weren't compatible with N7/N7P/N6. Maybe there were some in datacenter, but in consumer products, I'm drawing a blank.xol - Sunday, June 19, 2022 - link
Typical diagram shows 1 nanosheet to be about the same width of a 2/3 fin finFET (standard for non-low power devices)eg https://www.imec-int.com/en/imec-magazine/imec-mag... or https://www.anandtech.com/show/15865/intel-to-use-...
I'd guess that "phase 1" 2nm isn't a die shrink as such as is just a technology change to Nanosheet at similar dimensions.. and expect a potential shrink later on. A but like how 16nm was same size as 20nm but changed from planar to finFET (in this case shrink came first then technology change) .. someone else commented on the 16.20nm thing elsewhere in these comments
lightningz71 - Friday, June 17, 2022 - link
Even with a less than stellar density improvement, it's still a significant advancement. Having a power reduction of around 30% coupled even with modest density improvements makes higher chip stacks at higher performance as compared to the preceding process more achievable. This could give you a stack of, for example, a cache chiplet, a CPU chiplet, an iGPU chiplet, and finally, a high speed memory chiplet for the iGPU. With reasonable power budgets, that could be a staggering amount of performance in something that's no more than two inches in both dimensions.