Probably not until they enable the high density libraries with Intel 3 in 2024. At that point it will be more of a business decision as to whether their own process or TSMC’s process gives them a better product and at what price. So… stay tuned I guess.
HelloThere33, yea, Intel sees 6 nm and 3 nm TSMC allotment as a buffer taking from competitors and within this TSMC process range a test lab to compare against their own inhouse developments. mb
not happening until 2024 at the earliest, and not a great idea either considering TSMC can help free up so much capacity. maybe it'll make sense once their new fabs are up and ASML can get more EUV out.
And don't forget that with hoarding all TSMC 3nm, they prevent Apple/ AMD/ NVidia for using it. Well, not that those companies planning to use 3nm for now.
Correct. The Intel fans are deluded on their purchase of fab space from TSMC. Apple gets first dibs. Just processor investments to TSMC in 2022 for Apple are over $17 billion.
Interesting . . . It is very odd the direct comparison of "IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery" from January 6, 2019, with the AT article "Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance" . . .
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Any idea whether mass production will start by Q2-Q3 of 2023? I'm curious to see if meteor lake ships on time.
Is it known whether the delays with pointe vecchio and sapphire rapids are to do with manufacturing the tiles, or with packaging them, or with validation or something else? Intel seems to be struggling with execution these days....
Intel 4 = 7nm How can you trust a company that deliberately seeks to confuse its customers like this? All done to make it appear they have some sort of equivalency with TSMC when such is not the case.
All while other fabs claim "7nm" etc while they cheese other pieces of the design too? Who cares at this point. It was a more useful metric back when transistors were way larger and easier to shrink, but at this time... lots of different parts of the die shrink at varying rates. And there's no consensus between the fabs what to call what. Not sure what happened to ITRS.
There hasn't been any correlation between the nominal size of the node and the size of any actual feature since they were still naming processes in microns, not nanometers. TSMC and Samsung (and GloFo before they got out of the leading-edge node business) started iterating the marketing names for their nodes on process improvements that didn't actually involve smaller features, and after a few years of that while Intel didn't call any of the respins of 14nm "13nm" or "12nm" or even "11nm" what was really TSMC getting a full node ahead of Intel looked to uniformed observers (which it seems like there are legions of now) like they were two full nodes ahead.
The funny bit about all this is that Intel didn't bother changing the names until TSMC were very close to being two full nodes ahead.
Intel 7 is roughly comparable to TSMC N7 now, but it does have worse measured density in shipping products and worse power characteristics at high clock speeds. Historically this is the weakest Intel have been, and it's telling that this was when they finally decided to change up their node names to suit marketing demands.
They historically didn't sell access to their fabs to third parties. Intel's 14nm being eqivalent to someone else's 10nm made no difference when only Intel parts were being manufactured on it and it didn't have to be marketed.
Outside of internet flame wars I'm not all that sure how many people going on about "14nm++++++ Intel vs 12nm AMD" when that 12nm process was also previously branded GloFlo 14nm+ actually affected sales of Intel 9000 and AMD 2000, especially when people actually looked at benchmark data for those two generations. AMD might have had the smaller number, but it was quite apparent the gulf was in their manufacturing process until they moved to TSMC a year later.
Too bad TSMC is on the bring of 3nm by the time intel will be on a 5nm equivalent. And TSMC already is on “4nm”. There will not be a “intel supremacy” in the next years.
If Intel and TSMC come pretty close to hitting their public roadmaps (or experience similar levels of delays, or TSMC's are worse), Intel will have the lead at 18A. That's certainly not a given, but it's certainly possible.
Nice try, but Intel is first of all a lot of talk. After their many blunders they have first to prove that their new node is good at all. Stop being such a huge fanboy. It’s unlikely intel will overtake TSMC, the Asians are just better with this. Get used to it.
Odd comment considering TSMC (and Intel, AMD, etc.) hires engineers from all around the world, including the US.
Intel seems to be hitting their roadmap, the to 18A changes are going to be more iterative than the major swap to EUV was (and they definitely had gains while not delivering a product, issue was cost which has come way down).
Congratulations. You've written the dumbest thing I've read on the internet this week.
You children and your short memories.
In either case it won't really matter as once China seizes TSMC by force they'll be so sanctioned and embargo'd that they won't be able to make chips anymore anyways.
Yeah, I know. Right? I seriously thought they might do it when Russia went into Ukraine. There's no way the West could deal with both of those crises at once.
I'm sure China is watching the Ukraine invasion and taking very good notes.
This isn't consistent with what we know so far. Intel 4's quoted transistor density is close to N5 but slightly worse, though we won't know until Intel release some data on a shipping product, so that's a wait until some time in 2023 to see whether Intel 4 can match up to a process that was first ramping for volume in the middle of 2020.
Another thing we do already know is that Intel claimed a higher density than TSMC N7 for their 10nm node, while in practice, high-performance products shipping on TSMC N7 are usually ~10-20% more dense than anything that has ever released on any 10nm variant.
In conclusion: Intel 4 looks good enough for Intel's needs, 3 should be better, and if they execute to their plan they'll catch back up soon enough.
Well, instead of simply repeating these claims half a dozen times, why not provide some numbers & ideally a source, so we can better appreciate the differences?
Looks like intel 4 is denser than tsmc N4 (probably not as efficient), still competitive with what amd is using and by 2024 we'll see another huge jump with intel 3 and 20A
Actually it's inaccurate. The first major share of TSMC N3 is held by Apple & Intel combined. AMD & NVIDIA will get access to TSMC N3 only in 2024 at best. By 2024, Intel is coming out with Intel 20A which is light years ahead of TSMC N3.
In essence, by the time AMD & NVIDIA gets access to TSMC N3, intel will already be a FULL node ahead of it's competitors.
They don't have a more dense node. Measured density in shipping products based on Intel's 10nm / Intel 7 node variants is lower than TSMC N7, and if the difference between their quoted and actual density remains fairly consistent between nodes then Intel 4 will not be as dense as TSMC N5.
It’s certainly true that Intel products aren’t very dense relative to what they claim for their node, but this has been the case extending to before Sandybridge. Even Alchemist isn’t very dense relative to other gpu architectures. Intel would rather sacrifice area for better power and performance characteristics, so using their products as demonstrative of the node doesn’t seem accurate. Intel 4 won’t be as dense as N4 for the very simple fact that no one is trying to build a dense product on Intel 4.
The second iteration of Intel 7 is actually not that bad. The HP library offers better performance that alder lake at the same power envelop. This year, AMD's Zen 4 will offer good performance/power efficiency. But, raptor lake with take the performance crown due to the new Intel 7's HP libraries. But the power draw is gonna be a bit of a problem.
Intel 4 is not a 7nm process node. It's a far superior node compared to TSMC N5 & even TSMC N4. Actually, intel 4's HP library outpaces the upcoming TSMC N3's by a narrow margin which is very significant.
So, how many years will it be before this rebranded 7nm can actually mass-produce a die larger than Tiger Lake Quad?
The delays on Sapphire Rapids tells us the yield for large dies still sucks for Superfin. Probably going to be 2026 before their rebranded 7nm process can make a chip larger than Alder Lake.
They will solve the issue of big dies by no longer manufacturing big dies. The modular tile based meteor lake enables them to mix and match small tiles, connected by emib, and increase yields
Do you think Alder Lake desktop chips are not mass produced? Because that's, erm, an interesting contention (both the 8P/8E and 6P/0E dies are larger than Tiger Lake U, the former significantly so). I suppose you could argue if you're using a definition of "mass produced" that wouldn't include any server chips that you might be able to argue Tiger Lake H wasn't "mass produced", but 8-core Tiger Lake is definitely significantly bigger than 4-core Tiger Lake too (though smaller than 8P+8E Alder Lake-S). And of course Ice Lake SP is a much bigger die than those. And I suppose you could argue 6P+8E Alder Lake H/P isn't available yet (I couldn't find numbers on that one, but odds are it's about the same size as 8P+8E Alder Lake S because of the bigger GPU) but it's certainly going to be a very high volume part if it's not yet.
At any rate, Tiger Lake U is about 145 mm^2, 6P/0E Alder Lake S is ~165 mm^2, Tiger Lake H ~190 mm^2, 8P+8e Alder Lake S is ~215 mm^2, and Ice Lake SP is 370 mm^2. And all of those are certainly available today.
Thanks for the die size confirmations. My calcs have SF10 at a 20% cost advantage over TSMC 7 and at parity with TSMC 5. Intel achieves this on focused device production in a strategy that necessitates Intel trail one node behind securing and maintaining a downward sloping cost curve on continuing the trailing node depreciation for cost : price / margin advantage as TSMC moves too every next node upward sloping cost curve. On this lagging technique Intel cost is always decreasing as TSMCs cost increases. But if Intel slips two nodes behind the technique looses its parity ability and any leading advantage. I tracked Ice 10, Tiger U and Tiger H SF10 closely in terms of production economics. Some of that production data is here;
Tiger U was a quad SF10 validation run there are a ton of them; huge surplus in the channel. My thesis is their characteristics are all over the specification. Tiger H octa was next and then the SR 14C. I don't believe SR is delayed in terms of production readiness but because of business of compute validation irrelevant to the enterprise market on hardware so far ahead of software. Also SR being tough to swallow by the OEM dealer group accustom to Skylake and Cascade lake low price (high volume $400 to $600 on average per unit run end) as Intel kibble good enough to keep business humming along on ow price and availability.
Sapphire Rapids just in the packaging cost is obviously not a low priced product and I think OEMs are having a tough time swallowing SR for the market beyond hyperscale / public cloud business of compute that are not enterprise and mass market of business customers. I also see hyperscale market as monetarily saturated moving to all kinds of acceleration.
For example, how could the big five procure SR in excess of immediate demand knowing they can't resale overage into the secondary market to lower their procurement cost, on hardware so far ahead of software [?] the channel wont buy it ahead of mass market validation.
So does Intel fill the channel following XSL/XCL which is still highly demanded on known stable and low price verse Ice at 10 end generation product? Will Intel respin Ice to SF 10? Will Intel just keep producing Cascade Lake for the masses. Will OEMs take SR knowing software whole product voids and a risky price.
See my comment line for Xeon today channel sales trend observations:
> rebranded 7nm can actually mass-produce a die larger than Tiger Lake Quad?
Tiger Lake was/is produced on Intel 10 nm SuperFin (rebranded as "Intel 10", formerly called 10 nm++). Tiger Lake H exists and is a 8-core part, as @drothgery said.
> The delays on Sapphire Rapids tells us the yield for large dies still sucks for Superfin.
SPR, like ADL, is made on Intel 10 nm Enhanced Super Fin (rebranded as "Intel 7", formerly Intel 10 nm+++).
Mode_13th, writing off SR so said delayed on yield [?] is a traditional thesis, low yield high cost.
But consider 4 die at a very manufacturable 350 mm^2. They're not XCC. I acknowledge yield remains a question. I personally believe the package is damn expensive and the component validated in a non production environment, initially, focused on business of compute workloads recommendation systems and OLTP that's general enough and overlap with private / public cloud virtualized storage and server but that's not the general enterprise business market. SR has been in risk production since q3 2021 on my take supporting DDR5 validation and so has Genoa since q3 2021 memory had to have more than a simulator.
Subsequently my SR thesis is 1) the product is not whole as of yet outside business of compute applications, and 2) Intel OEM dealer group can't sell a less than whole platform; hardware ahead of software and, 3) the price low yield or otherwise is excessive for what Skylake and Cascade Lake provide for systems integration channel on corporate enterprise standardized compute.
So what fills the channel if not for XSL, XCL continuing? My answer is large cache Milan verse cache starved Skylake and Cascade Lake+r albeit AMD would have to aggressively supply Milan which I think is about to ramp the XSL XCL replacement market is to big to ignore. McNamara said Milan production would continue at AMD financial analyst day. I considered that the most important statement of AMD's public disclosure.
Finally, I give Intel [more] credit for getting its fabrication act together observing TL U to H. Alder is on same process as SR and Alder so said by Intel surpassing 15 M units of production. Intel for decades loves to produce around 245mm^2 consumer market components and 14/12nm HCC around 400 mm^2 was highly manufacturable granted a different process.
Intel can do stupid things, make decisions that lack integrity and definitively has made severe errors but I never count them out. Ice volume in the channel increased 16% in last nine weeks and splits channel market share on available volume with Milan. Ice is not SF10/7 but the predecessor fin fet process compound weekly channel supply volume growth is 6% per week over 59 weeks begins March 31. Intel says 4 M Ice have sold which is not a large volume for mainstay Xeon and I believe its because 1) market is standardized on XSL/XCL, 2) Ice is not SF10 and run end, 3) Its not whole for the mass market on hardware ahead of software.
This is what the market is currently buying XSL + XCL by core grade SKU sales trend last nine weeks;
Xeon Ice full line at 10 over 1st 59 weeks CWG (channel supply volume) = 6% Xeon Cascade Lake at 14/12 over 1st 59 weeks = 71.9% that's telling Xeon Ivy Bridge, 22 nm out the gate was difficult over 1st 59 weeks = 4.6% Xeon Haswell, 22 nm was easy out the gate over 1st 59 weeks = 33.87% Result; Ice looks like a v2 out the gate.
Broadwell quad Crystal Well 14 nm tough out the gate 1st 59 weeks = 1% Ice U quad at 10 over 59 weeks CWG (channel supply volume) = 19.8% Tiger U quad SF10/7 over 59 weeks CWG = 15.9% Tiger H octa SF10/7 over 50 weeks run to date CWG = 13.6% Alder S i9/i7/i5 only over 30 weeks rune to date CWG = 64.8% Intel's producing on SF10/7
We can look at another Ice supply aspect;
P40C = 4.91% full run to date supply and + 53% in the prior 9 weeks P38C = 2.09% + 300% P36C = 5.98% + 170% P32C = 10.18% + 70% G32C = 7.53% + 192% G28C = 14.60% + 74% G26C = 2.15% < 60% G24C = 7.29% + 89% G20C = 0.26% and n/a currently G18C = 4.31% + 12.5% G16C = 6.53% + 26% G12C = 1.75% < 60% G8C = 3.57% + 166% All Silver = 25.51% + 37% All W = 3.34% < 40%
Milan volume in the channel grew 33% in the prior nine weeks and on a compound weekly basis at 10.8% over 49 consecutive weeks beginning June 19, 2021. I have Milan production at 9,644,933 units to date which is a lot for AMD.
We can look at another Milan supply aspect;
64C = 35.21% full run to date supply and + 19.5% in the prior 9 weeks 56C = 3.67% + 11% 48C = 3.62% + 420% 32C = 18.21% + 91% 28C = 2.66% + 34% 24C = 20.26% + 19.6% 16C = 14.05% + 58.8% 8C = 2.33 < 16.7% G20C = 0.26% and n/a currently G18C = 4.31% + 12.5% G16C = 6.53% + 26% G12C = 1.75% < 60% G8C = 3.57% + 166% All Silver = 25.51% + 37% All W = 3.34% < 40%
Okay, Xeon Ice is being supplied similar to Ivy v2 that had a slow start. But Alder is yielding and 90% of volume are i9/i7 all else is organic fall out from sort. My thesis remains. Sapphire Rapids package is costly. SR hardware is ahead of general market applications software. Intel OEMs are bocking at procurement price and the ability to sell other than to 'business of compute' in question minimally on SR not yet validated in the general use market. No hyperscale public cloud operation will want Intel dealer group as its master distributor a direct Intel CPU sales environment primarily.
SR currently comes with costs that are not fully understood.
Well yes. But, in order to beat that, Intel would mostly have to build a lower-clocking chip, which isn't likely. They might be able to find a few other little power savings here and there, but the main power savings usually comes from the process node.
Then again, it's probably safe to assume they're not going to build the same chip they have today that merely clocks 20% higher. So, we should expect them to invest some of the efficiency gains in wider structures, better scheduling, or more cache. And that could conceivably deliver more than 20% performance, at ISO-power. However, at ISO-clocks, such a chip would lose much of the 40% power savings.
Once you get to 30W or so, Apple's M1 isn't really ahead anymore, a lot of the advantage has to do with a very good node, no overhead of X86 (there's a min. of power usage for the instruction sets, for same node/efficiency this is probably at the 35W mark currently). With just the node improvement they should be able to catch up at the 20W mark I would guess, which is ultrabook territory, question is whether TSMC will have a better node by then as well, and Intel has substantially improved regarding their efficiency cores (also interesting how Apple M2 graph comparison didn't compare perf/watt with them directly and instead used a middle binned 1255P).
Incorrect. Even the Apple's latest silicon M2 falls short in performance when compared to the older Intel Alder Lake (HX series). Apple's focussed on power efficiency. When it comes to raw performance, they still have to catch up.
And considering Zen 4 & Raptor Lake are on the horizon, Apple doesn't stand much of a chance. They can pull ahead only if they come out with a M2 with a higher power draw which is essential for high performance. But Apple won't do that i guess.
This is why Intel had to rename their nodes to TSMC node names. Intel 7nm was always TSMC 4/5nm equivalent node, but since idiots like you have no idea, Intel had to rename their nodes to follow TSMC node names.
But since it wasn't ready for the M2, there's a decent chance TSMC N3 will be shipping in the GPU tiles of Meteor Lake before it's used for a volume laptop, desktop, or server CPU. At least, it's improbable the M2 Pro, Max, or Ultra will be on N3 when the base M2 is on N4.
@Ryan Why are some of the metal layers listed as tuples and others not? Like this: "Metal 5, 6" Are they related somehow in the silicon with respect to their non-tuple counterparts?
The layers in tuples share the same metallization and pitch. I'll be able to add the specific numbers to the table later, once Intel publishes their full presentation.
The red highlighted area in the first picture is clearly not the area that has been expanded in the second picture. I think the red box in the first picture needs to expand by about 1/3 in size and move to the left about 100% of its current width.
It’s worse than that. The red box in the first picture is in completely the wrong place. In the first picture, you see the two large prongs coming down - the expanded area is below the first prong, but the red box is underneath the second prong.
There are several shadowy connectors or defects(?) in the second picture that line up with what you can see in the first picture - eg on each of the second row of horizontal bars.
Since Intel 4 will be produced at Fab 34 in Ireland and given Fab 34 received their first UEV tool transplanted from Oregon in April ’22, then keeping in mind that Intel is only receiving 1 EUV tool per month, Fab 34 will not have received all 13 EUV tools required for Meteor Lake until May ’23.
Once the last tool is installed, an additional 3-4 months for calibration, which pushes the beginning of Risk Production to 4Q23.
This schedule seems to indicate that Meteor Lake will not start Volume Production in ’23.
If Intel releases Meteor Lake before 2024, it will likely be from low yield (<20%) Risk Production, similar to Samsung 4nm (<20% yield).
Competition is good and certainly point taken that TSMC’s ‘5nm’ is no more accurate than Intel’s ‘4’ terminology, but the roadmap showing Intel going from 4 -> 3 -> 20a -> 18a in 5 quarters seems incredibly aggressive. I’d be willing to wager foolish sums that timeline won’t be met.
Is this paper generally available? I visited the initial link for the presentation at the conference but couldn't find the pdf in question. A Google search also turned up nothing.
Even though Intel has distributed it to the press with no further embargo, it looks like they haven't posted it for download. As it's not clear that I have permission to distribute it, I've poked Intel to see what's up.
Intel is not releasing the paper at this time. I may be publicly available on June 17th, which is when VLSI Symposium's content is released more widely.
Strange that so much is being discussed about this paper (not just at this site) even before Intel presented it - what happened to the usual embargo?
Anyway, it's already mentioned at two other sites that the 30 nm minimum pitch is not done by EUV but by self-aligned quadruple patterning (as before).
"Strange that so much is being discussed about this paper (not just at this site) even before Intel presented it - what happened to the usual embargo?"
Intel gave the press a preview of the paper ahead of the Tuesday embargo. So our embargo has already passed.
another presentation Thursday on an SRAM design on Intel-4 process... C24-1 - Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
If Intel does pull even with TSMC at 20A or ahead at 18A, it will be interesting to see if Apple considers using Intel Fab Services for at least part of their production.
Historically they don't shift supplier that quickly when in an established partnership, only when a trend is established, so I'd guess you need to see TSMC faling behind until they would switch.
Well, historically apple has always had more than one supplier for all their key components. But when it comes to fabs, they're stuck with tsmc for obvious reasons. No other fabs offer good nodes. Once Intel IFS opens gate with advanced nodes than tsmc, apple will sure grab a bite. It's in their DNA.
Overall this looks very positive for Intel, but as always, there's a couple of bits that make me chuckle when I read between the lines. For example:
"In short, Intel is seeing above-average gains in both frequencies and power efficiency." This is much easier to achieve when your previous process had below-average properties in these areas! Intel 7 was a huge improvement over the original 10nm, but 10nm may have been one of the worst manufacturing processes in recent memory, and 7 still shows some of its weaknesses, like the unreasonably large surge in power needed to hit competitive clock speeds.
Intel is fixing their issues is what I can understand and the EUV process finally. Plus the best part is Clockspeed boost. However the worst part is bigLittle trash for Intel CPUs until 2025+ they retire the CORE series by then.
The future is going to be uArch and Clockspeed. Intel's 7 / 10nm is already denser than TSMC N7, Intel 4 is going to compete with AMD's Zen 5 on N5 or N4 nodes at best. So it all boils to the uArch scalability. Since Zen 4 is showing 5.5GHz under the ADL PL2 I think AMD is winning the Arch design, Zen is a new uArch vs CORE.
Apple is irrelevant garbage because they do not compete in XEON and Mainstream LGA socket, they fight in the BGA land.
To me it's all meaningless because soon there won't be any node improvements any more. The question is, how far can architecture go, and can there be some new development in computing?
Since it's more of an unknown I will go by my dystopian picture of it.
2030 is where Great Reset is being planned so I'm assuming some massive changes in computing might occur at that point, give or take by 2035. But I believe that DIY PC will die eventually because of high cost in manufacturing and slowly market waning, looking at the volume of Smartphones and BGA Lapjokes that ship is very high in numbers people are fine with consuming use and throw junk more than anything, imagine an AirPods division is out pacing AMD, Nvidia and likes in sheer profits !! That's the level of consumerism you have right now. It's insane.
AR/VR/MR once Apple releases the product, Mainstream adoption will be very high, which will result on Stadia / XCloud type garbage taking over, once that is done PC will die because masses do not care about owning, or even buying a great piece of art (games which are free from political ideologies).
But yea silicon won't go away until 2040, I doubt that. The corporations who want extreme power will make it centralized computing like the top Japanese Sci-Fi ones like say - Ergo Proxy, Psycho-Pass etc. But with ofc worse idpol.
Yes, the DIY PC is slowly dying, and consumerist mobile is taking over, if it hasn't already done so. Plus, I suppose with the Web 3.0, metaverse nonsense, there'll be an ever greater push towards AR, VR, whatever it's called these days.
Concerning computing, while I grant that some new discovery could throw open the doors, I wouldn't be surprised there's some fundamental limit to computation---well, serial computation at any rate---and we're asymptotically approaching it. A bit like the speed of light. And, if the universe itself is being computed, our AMD and Intel CPUs will never run faster than that. Of course, science can open new doors and has done so before; it might be something that is inconceivable at present.
> I wouldn't be surprised there's some fundamental limit to computation
Obviously, but you saw that paper on the efficiency of computation as temperatures drop, right? We could be seeing future cloud computers build to run at LN2 temperatures (which is kind of a bad thing, considering the energy required by all that cooling). But if it turns out you can get 10x the computation for 3x the energy, it'll happen.
Of course, this will push high-end CPUs even further out of reach for home users and even small/medium businesses.
I've come across superconductivity at very low temperatures, and there are exotic materials that can do strange things. Certainly, I'll be glad to see any improvement, coming from the material side of the coin; but what I was really thinking about was a limit, from principles, to how fast operations can be done. Increasingly, quantum physics shows that everything seems to be information, so quite likely, I'd say, there are only so many operations allowed at the lowest level, and our CPUs are ultimately piggybacking on that system. Something like that, though it's hard to put into words. (But that is more like a clock rate. Perhaps it goes even deeper, to how information can be combined or viewed, in a timeless arena.)
"If a civilization wants to maximize computation it appears rational to aestivate until the far future in order to exploit the low temperature environment: this can produce a 10^30 multiplier of achievable computation."
I've only skimmed the paper, so I don't have a sense of what the shape of the curve looks like. Presumably, we could design computers that are much faster than what we have today, if they required temperatures near absolute-zero to operate. This is basically happening with quantum computers, though perhaps there's also a way to achieve significant gains with classical computers.
Thanks, I'll read that. But just judging from the abstract, I already don't agree with it. It seems far-fetched that any civilisation would go into hibernation just for the sake of exploiting future computation. A more parsimonious explanation for Fermi's paradox would be that, one, the universe is very, very big, making it difficult for fellow lifeforms to find or communicate with each other (needle in a haystack).* Two, life could be exceedingly rare, which would make us pretty much alone in the cosmos. A third, more unlikely, one would be that we are alone, though that seems a waste of a good universe.
* Space is currently expanding, at an ever increasing rate, and there are whole regions that we will be cut off from us for ever. Signals won't be able to reach those regions in time, effectively making separate universes.
> It seems far-fetched that any civilisation would go into hibernation > just for the sake of exploiting future computation.
Only if it's comprised of individual, mortal, self-interested entities. If you had some kind of eternal super-being (which one can imagine, with digital consciousness), then you might indeed choose to use only enough resources to keep other civilizations from consuming them first.
I know it's a poor analogy, but in the wild, large animals without predators tend to be long-lived, move slowly, and have a low birthrate. And they don't have any special payoff, at the end.
A very interesting thought. But then, consider this: it's possible that a being of that nature, if housed within this universe, would be more keenly sensitive to the end of usable energy in the far future, and, if there were not much time left for a working universe, the super computation would be dearly bought. Unless, of course, it could, like AC, harness that power to reverse entropy.
super computation might rise aggregation of consciousness, but from my point of view, is less efficient than evolution results (introduced from intangible capable *entity* beyond all) and we even don't understand a perception of perpetuum mobile, then how should a subsystem like electron/light/logic driven computing "power"?
Well, yes. Corporations want stable revenue streams which they control. Thus, renting computing power is a lot more attractive than selling you the hardware. And due to various accounting quirks, it often works out to be more attractive for businesses customers than actually buying the depreciating assets that we call "computers". For consumers, it gets rid of that big up-front price that's a stumbling block for many.
In essence, the only thing really wrong with it is the pesky little problem of the power dynamic being somewhat upside down. And that's mainly a problem due to monopolistic behavior and lack of standards limiting portability between cloud platforms.
Though I haven't used it myself, I've certainly seen the benefits that cloud computing---AWS in particular---brings to businesses. Indeed, for many, it's allowed them to process a lot more than before and take their business to a new level, and the ease is preposterous. In an ideal world, from a purely design point of view, I like the idea of keeping related things together. But we live in a world of humans, and while cloud platforms are presently fantastic, it makes me uneasy that "being centered in the hands of a few" is swept under the carpet. Along with the fact of its being the current vogue, makes me instinctively against it.
> I believe that DIY PC will die eventually because of high cost in manufacturing and slowly market waning,
I think it'll be here for a long time. The Raspberry Pi shows how big the tinkerer market is. Lots of us rather run our own fileservers, than keep all data in the cloud. And there's quite a lot of room for PC makers to consolidate product tiers and still offer something meaningfully different than phone, laptop, or server chips.
> AirPods division is out pacing AMD, Nvidia and likes in sheer profits !!
I hadn't heard that. However, it's basically irrelevant to the point. There are lots of businesses and markets still bigger than AMD and Nvidia's, but as long as theirs is still profitable for someone, they'll keep at it.
And if Apple's vertical integration propels them to monopoly status, they could start to see themselves affected by more regulation or even broken up. I'm not saying it'll happen soon or in this type of political climate, but a lot can change in 5 years.
Everyone does this "BS", then. It's the norm for all of the chip vendors to make these kinds of announcements, well before there's any hardware available for independent testing.
You get the exact same types of announcements from ARM, Apple, Qualcomm, IBM, AMD, SiFive, and many smaller companies.
In Intel's case, they have a new Foundry business, somewhat like TSMC, where a customer can contract them to make a chip. So, like TSMC and Samsung, Intel has to announce their new process node as part of their "sales" strategy, to attract business for their new production lines. This also means they need to face a higher level of disclosure and honesty, because their foundry ambitions would be sabotaged if they developed a reputation for doing otherwise.
That *is* very interesting. One big take-away for me is how they put it in perspective against prior Intel node improvements. That graph shows this one will be their smallest improvement, yet. The 40% density improvement pales in comparison to the 170% improvement they got from the transition between 14 nm to their 10 nm nodes.
I also got a chuckle out of the irony that "Intel 7" (i.e. 10 nm eSF) actually has slightly bigger features than their prior 10 nm nodes.
Rocket Lake was basically taking a 4.36 mm^2 Ice Lake core, which turned into a 10.7 mm^2 core on 14 nm - a 146% size disparity that roughly tallies with the claimed density differences. However, that's pretty non-competitive, when compared against Zen2's 3.54 mm area - more than 3x!
Wider features / paths, interconnect is king. Less dense transistor layouts = more insulator. I don't buy the economics of a shrink now. Performance increase is expected but manufacturability / yield a must have requirement. Thanks for the Rocket pointer. mb
comparison of reduction in functional groups scales over decreasing nodes sizes (AMD) https://cdn.mos.cms.futurecdn.net/yxcZZ8c8kxhJvAxw... (e.g. some 2010's cpu's SRAM parameters would be ~55% area and 70% transistor share, other statistics for area shares of analog/sram/logics circuits on chiplet design?)
intel should trash their pride like amd and simply use tsmc/samsung foundry for high margin products, i.e. cpu and server gpu. if not, xeon will be further backward than epyc.
Actually, that isn't a good idea. TSMC has hiked their prices twice in the last couple of years. This has a severe impact on the profit margins of companies like AMD & NVIDIA. This severely impacts their business esp. their lower & mid range products where the margins are already low!
> intel should ... simply use tsmc/samsung foundry for high margin products, i.e. cpu and server gpu.
Weren't they rumored to have bought up TSMC N3E capacity for a future Xeon CPU?
The bigger issue is going to be volume. There's no way Intel can substitute its current production volume with TSMC/Samsung. AMD is currently supply-limited to just about 10% of the server market share, with Intel owning most of the rest.
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patel21 - Monday, June 13, 2022 - link
So, does this mean that they can use their own nodes for their GPUs?noobmaster69 - Monday, June 13, 2022 - link
Probably not until they enable the high density libraries with Intel 3 in 2024. At that point it will be more of a business decision as to whether their own process or TSMC’s process gives them a better product and at what price. So… stay tuned I guess.HelloThere33 - Monday, June 13, 2022 - link
They will have no spare capacity for that, instead they will milk tsmc 3nm dry untill no longer relevant when they move full on to A18Bruzzone - Tuesday, June 14, 2022 - link
HelloThere33, yea, Intel sees 6 nm and 3 nm TSMC allotment as a buffer taking from competitors and within this TSMC process range a test lab to compare against their own inhouse developments. mbwhatthe123 - Monday, June 13, 2022 - link
not happening until 2024 at the earliest, and not a great idea either considering TSMC can help free up so much capacity. maybe it'll make sense once their new fabs are up and ASML can get more EUV out.t.s - Tuesday, June 14, 2022 - link
And don't forget that with hoarding all TSMC 3nm, they prevent Apple/ AMD/ NVidia for using it. Well, not that those companies planning to use 3nm for now.BradEK - Wednesday, June 15, 2022 - link
Even Intel cannot outspend Apple. If Apple wants 3nm, Apple will get 3nm.....haukionkannel - Thursday, June 16, 2022 - link
Intel don´t have to outspend Apple. It is enough to them to outspend AMD...mdriftmeyer - Sunday, June 26, 2022 - link
Correct. The Intel fans are deluded on their purchase of fab space from TSMC. Apple gets first dibs. Just processor investments to TSMC in 2022 for Apple are over $17 billion.Abort-Retry-Fail - Monday, June 13, 2022 - link
LOL
"This comment is apparently spam and we do not allow spam comments"
Abort-Retry-Fail - Monday, June 13, 2022 - link
Interesting . . .It is very odd the direct comparison of "IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery" from January 6, 2019, with the AT article "Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance" . . .
"This comment is apparently spam and we do not allow spam comments"
ballsystemlord - Monday, June 13, 2022 - link
BTW: You have to remove the ' from the above title in order to search for it. Otherwise, you get "Server Error in '/' Application."ballsystemlord - Monday, June 13, 2022 - link
I know, it's so annoying.techjunkie123 - Monday, June 13, 2022 - link
Any idea whether mass production will start by Q2-Q3 of 2023? I'm curious to see if meteor lake ships on time.Is it known whether the delays with pointe vecchio and sapphire rapids are to do with manufacturing the tiles, or with packaging them, or with validation or something else? Intel seems to be struggling with execution these days....
ballsystemlord - Monday, June 13, 2022 - link
I don't even think Intel knows. But see MLID, the youtube's recent video, https://youtu.be/rIN3IbA3vCYWaltC - Monday, June 13, 2022 - link
Intel 4 = 7nm How can you trust a company that deliberately seeks to confuse its customers like this? All done to make it appear they have some sort of equivalency with TSMC when such is not the case.HelloThere33 - Monday, June 13, 2022 - link
Remind me plesse, why does tsmc's 7nm is called "7nm"?HelloThere33 - Monday, June 13, 2022 - link
Please*colinstu - Monday, June 13, 2022 - link
All while other fabs claim "7nm" etc while they cheese other pieces of the design too?Who cares at this point. It was a more useful metric back when transistors were way larger and easier to shrink, but at this time... lots of different parts of the die shrink at varying rates. And there's no consensus between the fabs what to call what. Not sure what happened to ITRS.
drothgery - Monday, June 13, 2022 - link
Exactly.There hasn't been any correlation between the nominal size of the node and the size of any actual feature since they were still naming processes in microns, not nanometers. TSMC and Samsung (and GloFo before they got out of the leading-edge node business) started iterating the marketing names for their nodes on process improvements that didn't actually involve smaller features, and after a few years of that while Intel didn't call any of the respins of 14nm "13nm" or "12nm" or even "11nm" what was really TSMC getting a full node ahead of Intel looked to uniformed observers (which it seems like there are legions of now) like they were two full nodes ahead.
Spunjji - Wednesday, June 15, 2022 - link
The funny bit about all this is that Intel didn't bother changing the names until TSMC were very close to being two full nodes ahead.Intel 7 is roughly comparable to TSMC N7 now, but it does have worse measured density in shipping products and worse power characteristics at high clock speeds. Historically this is the weakest Intel have been, and it's telling that this was when they finally decided to change up their node names to suit marketing demands.
cakeisamadeupdrg - Thursday, June 16, 2022 - link
They historically didn't sell access to their fabs to third parties. Intel's 14nm being eqivalent to someone else's 10nm made no difference when only Intel parts were being manufactured on it and it didn't have to be marketed.Outside of internet flame wars I'm not all that sure how many people going on about "14nm++++++ Intel vs 12nm AMD" when that 12nm process was also previously branded GloFlo 14nm+ actually affected sales of Intel 9000 and AMD 2000, especially when people actually looked at benchmark data for those two generations. AMD might have had the smaller number, but it was quite apparent the gulf was in their manufacturing process until they moved to TSMC a year later.
Turbofrog - Monday, June 13, 2022 - link
160-200 MTr/mm^2 for Intel 4 is the same density as TSMC N5/N4.Khanan - Monday, June 13, 2022 - link
Too bad TSMC is on the bring of 3nm by the time intel will be on a 5nm equivalent. And TSMC already is on “4nm”. There will not be a “intel supremacy” in the next years.drothgery - Monday, June 13, 2022 - link
If Intel and TSMC come pretty close to hitting their public roadmaps (or experience similar levels of delays, or TSMC's are worse), Intel will have the lead at 18A. That's certainly not a given, but it's certainly possible.JJSteve - Monday, June 13, 2022 - link
Intel 4 is closer to TSMC N3 than N5. And TSMC N2 is not happening until 2026. Try again.Khanan - Monday, June 13, 2022 - link
Nice try, but Intel is first of all a lot of talk. After their many blunders they have first to prove that their new node is good at all. Stop being such a huge fanboy. It’s unlikely intel will overtake TSMC, the Asians are just better with this. Get used to it.RSAUser - Tuesday, June 14, 2022 - link
Odd comment considering TSMC (and Intel, AMD, etc.) hires engineers from all around the world, including the US.Intel seems to be hitting their roadmap, the to 18A changes are going to be more iterative than the major swap to EUV was (and they definitely had gains while not delivering a product, issue was cost which has come way down).
JKflipflop98 - Wednesday, June 15, 2022 - link
Congratulations. You've written the dumbest thing I've read on the internet this week.You children and your short memories.
In either case it won't really matter as once China seizes TSMC by force they'll be so sanctioned and embargo'd that they won't be able to make chips anymore anyways.
mode_13h - Thursday, June 16, 2022 - link
> once China seizes TSMC by forceYeah, I know. Right? I seriously thought they might do it when Russia went into Ukraine. There's no way the West could deal with both of those crises at once.
I'm sure China is watching the Ukraine invasion and taking very good notes.
Spunjji - Wednesday, June 15, 2022 - link
This isn't consistent with what we know so far. Intel 4's quoted transistor density is close to N5 but slightly worse, though we won't know until Intel release some data on a shipping product, so that's a wait until some time in 2023 to see whether Intel 4 can match up to a process that was first ramping for volume in the middle of 2020.Another thing we do already know is that Intel claimed a higher density than TSMC N7 for their 10nm node, while in practice, high-performance products shipping on TSMC N7 are usually ~10-20% more dense than anything that has ever released on any 10nm variant.
In conclusion: Intel 4 looks good enough for Intel's needs, 3 should be better, and if they execute to their plan they'll catch back up soon enough.
SiliconFly - Friday, June 24, 2022 - link
Actually, Intel 4 is better than TSMC N5 & N4 and closer to TSMC N3.mode_13h - Saturday, June 25, 2022 - link
Well, instead of simply repeating these claims half a dozen times, why not provide some numbers & ideally a source, so we can better appreciate the differences?Morawka - Tuesday, August 16, 2022 - link
he's going off transistor density.Charizzardoh - Tuesday, June 14, 2022 - link
Looks like intel 4 is denser than tsmc N4 (probably not as efficient), still competitive with what amd is using and by 2024 we'll see another huge jump with intel 3 and 20ASiliconFly - Friday, June 24, 2022 - link
Actually it's inaccurate. The first major share of TSMC N3 is held by Apple & Intel combined. AMD & NVIDIA will get access to TSMC N3 only in 2024 at best. By 2024, Intel is coming out with Intel 20A which is light years ahead of TSMC N3.In essence, by the time AMD & NVIDIA gets access to TSMC N3, intel will already be a FULL node ahead of it's competitors.
Charizzardoh - Tuesday, June 14, 2022 - link
People complaing about intel node naming when they have the denser node, with both 7 and 4, while samsung names 5 and 4 nm their terrible 7+ nodeSpunjji - Wednesday, June 15, 2022 - link
They don't have a more dense node. Measured density in shipping products based on Intel's 10nm / Intel 7 node variants is lower than TSMC N7, and if the difference between their quoted and actual density remains fairly consistent between nodes then Intel 4 will not be as dense as TSMC N5.Charizzardoh - Wednesday, June 15, 2022 - link
What is your source?Otritus - Friday, June 17, 2022 - link
It’s certainly true that Intel products aren’t very dense relative to what they claim for their node, but this has been the case extending to before Sandybridge. Even Alchemist isn’t very dense relative to other gpu architectures. Intel would rather sacrifice area for better power and performance characteristics, so using their products as demonstrative of the node doesn’t seem accurate. Intel 4 won’t be as dense as N4 for the very simple fact that no one is trying to build a dense product on Intel 4.SiliconFly - Friday, June 24, 2022 - link
The second iteration of Intel 7 is actually not that bad. The HP library offers better performance that alder lake at the same power envelop. This year, AMD's Zen 4 will offer good performance/power efficiency. But, raptor lake with take the performance crown due to the new Intel 7's HP libraries. But the power draw is gonna be a bit of a problem.mode_13h - Saturday, June 25, 2022 - link
> The HP library offers better performance that alder lake at the same power envelop.How much? And where did they announce this?
haukionkannel - Thursday, June 16, 2022 - link
Intel 4 is about the same as TSMC 4nm that is not even near 4nm... Same cemmercial department talk everywhere!SiliconFly - Friday, June 24, 2022 - link
Intel 4 is not a 7nm process node. It's a far superior node compared to TSMC N5 & even TSMC N4. Actually, intel 4's HP library outpaces the upcoming TSMC N3's by a narrow margin which is very significant.defaultluser - Monday, June 13, 2022 - link
So, how many years will it be before this rebranded 7nm can actually mass-produce a die larger than Tiger Lake Quad?The delays on Sapphire Rapids tells us the yield for large dies still sucks for Superfin. Probably going to be 2026 before their rebranded 7nm process can make a chip larger than Alder Lake.
HelloThere33 - Monday, June 13, 2022 - link
They will solve the issue of big dies by no longer manufacturing big dies. The modular tile based meteor lake enables them to mix and match small tiles, connected by emib, and increase yieldsShorty_ - Monday, June 13, 2022 - link
SPR is being delayed because of memory controller issues as is Genoa. It’s not a yield issue (at least it’s not being reported as one)Spunjji - Wednesday, June 15, 2022 - link
Is Genoa delayed?I can't find any info on that, or on it being due to memory controllers.It not being reported as a yield issue doesn't mean much. Intel never reported yield issues on Ice Lake, either.
drothgery - Monday, June 13, 2022 - link
Do you think Alder Lake desktop chips are not mass produced? Because that's, erm, an interesting contention (both the 8P/8E and 6P/0E dies are larger than Tiger Lake U, the former significantly so). I suppose you could argue if you're using a definition of "mass produced" that wouldn't include any server chips that you might be able to argue Tiger Lake H wasn't "mass produced", but 8-core Tiger Lake is definitely significantly bigger than 4-core Tiger Lake too (though smaller than 8P+8E Alder Lake-S). And of course Ice Lake SP is a much bigger die than those. And I suppose you could argue 6P+8E Alder Lake H/P isn't available yet (I couldn't find numbers on that one, but odds are it's about the same size as 8P+8E Alder Lake S because of the bigger GPU) but it's certainly going to be a very high volume part if it's not yet.At any rate, Tiger Lake U is about 145 mm^2, 6P/0E Alder Lake S is ~165 mm^2, Tiger Lake H ~190 mm^2, 8P+8e Alder Lake S is ~215 mm^2, and Ice Lake SP is 370 mm^2. And all of those are certainly available today.
mode_13h - Tuesday, June 14, 2022 - link
> Ice Lake SP is 370 mm^2But it's made on old Intel 10 nm+, not SuperFin or Enhanced SuperFin.
Spunjji - Wednesday, June 15, 2022 - link
It also has abysmal yields!mode_13h - Thursday, June 16, 2022 - link
No disagreement. I just wanted to establish a fact, though its relevance remains unclear (at least to me).Bruzzone - Tuesday, June 14, 2022 - link
drothgery and mode_13th,Thanks for the die size confirmations. My calcs have SF10 at a 20% cost advantage over TSMC 7 and at parity with TSMC 5. Intel achieves this on focused device production in a strategy that necessitates Intel trail one node behind securing and maintaining a downward sloping cost curve on continuing the trailing node depreciation for cost : price / margin advantage as TSMC moves too every next node upward sloping cost curve. On this lagging technique Intel cost is always decreasing as TSMCs cost increases. But if Intel slips two nodes behind the technique looses its parity ability and any leading advantage. I tracked Ice 10, Tiger U and Tiger H SF10 closely in terms of production economics. Some of that production data is here;
https://seekingalpha.com/instablog/5030701-mike-br...
https://seekingalpha.com/instablog/5030701-mike-br...
Tiger U was a quad SF10 validation run there are a ton of them; huge surplus in the channel. My thesis is their characteristics are all over the specification. Tiger H octa was next and then the SR 14C. I don't believe SR is delayed in terms of production readiness but because of business of compute validation irrelevant to the enterprise market on hardware so far ahead of software. Also SR being tough to swallow by the OEM dealer group accustom to Skylake and Cascade lake low price (high volume $400 to $600 on average per unit run end) as Intel kibble good enough to keep business humming along on ow price and availability.
Sapphire Rapids just in the packaging cost is obviously not a low priced product and I think OEMs are having a tough time swallowing SR for the market beyond hyperscale / public cloud business of compute that are not enterprise and mass market of business customers. I also see hyperscale market as monetarily saturated moving to all kinds of acceleration.
For example, how could the big five procure SR in excess of immediate demand knowing they can't resale overage into the secondary market to lower their procurement cost, on hardware so far ahead of software [?] the channel wont buy it ahead of mass market validation.
So does Intel fill the channel following XSL/XCL which is still highly demanded on known stable and low price verse Ice at 10 end generation product? Will Intel respin Ice to SF 10? Will Intel just keep producing Cascade Lake for the masses. Will OEMs take SR knowing software whole product voids and a risky price.
See my comment line for Xeon today channel sales trend observations:
https://seekingalpha.com/user/5030701/comments
Mike Bruzzone, Camp Marketing
mode_13h - Tuesday, June 14, 2022 - link
> rebranded 7nm can actually mass-produce a die larger than Tiger Lake Quad?Tiger Lake was/is produced on Intel 10 nm SuperFin (rebranded as "Intel 10", formerly called 10 nm++). Tiger Lake H exists and is a 8-core part, as @drothgery said.
> The delays on Sapphire Rapids tells us the yield for large dies still sucks for Superfin.
SPR, like ADL, is made on Intel 10 nm Enhanced Super Fin (rebranded as "Intel 7", formerly Intel 10 nm+++).
Bruzzone - Wednesday, June 15, 2022 - link
Mode_13th, writing off SR so said delayed on yield [?] is a traditional thesis, low yield high cost.But consider 4 die at a very manufacturable 350 mm^2. They're not XCC. I acknowledge yield remains a question. I personally believe the package is damn expensive and the component validated in a non production environment, initially, focused on business of compute workloads recommendation systems and OLTP that's general enough and overlap with private / public cloud virtualized storage and server but that's not the general enterprise business market. SR has been in risk production since q3 2021 on my take supporting DDR5 validation and so has Genoa since q3 2021 memory had to have more than a simulator.
Subsequently my SR thesis is 1) the product is not whole as of yet outside business of compute applications, and 2) Intel OEM dealer group can't sell a less than whole platform; hardware ahead of software and, 3) the price low yield or otherwise is excessive for what Skylake and Cascade Lake provide for systems integration channel on corporate enterprise standardized compute.
So what fills the channel if not for XSL, XCL continuing? My answer is large cache Milan verse cache starved Skylake and Cascade Lake+r albeit AMD would have to aggressively supply Milan which I think is about to ramp the XSL XCL replacement market is to big to ignore. McNamara said Milan production would continue at AMD financial analyst day. I considered that the most important statement of AMD's public disclosure.
Finally, I give Intel [more] credit for getting its fabrication act together observing TL U to H. Alder is on same process as SR and Alder so said by Intel surpassing 15 M units of production. Intel for decades loves to produce around 245mm^2 consumer market components and 14/12nm HCC around 400 mm^2 was highly manufacturable granted a different process.
Intel can do stupid things, make decisions that lack integrity and definitively has made severe errors but I never count them out. Ice volume in the channel increased 16% in last nine weeks and splits channel market share on available volume with Milan. Ice is not SF10/7 but the predecessor fin fet process compound weekly channel supply volume growth is 6% per week over 59 weeks begins March 31. Intel says 4 M Ice have sold which is not a large volume for mainstay Xeon and I believe its because 1) market is standardized on XSL/XCL, 2) Ice is not SF10 and run end, 3) Its not whole for the mass market on hardware ahead of software.
This is what the market is currently buying XSL + XCL by core grade SKU sales trend last nine weeks;
4C = 1.86% supply + 24.2% gain last nine week (trade in)
6C = 1.86% + 9.7%
8C = 12.26% < 38.2% shows a sweet spot
10C = 7.89% < 45% shows applications by core sweet spot
12C = 11.04% < 20.7%
14C = 11,89% < 40.09% sweet spot
16C = 11.78% < 8.5%
18C = 6.8% + 20.6% trade in
20C = 9.51% < 14.9% applications sweet spot enters virtual
22C = 2.26% + 1.4%
24C = 8.31% < 2.1%
26C = 2.08% + 2%
28C = 12.44% + 4.4% (virtual environment)
Xeon Ice full line at 10 over 1st 59 weeks CWG (channel supply volume) = 6%
Xeon Cascade Lake at 14/12 over 1st 59 weeks = 71.9% that's telling
Xeon Ivy Bridge, 22 nm out the gate was difficult over 1st 59 weeks = 4.6%
Xeon Haswell, 22 nm was easy out the gate over 1st 59 weeks = 33.87%
Result; Ice looks like a v2 out the gate.
Broadwell quad Crystal Well 14 nm tough out the gate 1st 59 weeks = 1%
Ice U quad at 10 over 59 weeks CWG (channel supply volume) = 19.8%
Tiger U quad SF10/7 over 59 weeks CWG = 15.9%
Tiger H octa SF10/7 over 50 weeks run to date CWG = 13.6%
Alder S i9/i7/i5 only over 30 weeks rune to date CWG = 64.8% Intel's producing on SF10/7
We can look at another Ice supply aspect;
P40C = 4.91% full run to date supply and + 53% in the prior 9 weeks
P38C = 2.09% + 300%
P36C = 5.98% + 170%
P32C = 10.18% + 70%
G32C = 7.53% + 192%
G28C = 14.60% + 74%
G26C = 2.15% < 60%
G24C = 7.29% + 89%
G20C = 0.26% and n/a currently
G18C = 4.31% + 12.5%
G16C = 6.53% + 26%
G12C = 1.75% < 60%
G8C = 3.57% + 166%
All Silver = 25.51% + 37%
All W = 3.34% < 40%
Milan volume in the channel grew 33% in the prior nine weeks and on a compound weekly basis at 10.8% over 49 consecutive weeks beginning June 19, 2021. I have Milan production at 9,644,933 units to date which is a lot for AMD.
We can look at another Milan supply aspect;
64C = 35.21% full run to date supply and + 19.5% in the prior 9 weeks
56C = 3.67% + 11%
48C = 3.62% + 420%
32C = 18.21% + 91%
28C = 2.66% + 34%
24C = 20.26% + 19.6%
16C = 14.05% + 58.8%
8C = 2.33 < 16.7%
G20C = 0.26% and n/a currently
G18C = 4.31% + 12.5%
G16C = 6.53% + 26%
G12C = 1.75% < 60%
G8C = 3.57% + 166%
All Silver = 25.51% + 37%
All W = 3.34% < 40%
Okay, Xeon Ice is being supplied similar to Ivy v2 that had a slow start. But Alder is yielding and 90% of volume are i9/i7 all else is organic fall out from sort. My thesis remains. Sapphire Rapids package is costly. SR hardware is ahead of general market applications software. Intel OEMs are bocking at procurement price and the ability to sell other than to 'business of compute' in question minimally on SR not yet validated in the general use market. No hyperscale public cloud operation will want Intel dealer group as its master distributor a direct Intel CPU sales environment primarily.
SR currently comes with costs that are not fully understood.
Mike Bruzzone, Camp Marketing
Speedfriend - Monday, June 13, 2022 - link
surely 20% perf per watt gains isnt going to get them anywhere near where Apple is now. Will they get more out of the design side?Jorgp2 - Monday, June 13, 2022 - link
Do you not understand that this is for the manufacturing node, not the actual end product?mode_13h - Tuesday, June 14, 2022 - link
Well yes. But, in order to beat that, Intel would mostly have to build a lower-clocking chip, which isn't likely. They might be able to find a few other little power savings here and there, but the main power savings usually comes from the process node.mode_13h - Wednesday, June 15, 2022 - link
Then again, it's probably safe to assume they're not going to build the same chip they have today that merely clocks 20% higher. So, we should expect them to invest some of the efficiency gains in wider structures, better scheduling, or more cache. And that could conceivably deliver more than 20% performance, at ISO-power. However, at ISO-clocks, such a chip would lose much of the 40% power savings.HelloThere33 - Monday, June 13, 2022 - link
No, but the 40% less power for same perf willmode_13h - Wednesday, June 15, 2022 - link
Not directly, but maybe if they use that additional power budget wisely.RSAUser - Tuesday, June 14, 2022 - link
Once you get to 30W or so, Apple's M1 isn't really ahead anymore, a lot of the advantage has to do with a very good node, no overhead of X86 (there's a min. of power usage for the instruction sets, for same node/efficiency this is probably at the 35W mark currently). With just the node improvement they should be able to catch up at the 20W mark I would guess, which is ultrabook territory, question is whether TSMC will have a better node by then as well, and Intel has substantially improved regarding their efficiency cores (also interesting how Apple M2 graph comparison didn't compare perf/watt with them directly and instead used a middle binned 1255P).SiliconFly - Friday, June 24, 2022 - link
Incorrect. Even the Apple's latest silicon M2 falls short in performance when compared to the older Intel Alder Lake (HX series). Apple's focussed on power efficiency. When it comes to raw performance, they still have to catch up.And considering Zen 4 & Raptor Lake are on the horizon, Apple doesn't stand much of a chance. They can pull ahead only if they come out with a M2 with a higher power draw which is essential for high performance. But Apple won't do that i guess.
Silma - Monday, June 13, 2022 - link
TLDR: Intel will go 7 nm in 2023 when everybody and their mothers go 4 nm.JJSteve - Monday, June 13, 2022 - link
This is why Intel had to rename their nodes to TSMC node names. Intel 7nm was always TSMC 4/5nm equivalent node, but since idiots like you have no idea, Intel had to rename their nodes to follow TSMC node names.Khanan - Monday, June 13, 2022 - link
Nobody cares, TSMC will be on 3 and 2 soon. Intel will still be behind. Stay toxic.drothgery - Monday, June 13, 2022 - link
But since it wasn't ready for the M2, there's a decent chance TSMC N3 will be shipping in the GPU tiles of Meteor Lake before it's used for a volume laptop, desktop, or server CPU. At least, it's improbable the M2 Pro, Max, or Ultra will be on N3 when the base M2 is on N4.JJSteve - Monday, June 13, 2022 - link
TSMC N2 is 2026 node lol.SiliconFly - Friday, June 24, 2022 - link
Again wrong. Intel 4 is better than TSMC N5 & N4 and it's HP library is slightly better than TSMC N3.The upcoming Intel 20A is light years ahead of the upcoming TSMC N3.
TSMC N2 is not even in the radar! But, Intel 18A is already well on track. Starting 2024, TSMC is history.
SiliconFly - Friday, June 24, 2022 - link
Wrong. The upcoming Intel 4 node is far superior than TSMC N5 & N4 and is on par with TSMC N3.Qasar - Saturday, June 25, 2022 - link
prove it, post a link to where you get this.ballsystemlord - Monday, June 13, 2022 - link
@Ryan Why are some of the metal layers listed as tuples and others not? Like this: "Metal 5, 6"Are they related somehow in the silicon with respect to their non-tuple counterparts?
Ryan Smith - Monday, June 13, 2022 - link
The layers in tuples share the same metallization and pitch. I'll be able to add the specific numbers to the table later, once Intel publishes their full presentation.ballsystemlord - Monday, June 13, 2022 - link
Thanks!Ryan Smith - Tuesday, June 14, 2022 - link
And updated.bji - Monday, June 13, 2022 - link
The red highlighted area in the first picture is clearly not the area that has been expanded in the second picture. I think the red box in the first picture needs to expand by about 1/3 in size and move to the left about 100% of its current width.Tomatotech - Tuesday, June 14, 2022 - link
It’s worse than that. The red box in the first picture is in completely the wrong place. In the first picture, you see the two large prongs coming down - the expanded area is below the first prong, but the red box is underneath the second prong.There are several shadowy connectors or defects(?) in the second picture that line up with what you can see in the first picture - eg on each of the second row of horizontal bars.
Doug_S - Monday, June 13, 2022 - link
Given the clock rates it is operating at, that "industry standard core" is presumably some sort of ARM core like A72 or A76.isofilm - Monday, June 13, 2022 - link
Since Intel 4 will be produced at Fab 34 in Ireland and given Fab 34 received their first UEV tool transplanted from Oregon in April ’22, then keeping in mind that Intel is only receiving 1 EUV tool per month, Fab 34 will not have received all 13 EUV tools required for Meteor Lake until May ’23.Once the last tool is installed, an additional 3-4 months for calibration, which pushes the beginning of Risk Production to 4Q23.
This schedule seems to indicate that Meteor Lake will not start Volume Production in ’23.
If Intel releases Meteor Lake before 2024, it will likely be from low yield (<20%) Risk Production, similar to Samsung 4nm (<20% yield).
JayNor - Monday, June 13, 2022 - link
Intels D1X mod3 recently opened, and was reportedly installing tools since last August.Zoolook - Wednesday, June 15, 2022 - link
They don't necessarily need all EUV scanners in place to start risk production only for full production speed.SiliconFly - Friday, June 24, 2022 - link
Intel 4 risk production in Q4 2022 & volume/ramp in Q2 2023. Products in market by late Q3 2023 or early Q4 2023.Sunrise089 - Monday, June 13, 2022 - link
Competition is good and certainly point taken that TSMC’s ‘5nm’ is no more accurate than Intel’s ‘4’ terminology, but the roadmap showing Intel going from 4 -> 3 -> 20a -> 18a in 5 quarters seems incredibly aggressive. I’d be willing to wager foolish sums that timeline won’t be met.techjunkie123 - Monday, June 13, 2022 - link
Almost like they're hoping investors will 5ake the bait.....tuxRoller - Monday, June 13, 2022 - link
Is this paper generally available?I visited the initial link for the presentation at the conference but couldn't find the pdf in question.
A Google search also turned up nothing.
Ryan Smith - Monday, June 13, 2022 - link
Even though Intel has distributed it to the press with no further embargo, it looks like they haven't posted it for download. As it's not clear that I have permission to distribute it, I've poked Intel to see what's up.Ryan Smith - Tuesday, June 14, 2022 - link
Intel is not releasing the paper at this time. I may be publicly available on June 17th, which is when VLSI Symposium's content is released more widely.mode_13h - Wednesday, June 15, 2022 - link
Thanks for the follow up!Anymoore - Monday, June 13, 2022 - link
Strange that so much is being discussed about this paper (not just at this site) even before Intel presented it - what happened to the usual embargo?Anyway, it's already mentioned at two other sites that the 30 nm minimum pitch is not done by EUV but by self-aligned quadruple patterning (as before).
Ryan Smith - Tuesday, June 14, 2022 - link
"Strange that so much is being discussed about this paper (not just at this site) even before Intel presented it - what happened to the usual embargo?"Intel gave the press a preview of the paper ahead of the Tuesday embargo. So our embargo has already passed.
JayNor - Monday, June 13, 2022 - link
Intel also has a presentation today on an Intel-4 RISC-V chip.C8-1: An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS
JayNor - Monday, June 13, 2022 - link
another presentation Thursday on an SRAM design on Intel-4 process...C24-1 - Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
KPOM - Tuesday, June 14, 2022 - link
If Intel does pull even with TSMC at 20A or ahead at 18A, it will be interesting to see if Apple considers using Intel Fab Services for at least part of their production.Zoolook - Wednesday, June 15, 2022 - link
Historically they don't shift supplier that quickly when in an established partnership, only when a trend is established, so I'd guess you need to see TSMC faling behind until they would switch.SiliconFly - Friday, June 24, 2022 - link
Well, historically apple has always had more than one supplier for all their key components. But when it comes to fabs, they're stuck with tsmc for obvious reasons. No other fabs offer good nodes. Once Intel IFS opens gate with advanced nodes than tsmc, apple will sure grab a bite. It's in their DNA.Spunjji - Wednesday, June 15, 2022 - link
Overall this looks very positive for Intel, but as always, there's a couple of bits that make me chuckle when I read between the lines. For example:"In short, Intel is seeing above-average gains in both frequencies and power efficiency."
This is much easier to achieve when your previous process had below-average properties in these areas! Intel 7 was a huge improvement over the original 10nm, but 10nm may have been one of the worst manufacturing processes in recent memory, and 7 still shows some of its weaknesses, like the unreasonably large surge in power needed to hit competitive clock speeds.
Silver5urfer - Friday, June 17, 2022 - link
Intel is fixing their issues is what I can understand and the EUV process finally. Plus the best part is Clockspeed boost. However the worst part is bigLittle trash for Intel CPUs until 2025+ they retire the CORE series by then.The future is going to be uArch and Clockspeed. Intel's 7 / 10nm is already denser than TSMC N7, Intel 4 is going to compete with AMD's Zen 5 on N5 or N4 nodes at best. So it all boils to the uArch scalability. Since Zen 4 is showing 5.5GHz under the ADL PL2 I think AMD is winning the Arch design, Zen is a new uArch vs CORE.
Apple is irrelevant garbage because they do not compete in XEON and Mainstream LGA socket, they fight in the BGA land.
GeoffreyA - Friday, June 17, 2022 - link
To me it's all meaningless because soon there won't be any node improvements any more. The question is, how far can architecture go, and can there be some new development in computing?Silver5urfer - Friday, June 17, 2022 - link
Since it's more of an unknown I will go by my dystopian picture of it.2030 is where Great Reset is being planned so I'm assuming some massive changes in computing might occur at that point, give or take by 2035. But I believe that DIY PC will die eventually because of high cost in manufacturing and slowly market waning, looking at the volume of Smartphones and BGA Lapjokes that ship is very high in numbers people are fine with consuming use and throw junk more than anything, imagine an AirPods division is out pacing AMD, Nvidia and likes in sheer profits !! That's the level of consumerism you have right now. It's insane.
AR/VR/MR once Apple releases the product, Mainstream adoption will be very high, which will result on Stadia / XCloud type garbage taking over, once that is done PC will die because masses do not care about owning, or even buying a great piece of art (games which are free from political ideologies).
But yea silicon won't go away until 2040, I doubt that. The corporations who want extreme power will make it centralized computing like the top Japanese Sci-Fi ones like say - Ergo Proxy, Psycho-Pass etc. But with ofc worse idpol.
GeoffreyA - Friday, June 17, 2022 - link
Yes, the DIY PC is slowly dying, and consumerist mobile is taking over, if it hasn't already done so. Plus, I suppose with the Web 3.0, metaverse nonsense, there'll be an ever greater push towards AR, VR, whatever it's called these days.Concerning computing, while I grant that some new discovery could throw open the doors, I wouldn't be surprised there's some fundamental limit to computation---well, serial computation at any rate---and we're asymptotically approaching it. A bit like the speed of light. And, if the universe itself is being computed, our AMD and Intel CPUs will never run faster than that. Of course, science can open new doors and has done so before; it might be something that is inconceivable at present.
mode_13h - Saturday, June 18, 2022 - link
> I wouldn't be surprised there's some fundamental limit to computationObviously, but you saw that paper on the efficiency of computation as temperatures drop, right? We could be seeing future cloud computers build to run at LN2 temperatures (which is kind of a bad thing, considering the energy required by all that cooling). But if it turns out you can get 10x the computation for 3x the energy, it'll happen.
Of course, this will push high-end CPUs even further out of reach for home users and even small/medium businesses.
GeoffreyA - Sunday, June 19, 2022 - link
I've come across superconductivity at very low temperatures, and there are exotic materials that can do strange things. Certainly, I'll be glad to see any improvement, coming from the material side of the coin; but what I was really thinking about was a limit, from principles, to how fast operations can be done. Increasingly, quantum physics shows that everything seems to be information, so quite likely, I'd say, there are only so many operations allowed at the lowest level, and our CPUs are ultimately piggybacking on that system. Something like that, though it's hard to put into words. (But that is more like a clock rate. Perhaps it goes even deeper, to how information can be combined or viewed, in a timeless arena.)mode_13h - Monday, June 20, 2022 - link
I was referring to this: https://mindmatters.ai/2020/10/researchers-the-ali...Here's the actual paper: https://arxiv.org/pdf/1705.03394.pdf
"If a civilization wants to maximize computation it appears rational to aestivate until the far future in order to exploit the low temperature environment: this can produce a 10^30 multiplier of achievable computation."
I've only skimmed the paper, so I don't have a sense of what the shape of the curve looks like. Presumably, we could design computers that are much faster than what we have today, if they required temperatures near absolute-zero to operate. This is basically happening with quantum computers, though perhaps there's also a way to achieve significant gains with classical computers.
GeoffreyA - Monday, June 20, 2022 - link
Thanks, I'll read that. But just judging from the abstract, I already don't agree with it. It seems far-fetched that any civilisation would go into hibernation just for the sake of exploiting future computation. A more parsimonious explanation for Fermi's paradox would be that, one, the universe is very, very big, making it difficult for fellow lifeforms to find or communicate with each other (needle in a haystack).* Two, life could be exceedingly rare, which would make us pretty much alone in the cosmos. A third, more unlikely, one would be that we are alone, though that seems a waste of a good universe.* Space is currently expanding, at an ever increasing rate, and there are whole regions that we will be cut off from us for ever. Signals won't be able to reach those regions in time, effectively making separate universes.
mode_13h - Monday, June 20, 2022 - link
> It seems far-fetched that any civilisation would go into hibernation> just for the sake of exploiting future computation.
Only if it's comprised of individual, mortal, self-interested entities. If you had some kind of eternal super-being (which one can imagine, with digital consciousness), then you might indeed choose to use only enough resources to keep other civilizations from consuming them first.
I know it's a poor analogy, but in the wild, large animals without predators tend to be long-lived, move slowly, and have a low birthrate. And they don't have any special payoff, at the end.
GeoffreyA - Thursday, June 23, 2022 - link
A very interesting thought. But then, consider this: it's possible that a being of that nature, if housed within this universe, would be more keenly sensitive to the end of usable energy in the far future, and, if there were not much time left for a working universe, the super computation would be dearly bought. Unless, of course, it could, like AC, harness that power to reverse entropy.back2future - Thursday, June 23, 2022 - link
super computation might rise aggregation of consciousness, but from my point of view, is less efficient than evolution results (introduced from intangible capable *entity* beyond all)and
we even don't understand a perception of perpetuum mobile, then how should a subsystem like electron/light/logic driven computing "power"?
GeoffreyA - Saturday, June 18, 2022 - link
"The corporations who want extreme power will make it centralized computing"Unwittingly, this is already happening with the current cloud obsession, computation increasingly being centered in the hands of a few: AWS, etc.
mode_13h - Monday, June 20, 2022 - link
Well, yes. Corporations want stable revenue streams which they control. Thus, renting computing power is a lot more attractive than selling you the hardware. And due to various accounting quirks, it often works out to be more attractive for businesses customers than actually buying the depreciating assets that we call "computers". For consumers, it gets rid of that big up-front price that's a stumbling block for many.In essence, the only thing really wrong with it is the pesky little problem of the power dynamic being somewhat upside down. And that's mainly a problem due to monopolistic behavior and lack of standards limiting portability between cloud platforms.
GeoffreyA - Monday, June 20, 2022 - link
Though I haven't used it myself, I've certainly seen the benefits that cloud computing---AWS in particular---brings to businesses. Indeed, for many, it's allowed them to process a lot more than before and take their business to a new level, and the ease is preposterous. In an ideal world, from a purely design point of view, I like the idea of keeping related things together. But we live in a world of humans, and while cloud platforms are presently fantastic, it makes me uneasy that "being centered in the hands of a few" is swept under the carpet. Along with the fact of its being the current vogue, makes me instinctively against it.mode_13h - Saturday, June 18, 2022 - link
> I believe that DIY PC will die eventually because of high cost in manufacturing and slowly market waning,I think it'll be here for a long time. The Raspberry Pi shows how big the tinkerer market is. Lots of us rather run our own fileservers, than keep all data in the cloud. And there's quite a lot of room for PC makers to consolidate product tiers and still offer something meaningfully different than phone, laptop, or server chips.
> AirPods division is out pacing AMD, Nvidia and likes in sheer profits !!
I hadn't heard that. However, it's basically irrelevant to the point. There are lots of businesses and markets still bigger than AMD and Nvidia's, but as long as theirs is still profitable for someone, they'll keep at it.
And if Apple's vertical integration propels them to monopoly status, they could start to see themselves affected by more regulation or even broken up. I'm not saying it'll happen soon or in this type of political climate, but a lot can change in 5 years.
iranterres - Monday, June 20, 2022 - link
Claiming performance without benchmarks is bullshit.mode_13h - Monday, June 20, 2022 - link
Everyone does this "BS", then. It's the norm for all of the chip vendors to make these kinds of announcements, well before there's any hardware available for independent testing.You get the exact same types of announcements from ARM, Apple, Qualcomm, IBM, AMD, SiFive, and many smaller companies.
In Intel's case, they have a new Foundry business, somewhat like TSMC, where a customer can contract them to make a chip. So, like TSMC and Samsung, Intel has to announce their new process node as part of their "sales" strategy, to attract business for their new production lines. This also means they need to face a higher level of disclosure and honesty, because their foundry ambitions would be sabotaged if they developed a reputation for doing otherwise.
Bruzzone - Monday, June 20, 2022 - link
Interesting complimentary report here at Semiwiki titled Intel 4 Deep Dive by Scotten Jones with IC Knowledge;https://semiwiki.com/semiconductor-manufacturers/i...
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mode_13h - Monday, June 20, 2022 - link
That *is* very interesting. One big take-away for me is how they put it in perspective against prior Intel node improvements. That graph shows this one will be their smallest improvement, yet. The 40% density improvement pales in comparison to the 170% improvement they got from the transition between 14 nm to their 10 nm nodes.I also got a chuckle out of the irony that "Intel 7" (i.e. 10 nm eSF) actually has slightly bigger features than their prior 10 nm nodes.
mode_13h - Monday, June 20, 2022 - link
> the 170% improvement they got from the transition between 14 nm to their 10 nm nodes.This reminded me of the area disparity between Ice Lake and Rocket Lake cores, shown at the bottom of this article:
https://chipsandcheese.com/2022/06/07/sunny-cove-i...
Rocket Lake was basically taking a 4.36 mm^2 Ice Lake core, which turned into a 10.7 mm^2 core on 14 nm - a 146% size disparity that roughly tallies with the claimed density differences. However, that's pretty non-competitive, when compared against Zen2's 3.54 mm area - more than 3x!
Bruzzone - Monday, June 20, 2022 - link
Wider features / paths, interconnect is king. Less dense transistor layouts = more insulator. I don't buy the economics of a shrink now. Performance increase is expected but manufacturability / yield a must have requirement. Thanks for the Rocket pointer. mbback2future - Friday, June 24, 2022 - link
comparison of reduction in functional groups scales over decreasing nodes sizes (AMD)https://cdn.mos.cms.futurecdn.net/yxcZZ8c8kxhJvAxw...
(e.g. some 2010's cpu's SRAM parameters would be ~55% area and 70% transistor share, other statistics for area shares of analog/sram/logics circuits on chiplet design?)
Adramtech - Wednesday, June 29, 2022 - link
The zoomed cross section needs to be moved over 4 spaces to the left, and made wider.zamroni - Friday, July 1, 2022 - link
intel should trash their pride like amd and simply use tsmc/samsung foundry for high margin products, i.e. cpu and server gpu.if not, xeon will be further backward than epyc.
SiliconFly - Friday, July 1, 2022 - link
Actually, that isn't a good idea. TSMC has hiked their prices twice in the last couple of years. This has a severe impact on the profit margins of companies like AMD & NVIDIA. This severely impacts their business esp. their lower & mid range products where the margins are already low!mode_13h - Monday, July 4, 2022 - link
It just means AMD/Nvidia have to pass on the price increases downstream. And yes, some lower-end products might even be unprofitable for them to make.Again, I feel like where TSMC/Samsung are really hurting AMD/Nvidia isn't so much pricing as just limited production capacity.
mode_13h - Monday, July 4, 2022 - link
> intel should ... simply use tsmc/samsung foundry for high margin products, i.e. cpu and server gpu.Weren't they rumored to have bought up TSMC N3E capacity for a future Xeon CPU?
The bigger issue is going to be volume. There's no way Intel can substitute its current production volume with TSMC/Samsung. AMD is currently supply-limited to just about 10% of the server market share, with Intel owning most of the rest.
Morawka - Tuesday, August 16, 2022 - link
Does TSMC use Cobalt or copper for their first few layers? Samsung? It would be interesting to know how each fab unit approached the same problem.