Thanks for this! I feel like we've been in this "megahertz myth" world, so focused on channel width as a placeholder for a generation of process technology. Current fab processes have way more parameters than planar FET designs. So it's great to see some illustrations of what we might expect next.
Samsung 14lpp -> 10lpe -> 7lpp -> 3gae is 0.7x0.5x0.5, or 17.5% power. Transistor density is roughly equivalent to TSMC n5 (albeit slight less dense). TSMC 16ff -> n7 -> n5 -> n3 is 0.4x.7x.7 or 19.6% power. TSMC n3 is about 1.7x density of n5. 16ff is more power efficient than 14lpp (from comparing comparable products I get 0.76x power) which would result in n3 consuming 15% less power than 3gae. TSMC has historically delivered better performance (higher frequencies) and yields on their nodes. I would expect that TSMC would have a significantly denser node that is moderately more power efficient better in performance. If Samsung nails GAAFETs, then they may have comparable or better yields, especially since TSMC is running into problems with their n3 node. However, Samsung has not delivered a ‘good’ FinFET node, so I doubt they’d do well on the even more complex GAAFETs.
It may not necessarily be clock speed. It could also be a 30% increase in the number of execution units within the same die area and power budget. For example, 30% more cores in the CPU at the same clock speed.
I would like to think that would fall under the "area reduction" metric rather than the "performance" metric, at the very least when the figures are from the fab rather than circuit designers.
Gate oxide scaling has been stalled for a LONG time (since ~22nm). The slide notes that their solution has been validated for finFETs too, so this should bring improvements to 'traditional' processes also.
The industry has been on Hi-K dielectrics for a while now & traditional SiO2 or SiON gate materials are no longer used in nm technologies (22nm & below).
Hi-K allows for physically thicker dielectric layers that have low gate leakage characteristics (tunneling etc) whilst having the equivalent electrical gate function of a much thinner gate dielectric (if had been built in traditional oxide).
So gates haven't been "oxide" for a while now. It's been a compound oxide plus Hi-K materials. With the Hi-K materials (AFAIK - Hafnium or Molybdenum compounds or other rare-earth metal combinations) getting tweaked every generation or so to slightly improve their capabilities.
FinFET gate lengths are the ones that have been slow to scale - only gradually decreasing from 28nm thru 18nm or so across 5 or 6 process generations (28, 22, 16, 12, 10, 7), with a lot of the performance gains coming from fin height instead, which effectively increases the FinFET width per unit area & hence improves drive strength.
When last I heard, Samsung was having major problems with yield[1]. Has the situation improved, or is this just an article to distract us from Samsung's problems?
I'm always a bit apprehensive that reliability will be one of the casualties of the semiconductor process race. I tend to keep stuff for a long time, and I'd hate it if we reached a point where CPUs were simply "used up" after 5 years of average use (or maybe 1.5 years of intense use).
Not only is it bad for the environment, but it could be catastrophic, in the case of a supply chain disruption even bigger than what we've experienced.
I think we're going to see an acceleration in the number of places where durability matters more than performance, and increasing catering to that need will follow. We'll have two tiers of computer equipment 'fast' and 'durable' and fast will be one or two orders of magnitude faster but will burn out in timescales that will require MTBF labeling, and durable will last at least decades.
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watersb - Thursday, May 12, 2022 - link
Thanks for this! I feel like we've been in this "megahertz myth" world, so focused on channel width as a placeholder for a generation of process technology. Current fab processes have way more parameters than planar FET designs. So it's great to see some illustrations of what we might expect next.lemurbutton - Friday, May 13, 2022 - link
Is Samsung's 3nm expected to be competitive with TSMC's 3nm?ishould - Friday, May 13, 2022 - link
I'd expect it to be very competitive. They might actually be close to taking the crown if they get lucky and Intel/TSMC timelines slipballsystemlord - Friday, May 13, 2022 - link
Actually, I've heard the exact opposite. Even if you're correct, if yield doesn't improve, performance will not matter.IntelUser2000 - Monday, May 16, 2022 - link
Semianalysis doesn't think it'll be either. They significantly downgraded their gains in all three metrics.Also when the yields are bad enough, it'll impact performance of real world devices. Look how they had to reduce the clocks of the RDNA2 mobile part.
ballsystemlord - Friday, May 13, 2022 - link
I mean yield with respect to their current 5nm offering.Otritus - Saturday, May 14, 2022 - link
Samsung 14lpp -> 10lpe -> 7lpp -> 3gae is 0.7x0.5x0.5, or 17.5% power. Transistor density is roughly equivalent to TSMC n5 (albeit slight less dense). TSMC 16ff -> n7 -> n5 -> n3 is 0.4x.7x.7 or 19.6% power. TSMC n3 is about 1.7x density of n5. 16ff is more power efficient than 14lpp (from comparing comparable products I get 0.76x power) which would result in n3 consuming 15% less power than 3gae. TSMC has historically delivered better performance (higher frequencies) and yields on their nodes. I would expect that TSMC would have a significantly denser node that is moderately more power efficient better in performance. If Samsung nails GAAFETs, then they may have comparable or better yields, especially since TSMC is running into problems with their n3 node. However, Samsung has not delivered a ‘good’ FinFET node, so I doubt they’d do well on the even more complex GAAFETs.Tigran - Friday, May 13, 2022 - link
>>30% performance increase<< Is it about clock rate? If yes - why do they always call it "performance"?vlad42 - Friday, May 13, 2022 - link
It may not necessarily be clock speed. It could also be a 30% increase in the number of execution units within the same die area and power budget. For example, 30% more cores in the CPU at the same clock speed.Dolda2000 - Tuesday, May 17, 2022 - link
I would like to think that would fall under the "area reduction" metric rather than the "performance" metric, at the very least when the figures are from the fab rather than circuit designers.edzieba - Friday, May 13, 2022 - link
Gate oxide scaling has been stalled for a LONG time (since ~22nm). The slide notes that their solution has been validated for finFETs too, so this should bring improvements to 'traditional' processes also.TimSyd - Friday, May 13, 2022 - link
The industry has been on Hi-K dielectrics for a while now & traditional SiO2 or SiON gate materials are no longer used in nm technologies (22nm & below).Hi-K allows for physically thicker dielectric layers that have low gate leakage characteristics (tunneling etc) whilst having the equivalent electrical gate function of a much thinner gate dielectric (if had been built in traditional oxide).
So gates haven't been "oxide" for a while now. It's been a compound oxide plus Hi-K materials. With the Hi-K materials (AFAIK - Hafnium or Molybdenum compounds or other rare-earth metal combinations) getting tweaked every generation or so to slightly improve their capabilities.
FinFET gate lengths are the ones that have been slow to scale - only gradually decreasing from 28nm thru 18nm or so across 5 or 6 process generations (28, 22, 16, 12, 10, 7), with a lot of the performance gains coming from fin height instead, which effectively increases the FinFET width per unit area & hence improves drive strength.
DanNeely - Friday, May 13, 2022 - link
7nm to 3nm is several full nodes worth of nominal scaling, 45% area reduction is only 1 node worth.ballsystemlord - Friday, May 13, 2022 - link
When last I heard, Samsung was having major problems with yield[1]. Has the situation improved, or is this just an article to distract us from Samsung's problems?https://www.phonearena.com/news/samsung-execs-accu...
mode_13h - Saturday, May 14, 2022 - link
I'm always a bit apprehensive that reliability will be one of the casualties of the semiconductor process race. I tend to keep stuff for a long time, and I'd hate it if we reached a point where CPUs were simply "used up" after 5 years of average use (or maybe 1.5 years of intense use).Not only is it bad for the environment, but it could be catastrophic, in the case of a supply chain disruption even bigger than what we've experienced.
DougMcC - Saturday, May 14, 2022 - link
I think we're going to see an acceleration in the number of places where durability matters more than performance, and increasing catering to that need will follow. We'll have two tiers of computer equipment 'fast' and 'durable' and fast will be one or two orders of magnitude faster but will burn out in timescales that will require MTBF labeling, and durable will last at least decades.ballsystemlord - Sunday, May 15, 2022 - link
When you say "durable" you mean durable like the Tuf series of MBs? ;)