The emotional tone behind this (as opposed to the actual facts) rides an awful lot on the meaning of "full nodes" and how they are labelled. But this is more or less meaningless, as has been stated many many times before!
Back in the old days, the equating of "node=sqrt(2) linear shrink" was obvious, but it's been so many years since that was true.
But NOW node seems to mean more something like "substantial change in some aspect of the tech", whether that is adoption of Fins, adoption of EUV, adoption of EUV double-patterning, adoption of GAA, or adoption of back-side power delivery. In between those large tech changes, we have on-going lithography shrinks of say .9 or so (rather than the .7 of old-school sqrt(2) shrinking) every so often.
This to me does not suggest any sort of doom or even slowdown; it just suggests that things are different. There's more of an emphasis of underlying changes which cause substantial disruption to the fab, less of an emphasis on the on-going small but "routine" improvements that don't require huge fab disruption.
This was probably an inevitable BUSINESS consequence (not TECH consequence). Now that a "real" node change equals a seriously disruptive (and seriously expensive) change in the fab, it becomes not just an engineering issue, it has to be something discussed by finance folks, something negotiated with the huge suppliers, something very very public. Meanwhile the old-style "routine" improvements can be relegated to a less public role because they don't require the same pre-allocation of billions and billions of dollars.
As a side issue, this same analysis points out the ongoing idiocy of Intel's boasting of their i2 and 18A processes. What Intel (or their fanbase don't get) is that the real work of a process now IS that billions and billions of dollars spend, and the outfitting of the next round of fabs. It's NOT the work in the labs, that happens years earlier. Intel can build the fab shells, cool; but they do not have special access to the ASML and LAM equipment required to populate those fabs. So, come 2024 (or 2022H2 or whenever 18A is now supposed to have moved up to) what Intel will have is a lab that can produce some nice test wafers, not a production line capable of supplying Apple or i5-level demands.
the slowdown is in TSMC's cadence. TSMC has a history of 2~ year cadence on their "new" nodes, which is highly desirable since it gives designers predictable build-refresh-build cycles. it has nothing to do with actual densities and performance targets.
Oh, it’s definitely a slowdown. All of the small advancements in between the major node reductions are to give clients something to help them sell more chips. I’m not against that, but it indicates that TSMC, and others, are relying on these between node advances to keep things going, somewhat, so that when a full node reduction comes it’s not as spectacular as it once was.
I did read your comment, and like I said you didn't read the article as it was talking about the update cadence, not some arbitrary performance metric.
a 40% power savings a year or two later than usual doesn't exactly help designers when they have to release products every year. that's the slowdown the article is talking about, not the performance figures.
It would appear that you have done zero reading regarding Intel's capacity and EUV installations. They've been installing EUV machines in the D1 series of fabs for at least the last couple of years and they're still installing more. Intel is also getting the first High-NA machines from ASML which won't be ready until late 2024/early 2025.
The news regarding TSMC is a simple truth that they're slowing down their own cadence of full node releases. This doesn't indicate they're in trouble or that anything is going wrong. They need to give their customers the most concrete information possible and being conservative is very smart. I suspect that TSMC, much like all the leading fabs, is beholden to the rate at which ASML can manufacture EUV/DUV machines.
Nice post. Lots of folks have trouble understanding that Intel is operating in rapid recovery mode, having let their own FABs languish for a decade--waiting on AMD to leapfrog them, again, before attempting to compete, I suppose. Thing is, TSMC has been in heavy development mode along with AMD, as well, which underscores the huge job Intel has ahead of it. There's only so much you can do with marketing, I guess Intel is learning. But when marketing is all you have...well...;) (I know it's not "all" Intel has, but sometimes it is hard to resist, especially when we have anachronisms like Gelsinger announcing he feels relieved "now that he's put AMD in the rear view mirror with Alder Lake"...Who was it who said so aptly..."That would be true only if Intel is moving backwards"...?...;) Intel's time with Apple has definitely rubbed off, imo.
Yea, “rear mirror” is hardly the case when your CPU is still 5% slower in total (gaming isn’t relevant for 16 core CPU or at least not their major field), while being auto overclocked and extremely inefficient. Rear mirror isn’t either when you have to give up AVX 512 support and regress in order to do it.
That said, Gelsinger is a typical ridicilous Intel guy. His other ridiculous claim was that he will try to win Apple back, which of course is even less likelier to happen since Apple is pretty great in designing their own CPUs and has no interest in giving up control again.
AMD and Intel can exceed Apple’s performance if they continue to throw more power at it. We see that with their latest designs. Slightly faster in some contexts, but when including GPUs, a good four to five times as much power.
I re ember when both AMD and Intel stated that they would t exceed 125 watts. Well, that’s well out the door.
I do suspect ASML will ramp up production by a very large amount to accommodate Intel. That is a ton of business ASML wants. So while I agree on every point I am a bit more optimistic on Intel getting machines from ASML over the next couple years.
Can't disagree. But I think that anyone that transitions very well to a GAA architecture will win (at least) in the mobile space as leakage becomes bigger factor with shrinks. If there is a standout in the GAA implementation then client design wins will support FAB build out investments. May be a longer cycle given equipment complexity and delivery time. But great FinFET implementations have a 12 year+ impact on transistor leadership.
I think GAA is such a fundamental change, and money & capacity will follow the best implementation(s)
Table 2 has a row that reads "Risc Production" This is obviously when a foundry starts producing RISC chips on a new node. Eventually the production process on said node graduates and yields improve to the extent of being able to produce larger CISC chips :-)
They aren't dedicating enough resources for MRAM because even the medium-term ROI is very unfavourable.
I'd also really like to see more research into VC-MRAM and see more foundries bringing SOT-MRAM to newer nodes.
But the commoditization of memory means that the industry has become way too conservative, and technologies with solid foundations have to be thrown under the bus in favour of investing billions into slowly optimizing the costs and flaws out of the technologies that are making them money right now.
MRAM will still eventually break through simply because the low-power market needs it, but it might be decades before it's optimized and scaled enough to see it replacing SRAM in things like L3 caches, which is one of the promising applications for MRAM as predicted by IBM.
Amazing stuff. Aside from specific cutting edge stuff (GPUs, CPUs, mobile SoCs, niche ASICs), its not a big deal if the dev time increases to say 5 or 7 years. A lot of stuff is just fine on older nodes, and these "older" nodes are still ridiculously advanced, like 7/8/10/13nm tech that sites consider "old".
The amazing stuff of the next 30 years is going to come from 3D integrated circuits, not the next few node shrinks and transistor types (gate-all-around and others). Although those will also be helpful.
Hoping to see some nice 7nm budget chips once high-end products move to 5nm and later.
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name99 - Friday, April 22, 2022 - link
The emotional tone behind this (as opposed to the actual facts) rides an awful lot on the meaning of "full nodes" and how they are labelled. But this is more or less meaningless, as has been stated many many times before!Back in the old days, the equating of "node=sqrt(2) linear shrink" was obvious, but it's been so many years since that was true.
But NOW node seems to mean more something like "substantial change in some aspect of the tech", whether that is adoption of Fins, adoption of EUV, adoption of EUV double-patterning, adoption of GAA, or adoption of back-side power delivery.
In between those large tech changes, we have on-going lithography shrinks of say .9 or so (rather than the .7 of old-school sqrt(2) shrinking) every so often.
This to me does not suggest any sort of doom or even slowdown; it just suggests that things are different. There's more of an emphasis of underlying changes which cause substantial disruption to the fab, less of an emphasis on the on-going small but "routine" improvements that don't require huge fab disruption.
This was probably an inevitable BUSINESS consequence (not TECH consequence). Now that a "real" node change equals a seriously disruptive (and seriously expensive) change in the fab, it becomes not just an engineering issue, it has to be something discussed by finance folks, something negotiated with the huge suppliers, something very very public. Meanwhile the old-style "routine" improvements can be relegated to a less public role because they don't require the same pre-allocation of billions and billions of dollars.
As a side issue, this same analysis points out the ongoing idiocy of Intel's boasting of their i2 and 18A processes. What Intel (or their fanbase don't get) is that the real work of a process now IS that billions and billions of dollars spend, and the outfitting of the next round of fabs. It's NOT the work in the labs, that happens years earlier.
Intel can build the fab shells, cool; but they do not have special access to the ASML and LAM equipment required to populate those fabs. So, come 2024 (or 2022H2 or whenever 18A is now supposed to have moved up to) what Intel will have is a lab that can produce some nice test wafers, not a production line capable of supplying Apple or i5-level demands.
NICOXIS - Friday, April 22, 2022 - link
Intel fought so hard for 10nm, they have to enjoy it at least a decade :Dwhatthe123 - Friday, April 22, 2022 - link
the slowdown is in TSMC's cadence. TSMC has a history of 2~ year cadence on their "new" nodes, which is highly desirable since it gives designers predictable build-refresh-build cycles. it has nothing to do with actual densities and performance targets.at least read the article.
name99 - Sunday, April 24, 2022 - link
At least read the fscking comment!melgross - Monday, April 25, 2022 - link
Oh, it’s definitely a slowdown. All of the small advancements in between the major node reductions are to give clients something to help them sell more chips. I’m not against that, but it indicates that TSMC, and others, are relying on these between node advances to keep things going, somewhat, so that when a full node reduction comes it’s not as spectacular as it once was.Nevertheless, “Moore’s Law” is out the window.
whatthe123 - Monday, April 25, 2022 - link
I did read your comment, and like I said you didn't read the article as it was talking about the update cadence, not some arbitrary performance metric.a 40% power savings a year or two later than usual doesn't exactly help designers when they have to release products every year. that's the slowdown the article is talking about, not the performance figures.
thestryker - Friday, April 22, 2022 - link
It would appear that you have done zero reading regarding Intel's capacity and EUV installations. They've been installing EUV machines in the D1 series of fabs for at least the last couple of years and they're still installing more. Intel is also getting the first High-NA machines from ASML which won't be ready until late 2024/early 2025.The news regarding TSMC is a simple truth that they're slowing down their own cadence of full node releases. This doesn't indicate they're in trouble or that anything is going wrong. They need to give their customers the most concrete information possible and being conservative is very smart. I suspect that TSMC, much like all the leading fabs, is beholden to the rate at which ASML can manufacture EUV/DUV machines.
WaltC - Saturday, April 23, 2022 - link
Nice post. Lots of folks have trouble understanding that Intel is operating in rapid recovery mode, having let their own FABs languish for a decade--waiting on AMD to leapfrog them, again, before attempting to compete, I suppose. Thing is, TSMC has been in heavy development mode along with AMD, as well, which underscores the huge job Intel has ahead of it. There's only so much you can do with marketing, I guess Intel is learning. But when marketing is all you have...well...;) (I know it's not "all" Intel has, but sometimes it is hard to resist, especially when we have anachronisms like Gelsinger announcing he feels relieved "now that he's put AMD in the rear view mirror with Alder Lake"...Who was it who said so aptly..."That would be true only if Intel is moving backwards"...?...;) Intel's time with Apple has definitely rubbed off, imo.Khanan - Sunday, April 24, 2022 - link
Yea, “rear mirror” is hardly the case when your CPU is still 5% slower in total (gaming isn’t relevant for 16 core CPU or at least not their major field), while being auto overclocked and extremely inefficient. Rear mirror isn’t either when you have to give up AVX 512 support and regress in order to do it.That said, Gelsinger is a typical ridicilous Intel guy. His other ridiculous claim was that he will try to win Apple back, which of course is even less likelier to happen since Apple is pretty great in designing their own CPUs and has no interest in giving up control again.
melgross - Monday, April 25, 2022 - link
AMD and Intel can exceed Apple’s performance if they continue to throw more power at it. We see that with their latest designs. Slightly faster in some contexts, but when including GPUs, a good four to five times as much power.I re ember when both AMD and Intel stated that they would t exceed 125 watts. Well, that’s well out the door.
Kamen Rider Blade - Tuesday, April 26, 2022 - link
Apple doesn't care about high power consumption, they care about power efficiency and low power.So throwing wattage at the problem isn't the solution that Apple wants.
And AMD is closer than Intel on the efficiency curve and lower power to where Apple wants things.
FreckledTrout - Friday, April 29, 2022 - link
I do suspect ASML will ramp up production by a very large amount to accommodate Intel. That is a ton of business ASML wants. So while I agree on every point I am a bit more optimistic on Intel getting machines from ASML over the next couple years.jayfang - Wednesday, May 11, 2022 - link
Can't disagree. But I think that anyone that transitions very well to a GAA architecture will win (at least) in the mobile space as leakage becomes bigger factor with shrinks. If there is a standout in the GAA implementation then client design wins will support FAB build out investments. May be a longer cycle given equipment complexity and delivery time. But great FinFET implementations have a 12 year+ impact on transistor leadership.I think GAA is such a fundamental change, and money & capacity will follow the best implementation(s)
SarahKerrigan - Friday, April 22, 2022 - link
"Risc Production" should probably be "Risk Production" (though the risk production stage will likely include RISC processors!)Ryan Smith - Friday, April 22, 2022 - link
Thanks!My spellchecker has been taught that "risc" is a valid word. Which is great right up until the point where someone uses it in place of "risk".
Arnulf - Friday, April 22, 2022 - link
Table 2 has a row that reads "Risc Production" This is obviously when a foundry starts producing RISC chips on a new node. Eventually the production process on said node graduates and yields improve to the extent of being able to produce larger CISC chips :-)Diogene7 - Friday, April 22, 2022 - link
I am wondering if there is any chance to have news about TSMC, Samsung,… advancements of High Volume Manufacturing (HVM) of MRAM ?I recall that TSMC was planning to get some new MRAM improvements into risk production toward 2022 / 2023 ?
brucethemoose - Friday, April 22, 2022 - link
Who wants MRAM in high volume? I thought its density wasn't that great yet.Wereweeb - Friday, April 22, 2022 - link
They aren't dedicating enough resources for MRAM because even the medium-term ROI is very unfavourable.I'd also really like to see more research into VC-MRAM and see more foundries bringing SOT-MRAM to newer nodes.
But the commoditization of memory means that the industry has become way too conservative, and technologies with solid foundations have to be thrown under the bus in favour of investing billions into slowly optimizing the costs and flaws out of the technologies that are making them money right now.
MRAM will still eventually break through simply because the low-power market needs it, but it might be decades before it's optimized and scaled enough to see it replacing SRAM in things like L3 caches, which is one of the promising applications for MRAM as predicted by IBM.
Ah, the beauty of flawless market economics
webdoctors - Saturday, April 23, 2022 - link
Amazing stuff. Aside from specific cutting edge stuff (GPUs, CPUs, mobile SoCs, niche ASICs), its not a big deal if the dev time increases to say 5 or 7 years. A lot of stuff is just fine on older nodes, and these "older" nodes are still ridiculously advanced, like 7/8/10/13nm tech that sites consider "old".nandnandnand - Sunday, April 24, 2022 - link
The amazing stuff of the next 30 years is going to come from 3D integrated circuits, not the next few node shrinks and transistor types (gate-all-around and others). Although those will also be helpful.Hoping to see some nice 7nm budget chips once high-end products move to 5nm and later.