Something about Amazon's Graviton 3 and its use of Neoverse V1 cores deserves a mention.
...and speaking of ARM and efficient cores, the absence of a successor to the Cortex-A35 springs to mind. In fact, given how the X-series cores seem to have demoted the A700-series to mid-tier, should the A510 really be seen as something more than the A35's de facto successor?
Pretty sure I already made the 5 tier joke in reply to you.
Yeah, who knows. I think phones could definitely add an A35 successor for standby alongside Cortex-X2, A710 and A510, but I don't remember seeing any recent SoCs that had any A35 cores anyway. Maybe they don't get reported on as much. I do see that the Snapdragon Wear 5100 uses 4x Cortex-A53 for some strange reason.
> Pretty sure I already made the 5 tier joke in reply to you.
Yeah, and it kinda reminds me of the way automobiles were adding ever more speeds to their transmissions, so that the engine could always operate near the optimal efficiency-point.
The most tiers of cores in a single SoC that seem justified would probably be 3. The top & mid tiers should handle latency-sensitive workloads, while the bottom tier is useful for background tasks and idle-mode operation.
I agree. But the efficiency and performance of the Cortex-A53 is pretty disappointing for today's standards. With the newer A55 and the A510 being not much better. The Cortex-A35 was pretty awesome in its hey-day as it offered a new 64bit-platform, high efficiency, for those low-power needs.
So I can actually see something like a miniaturised A510 on an 8nm, being a spiritual successor to the old 16nm A35 standing. What we really need is a much better "small core". Something that's OoO, small, and highly efficient. For instance, a Cortex-A73, updated for ARMv9 protocol, and miniaturised on 4nm for phones. Only then can Android devices begin competing properly against iOS devices. Since the lack of need to flip through both core types will save a lot of energy and latency times.
We also need a revolution on the large cores, since Apple's A13-P cores are still ahead of the latest X2 cores. I think we'll pass that threshold with the European X3 cores (second-gen ARMv9). I'd also add that the 4+4 design isn't that efficient, as the third and fourth large cores use up lots of power without being necessary contributing much computing. And we should skip the (1+3)+4 design too. We should just go with a 3+5 design instead, and either use three X3 cores if they're efficient enough, or use it's derivative (eg Cortex-A730) cores but with more cache and thermal headroom.
You start by saying you agree, but then you seem to argue for the opposite.
I think the lowest tier cores should be optimized for energy-efficiency, period. They only need to be fast enough and supplied in quantities big enough to complete most of the background processing in a reasonable amount of time. This is purely about battery life.
I'd speculate that Apple is only using 2-tiers because they lack bandwidth in their design team to do a 3rd tier.
I agree that the: A510 is the (spiritual) successor to the Cortex-A35, which was the successor to the Cortex-A7.
The original Cortex-A53 was great for its time in 2014, was quiet obsolete and lacklustre in 2017 or beyond. For all practical purposes, we didn't actually get a true successor. The A55 is a joke and so is the A510, if we are talking about using them as "small cores" in phones (excluding cheap budget/entry level).
We don't need more "speed tiers". Our software isn't advanced enough, and our use cases don't warrant it. It is far more ideal to reduce latency, and having a more simplified system. That's the route Apple takes, and they've been leading the market since the iPhone 5S in 2013. The Hypothetical SoC that I listed above is far better than your Hypothetical SoC with three or four different cpu types. For instance: (3+5) X1-A73.... versus.... (1+3+3+1) X1-A78-A55-A35 (3+5) A78-A73.... versus... (4+2+2) A78-A55-A35
> We don't need more "speed tiers". Our software isn't advanced enough, > and our use cases don't warrant it.
That's nonsense. The OS knows which app(s) is/are running in the foreground. That's enough to prioritize their threads (at least, when the screen is unlocked) to run on the faster cores.
> That's the route Apple takes
Just because apple went with 2 tiers doesn't make it the right thing to do, you know? They could have other reasons than what's technically best.
I know you wish ARM would just design Apple-grade cores and you think that would be good enough. I'm trying to think about the problem in the abstract, and beyond simply wishing that ARM was more like Apple.
> your Hypothetical SoC with three or four different cpu types.
WTF? I clearly said, in 2 different posts, that I thought 3 tier was ideal.
Well, it's not non-sense and you're wrong. There is latency when shuffling processes from one core or complex to another. Some Apps don't require much performance, but then you run it, and later they require it. Running Apps always on the fast cores is not the solution, and nor is the opposite. So what we have right now, is the scheduler usually goes into performance mode when you interact with the screen or start up an App. Then it understands which category it needs to go into. Then it moves the process into that complex. And after a minute, it might migrate that thread back into the large cores. This behaviour is very common in something like your Web Browser.
Why do you think the Helio X30 was such a flop?
Apple's philosophy is totally different. Remember these guys invented/popularised the Personal Computer. They have their own language, their own software, their own user interface, and their own hardware. And decades of experience there, but without the baggage of legacy code in iOS. So there's a big difference compared to Google.
I didn't state that ARM should just get Apple's cores. When you think about it, there's no magic in their cores. Just take the 16nm Cortex-A73, then miniaturise it in a 4nm node, modernise its feature-set without making it more complex, make it run from low-to-mid voltage, voila. Sure, it might use more power than Apple's E-cores AND it might run slower too. But it will be more inline with the current software requirements and performance demands of the main/small cores on a phone. And that translates to both a better experience than the current A53 cores, and overall better efficiency. And for the large cores, grab the Cortex-A78, add more cache and extra branch predictions, there you have an X1 core. Not as good as Apple's P-cores, but it is acceptable for its time.
Large X1 - Mini 73 (3+5) design, will run circles around the QSD 888's design of X1, A78, A55 (1+3+4) processor. It might not show it on the synthetic benchmarks, but in real-world use, it will be faster AND use less energy. And the idea of adding more "speed tiers" is just going to exasperate that.
" WTF? I clearly said, in 2 different posts, that I thought 3 tier was ideal. " sigh. Now I know you're discussing this in bad-faith. Since you can clearly read that I said THREE or four. I did clearly read your comments, and others. Case in point, you have not commented on the comparison I made: (3+5) A78-A73.... versus... (4+2+2) A78-A55-A35
> There is latency when shuffling processes from one core or complex to another.
Maybe a microsecond or so. As long as it's fairly infrequent, it's negligible.
What's costly, in terms of power, is to take a core out of sleep. And running background jobs means repeatedly doing exactly that. So, it's not only the energy used during execution that you need to think about. Therefore, background and I/O-limited threads should run on the smallest and most-efficient core possible.
> Some Apps don't require much performance, but then you run it, > and later they require it. Running Apps always on the fast cores is not the solution, > and nor is the opposite.
That's too simplistic, of course. It's more like this: when a thread is using its entire timeslice and it's part of a foreground app, then boost the clock speed of the core or move the thread to a more powerful core. If the thread is part of a backgrounded app or service, demote its priority, so that it'll tend to stay on the most efficient cores, even if it's compute-bound. Then, if it holds a resource blocked on by a higher-priority thread, give it the priority of the blocked thread.
Even that is a bit over-simplified, but the point is that this isn't an intractable or even a new problem. Boosting the priority of threads belonging to foreground apps is a technique that's been used for decades, on various operating systems.
> Why do you think the Helio X30 was such a flop?
I don't know anything about it, but a product can have a whole range of different issues that undermine it, such as thermal issues, inappropriate cache configuration, or even memory controller bugs that hamper performance.
> Apple's philosophy is totally different.
You don't actually know why they do what they do. To interpret their decisions without that knowledge is a bit like looking at chicken entrails. Nobody knows exactly what they mean, so they're completely open to interpretation.
> Remember these guys invented/popularised the Personal Computer.
No, they aren't. These are different people working for a company which has undergone 4+ decades of evolution. Different people; different company (effectively); very different product.
> They have their own language, their own software, their own user interface, > and their own hardware.
So does Microsoft. And Google, even.
> but without the baggage of legacy code in iOS.
Oh, I bet there is!
> I didn't state that ARM should just get Apple's cores.
But you want to blindly follow Apple's strategy. I'm arguing that 3-tier is better, and you haven't given a good argument why it's not (except that Apple doesn't do it).
> Now I know you're discussing this in bad-faith. > Since you can clearly read that I said THREE or four.
I never said four. That's not bad faith on *my* part. Don't make it sound like I'm saying something I'm not, and then we won't have a problem.
> Case in point, you have not commented on the comparison I made:
What do you want me to say? I'm not obligated to weigh in on a point I don't have data or the confidence to take a position on. If you want to talk about *specific* core configurations, that is a very data-driven argument, and also depends on cache + DRAM configuration.
All I'm saying is that I'd have probably 2 cores that are strictly optimized for energy-efficiency and nothing else.
As nandnandnand says, there aren't many SoC based on A35. ( and I did laugh loud on his 5 tier joke x) . Who knows maybe we will see 4- or 5-tiers.
Mediatek has tried to push A35 but SoC based on it weren't popular.
It's seems like A35 maked sense at 28nm node where A53 wasn't enough power efficient. On 10 nm and newer, battery impact on A35 and A53 should be very similar.
Mostly a case of diminishing returns, at such a small node size it's basically gotten to the point that the idle power of both is very similar, while peak performance for the task is higher at a similar/slightly better power efficiency.
That's why watches don't have the high performance cores, since it's more important that the battery lasts longer, people don't generally use it for e.g. a game where a high single performance core for orchestration would have a large impact.
I haven't been this concerned about stock CPU heat since the early days of Pentium/Athlon. My 5900x could never CPU boost on all cores to 4.5Ghz and usually back down to 4.1 because of thermal. That's inside a Fractal Design 7C case with Noctua d15 CPU cooler inside a cool room.
sounds like bad contact. AMD's IHS quality is all over the place. my 5900x stays around 4.5~4.6 with 75C~ temps. I don't think my cooler would be 15C superior to a D15 so it's probably not a cooler problem.
Try reapplying thermal paste and reseat, sounds like the cooler is not making proper contact, since that cooler and case should have no issue cooling it (unless you've messed with the fan profiles).
Also, I noticed that while you linked to the article, you didn't mention anything about Bergamo or its "Zen 4c" cores, which appear to be AMD's answer to Intel's Gracemont E-cores.
WOW was already developed for mac. Transition is easy. Overwatch was not. Apple too has to support game devs and their demands regarding API features and Apple does not care. Apple expects everyone to make games for Metal, ios compatible and other platforms might just not exist.
This is not as big a deal as you think. For big game studios with their own bespoke engines, the engines are written with platform abstraction in mind. So when a new platform appears, the engine team will just get to work. This is how it's been for more than 20 years.
And if you're using off-the-shelf engines like Unity or Unreal Engine, those already support the MacOS, iOS, ARM and Metal.
In short, there aren't any real technical limitations to developers getting their games onto Mac OS.
The real issue is that of publishing. I.e. is there any point?
Games have traditionally sold very poorly on Mac OS, so most publishers don't see the point of spending money on platform integration, QA, platform submission, etc... only to end up with about a hundred sales.
This is a ball that Apple needs to start rolling with acquisitions, 1st-party titles, exclusives if they are keen on entering the gaming market - but it doesn't look like they're that keen on it. Besides, iOS gaming is doing really well for them so there's no incentive.
This is not a very realistic opinion. Most large studies build their engines to support the major platforms only, which right now is Xbox Series, PlayStation 5 and Windows. It costs a lot of money to support additional platforms, because of all the platform-specific tuning. For off the shelf engines, it's less work provided the engine supports the platform. Not all off the shelf engines have great platform support, Unreal & Unity as two examples do, but many don't.
Mac OS is not a very popular gaming platform so it's not worth developers time to develop Mac ports based on the expected sales. Add the current total lack of discrete GPU hardware (or some sort of massive GPU-centric SoC like the ones the consoles use) and you have even less reason to release Mac versions of games.
And don't get me started on the fact that Mac OS doesn't support Vulkan, that's the stupidest thing Apple has done recently. Don't support the open standard and build an inferior proprietary standard so everyone has to rewrite their rendering engines. Apple is blatantly developer hostile, which is why in most cases companies have to pay Apple devs more, because no one wants that job.
Mobile gaming is already 59% of the market. I suspect Apple is more or less OK with the current situation... At some point the types of gamers who are most vocal on the internet need to accept that they're a minority species, just not very important in anyone's business calculations. Some car companies see value in playing with formula one and selling muscle cars; some don't -- that's just life when you have minority tastes.
The new M1 MacBooks, despite being able to run IOS Games (Mobile games, as referred in your article) don't have touchscreens, which severely their limit capability on said games. Thus, combined with the bad emulation performance, the M1-equipped laptops are really not that good for gaming, either mobile or classical.
Since this article is about PC chips then obviously the definition is PC gaming, which excludes mobile gaming. Also, if you must talk about mobile games on PCs, lots more people play mobile games on Chromebooks than they do on Macs. Why? For 3 reasons. 1. Few iOS developers have agreed to allow or support iOS games on macOS where all Android games are on ChromeOS. 2. They are only available on M1 Macs - which are a small minority of Macs in the wild - where Android games run on both x86 and ARM Chromebooks. 3. The biggest reason: ChromeOS supports touchscreens where macOS doesn't. And it gets better - or worse - when Android apps come to Windows 11 next year (with independent solutions provided by Google and Microsoft/Amazon) that will also crush mobile gaming on macOS.
So yeah, macOS - due to its under 10% market share (now #3 behind Windows and ChromeOS) and platform limitations imposed by Apple, hasn't been a factor in gaming since the early 90s Sierra Online days and will never be again.
mobile is high revenue from a lower population of users. top spenders or "whales" spend outspend normal users exponentially, so the revenue to user count isn't all that favorable for manufacturers. You can see the results in earnings reports from companies with both gambling games and traditional mobile games. Their traditional mobile games go absolutely nowhere while their microtransaction revenue is through the roof.
Definitely mobile gaming! Young people own gaming phones, not gaming computers any more. The move to mobile gaming is just starting to move faster! I am old fashion gamer with gaming computer, but I also know that I am a fossil!
It's not a move it's a different market growing on it's own, it's not hordes of PC gamers "moving", I'm sure some older PC gamers are also playing some mobile games but I'm also sure that very few quits playing games on PC to only play mobile games.
It's two very different things, IMHO most of the mobile gaming industry are more like casino gaming than PC gaming, but that's just my opinion.
AMD has been emphasizing efficient cores since Zen2 2.5 years ago--the most efficient core gets the single thread (usually.) This can change, too, based on the software that is being run, etc. For multicore, you want all cores maxed out, of course, also done by AMD since Zen2 debuted.
It's possible that AMD could have used the above strategy in perpetuity without adopting a heterogeneous design to counter Intel's small cores. By the time we get down to 2nm or so, it would be possible to put 16-32 big cores in the die area where 8 cores used to be, more than enough for most consumers. Then just have some of them favored to run at higher clock speeds as needed.
But now we have confirmation of Zen 4c which supports the rumor of 8x Zen 5 + 16x Zen 4c processors. AMD can shave off some clock speed, cache, and features (apparently not hyperthreading), fit more cores in a smaller area, and hopefully improve both perf/watt and perf/area. Coming in much later than Alder Lake, they can benefit from a couple years of OS/software/game optimizations targeting 8 big cores and 8-16+ slower small cores.
There's x86's ultimate future for most users. 8-16 big cores, and dozens to hundreds of smaller cores. Alongside iGPU, machine learning, and other accelerators.
> By the time we get down to 2nm or so, it would be possible to put 16-32 big > cores in the die area where 8 cores used to be
A while ago, I recall reading about a point where silicon manufacturing can keep getting the features smaller, but the density of gate activity has to be lower to combat leakage, or something like that. If it turns out to be true, then big "small" cores could be a good approach.
> There's x86's ultimate future ... 8-16 big cores, and dozens to hundreds of smaller cores.
We need some software innovations to make use of so many little cores. Innovation in thread synchronization, communication, scheduling, and management. It would have to span all the way from the silicon to the OS and userland threading APIs. All solvable problems, but I'm not aware of a lot of movement in most of these areas.
Well if anything is going to spur that movement, it should be Alder Lake and Raptor Lake. Raptor Lake i9 in particular, that will have 16 efficiency cores which is a lot to leave on the table. Heterogeneous AMD could launch over a year after Raptor Lake.
It needs a concerted industry push, whereas you're describing a "build it and they will come" approach. We already have 256-thread CPUs and even *that* didn't lure software parties to do the necessary work.
Intel contributed TBB, which was a big help in app multithreading. However, it's not enough.
When a process wants to spin up worker threads, this is something that should be managed by the kernel. That keeps the CPU from getting swamped with too many worker threads fighting each other, it lets the kernel dynamically apportion them, and it also enables the kernel to schedule them to run as a group.
Google has been working on some threading improvements, but their progress seems glacial.
No, it means they are not targeting performance anymore, rather they are targeting power efficiency. Tbh, the statement is a bit iffy, most of the power efficiency is due to having hit the limit of silicon at the node size, so upping power etc. will yield minimal performance gains, so rather make it more efficient in power usage, so can then up the power envelope again, both increasing performance.
I believe they're talking about the fact that Intel holds the CPU performance crown over AMD right now, with the release of Alder Lake. AMD was the winner when Zen 3 was launched, and stayed the winner against Intel 11th gen (which was a joke tbf). Now Intel's recently launched 12th gen is generally superior to Zen 3 and also offers a big improvement over their lackluster 11th gen parts.
British humor? 10-core Comet Lake processor, built on the Skylake++++ platform, that Intel created 'because its Core i9-11900K was too high a frequency to bin enough hardware to provide the number of units demanded by the ecosystem'". Demanded by the ecosystem? Before or after Rocket initial application performance reports. Intel could have spent more silicon area on the part to overcome some performance limits. Ultimately Rocket is an AVX 512 developer's appliance if only Intel had positioned as such would have caused far less conundrum. W 1390 sells albeit in tiny volume v Core while Core 11th sits on the shelf.
"but in Intel’s recent financial calls, the demand for the high-end 40 core parts wasn’t really there, with customers preferring to stay around the 28-core. There are suggestions that this might be because Intel’s yields on the 40-core are low, however it will be interesting to see how strong Intel will suggest its 2022 platform, 4th Gen Sapphire Rapids, as a direct replacement to those sticking on 1st/2nd gen hardware."
Astute observation [how fast] Sapphire Rapids movement into = / > 32 core market? 40 Core Ice represents 3% of Xeon Ice lake full run volume and adding 38C 6%. Yield, hard to say, Ice is an intermediate technology in relation what came before and what will come after. Fact is AMD purposely focuses Epyc supply at 32C and above equals 48% of all Milan volume over the full run. Designed to keep Intel out of hyperscale volume wise, albeit, AMD total Milan volume in q3 2021 was 17% of Intel in quarter production.
On the Intel ecosystem stuck at 28 cores its applications driven and primarily by enterprise. 28C is a sweet spot on incremental upgrade. Across the Xeon Scalable platform market as a whole the primary core grades being replaced on channel data are 14C and 20C. Channel is supplying Skylake and Cascade 24 through 26C. Then the question is what's happening greater than 26C? On that question whether wait and see and who's platform; Intel or AMD. AMD hyperscale is an adequately evolving niche stronghold on AMD supply constraint. The key question is which way the enterprise market will lean. mb
Astute post Mike. Few people here that are not fanboys of something.
Myself, being involved in enterprise procuring, let me chime in my $0.02
Enterprise looks at the cost of the new platform plus performance. Power costs are not that important.
If AMD provides very competitive pricing and the particular software runs well, they will get more market share. Enterprise procurers tend to be less cutting edge and more conservative than their hyperscale counterparts since they protect their own employment first and then the companies best interests :)
You know what is a valid question? Give that AMD does have some supply constraints, do they really want to get to the enterprise now or focus more on solidifying their hyperscaler dominance?
If I was running the biz, I would throw the kitchen sink to get so deep in the hyperscalers that INTC would have way too much difficulty to unseat me in the future. Looking at how Lisa prioritizes the production so far, I am guessing she is in agreement with my thinking :)
Regarding your first point, I think it was a typo on Ian's part, and he meant to refer to the 10900K, not the 11900K. At the time of the article for the 10850K in question, Rocket Lake hadn't even been released yet.
I know that it would be a nightmare to get it right, but a BIOS and main board that could accept both DDR4 and DDR5 RAM (not mixed on the same board) would help with AL acceptance. Many of us have a pair of DDR4 modules from current builds, and if I could use those while I wait for DDR5 prices to come down to planet Earth, I might upgrade. Just a thought. And yes, I know that having 4 or 6 slots of mixed standards is a headache in the making, but still, might be worthwhile.
Yeah, honestly, there's not much reason to populate the four DIMM slots that come in most ATX motherboards. One can easily have 128GB of RAM by using 2x64GB DIMMs. For 99% of users that's already an obscene amount of RAM.
Four DIMMs are more useful if you want to build a dual-channel system and later upgrade the RAM amount without waste.
2xDDR4 and 2xDDR5 slots on the same motherboard would increase it's useful life for those willing to buy one.
Because it would add quite a bit of cost in terms of testing and support, there also isn't much point as performance difference between DDR4 and 5 is minimal, so the only reason right now for 5 is larger DIMMs, whereby having 4 DDR4 DIMMs would satisfy near all use-cases so why make 2 of them 5?.
Depending on how much cost it would add to the board, you might not even be much better off than if you started with an entry-level DDR4 board and later upgraded to a DDR5 board, if/when you wanted to switch.
See the moves from SD to DDR, DDR to DDR2, DDR2 to DDR3, and DDR3 to DDR4. Every single one of these generations had combo boards to help adoption.
DDR5 isnt magic, it has the same issue, and surpise surprise intel decided to disallow it this time and DDR5 acceptance is slow compared to dDR4. Whoda thunk it?
I'll try to find the manual, but the case and parts are still in my room, where it's become a makeshift bookstand. In all likelihood, the SIMMs and DIMM couldn't be used at the same; and I never did get the DIMM working, because I tried 100 MHz SDRAM but the bus was 66 MHz. I believe it was the i437 chipset. This is almost exactly what it looked like except that it was green:
A few months ago there was an article here that said al can support both on the same mobo but intel won't allow it. Maybe intel will change their mind now seeing how asus is developing a ddr4 to ddr5 card.
Confused. You can throttle individual cores of the same type and be effcient. Or you can create complexity with 2 types of cores - one regular and one efficient. Is this an Intel die size issue going from 14nm to something smaller? Something has happened with Intel and die size?
Gracemont is not just efficient, it's also physically much smaller than Zen cores. The idea being that CPUs in the near future will be a few "high performance cores", and then dozens of small, efficient cores, various workload and AI accelerators, a beefy iGPU, etc.
Having an architecture that has a single core performance of "good enough" while being ridiculously small and power efficient allows Intel to stick with a few power hungry cores and then tacking on a boatload of small cores.
AMD will eventually shift to multiple core types as well, just like every other CPU manufacturer has.
Th eissue here is that a downclocked P core can easily outperform the E core while also drawing less power. The E core has failed at its primary task, that being more efficient.
> downclocked P core can easily outperform the E core while also drawing less power.
Source? Intel's marketing materials for Lakefield did show a cross-over point, beyond which Tremont cores @ max clock speed were less efficient than Sunny Cove cores. So, it's conceivable that's still true of Gracemont and Golden Cove.
However, what you're forgetting about (at least for desktop applications) is perf/area which effectively means perf/$. And there, we know Gracemont offers about 2x the perf/area of Golden Cove. So, it turns out that for the same area as an 8+8 ALD die, you could only have a 10+0 die that would have lower all-thread performance than the 8+8 configuration. Indeed, the benchmarks confirm this, although results are lower than the 12+0 -equivalence predicted by linear scaling.
Thanks for the suggestions. The cooler and paste seem fine. The 5900X is sharing the case with RTX3090 and there is too much heat build up during sustained stress. At stock the 5900X throttles back to all core 4ghz almost immediately. I under volt both the CPU and GPU and could hit 4.4Ghz all cores for a few minutes but eventually the RTX3090 will add to the heat and the 5900X will throttle back down to 4.1ghz. The RTX3090 on the other hand always hits above its advertised speed and could sustain the clock without suffering from throttle. It's just not right AMD advertises the 5900X using words like its "maximum" boost is 4.8Ghz when the CPU is so sensitive to heat at stock. I could add more fans to exhaust the case of heat but I shouldn't need to in order to just to hit the "stock" boost is what I am saying.
Rather than add more exhaust fans, do you have room to add any more intake fans? Years ago, I remember seeing some claim from a case manufacturer that positive-pressure not only gave you better dust filtration (if your case even *has* dust filters, that is), but also resulted in better air circulation and therefore lower temps.
the 5900x i have with the NH-D15 cooler under load is 66c and, according to cpuz is running @ 4.5 and ryzen master says all core @ 4.3-4.4. maybe you didnt lucky with the silicon lottery ?
After under volt, idle temp is 45c and regular tasks rarely went above 65c. I could run all cores @ 4.5Ghz at ~85-87c stressing only the CPU drawing but 125W in HandBrake. However, once the 3090 is engaged which is needed for all my heavy load tasks, 5900x will hit the 90c throttle and could sustain only 4.1Ghz. This is after under volt, at stock the 5900x will hit 90c right away and throttle back to 4.1Ghz even with 3090 at idle.
This is my point. "Stock speed" used to be the floor but now is actually more a ceiling with current gen of AMD. Nvidia stock clock is still the floor with my 3090 as my GPU boosts way above its stock clock. I don't know what it's like for Intel.
The lack of side fans on modern cases is becoming a major issue wit the power draw of modern hardware. Take an old HAF case, like the 922 or 932, put a modern build in it, and it will smoke anything new on the market in terms of temps.
the temp drop from moving to a 932 was a huge deal in my case. The old case had 2 front and 2 top fans, but count keep up in any shape or form to the 932.
tell that to the case makers who are making the sides with side windows
my tj07 has no side fans, and i have no cooling issues, but i also dont have a 3090 dumping all that heat in to the case, which is probably the problem with his throttling issues.
I am continually amazed that such an obviously inefficient form factor continues to be the standard. No GPU waste heat should be exhausted into a case.
Nobody wants 3U GPUs, which is what you'd need to get rid of GPU waste heat without sounding like a hairdrier. There's a reason 2U blower-style GPUs aren't popular.
Since SLI and Crossfire are dead you’re overstating the dislike of 3-slot GPUs as well. Knickers didn’t get twisted from running two two-slot cards. Even designs that exhaust waste heat into cases are much better in 3-slot form, since they help to combat the absurdity of using tiny fans for the cooling.
Pet peeve time. I am PRETTY sure I read of someone at AMD saying that trx40 would not be a one processor socket.... Seems AMD can lie with a straight face. Our good Doctor Cutress could ask this rather embarrassing question of Doctor Su, if only he could grow a pair. Given how he feels about Intel, maybe he could ask Doctor Gelsinger when a desktop (hedt) product of Intel's would have 32+ PCIe 4.0 lanes
I worked at NASA/ Johnson Space Center Houston until Feb 1 1986.Doctorates were kinda like a dime a dozen back then. Hell, I even have two.
Given the lower clock speed of Ice Lake, they probably decided there wouldn't be enough demand for a HEDT version. We'll see whether they do another X-series release for Sapphire Rapids.
> I am PRETTY sure I read of someone at AMD saying that trx40 > would not be a one processor socket.... Seems AMD can lie with a straight face.
Before you accuse them of lying and insult Ian, you should probably put in at least the minimal effort needed to get your facts straight and find an actual source to cite.
Such a lack of rigor, for a dual-doctorate! Tsk tsk. I sure hope you were more diligent in the work you did at NASA!
They're what push Alder Lake into the realm of being competitive with top-tier AMD Ryzens, because they have greater performance-density than the P-cores. Consider the charts at the bottom of these two pages:
With only 8 P-cores, the i9-12900K scored 62.8/73.9 (Spec2017 int/fp), whereas Ryzen 9 5900X scored 72.5/62.3. And if you used the area of those two E-core clusters for 2 more P-cores and assume linear scaling (which it wouldn't), then the Alder Lake should score 78.5/92.4 rather than the 79.1/79.8 that it got with the E-cores.
So, even with perfect scaling, it'd still have lower int performance than it gets with the E-cores. And that's without even considering whether powering those extra P-cores would induce (further) thermal or power-based throttling.
Intel knew what they were doing, when they added those E-cores. And for people who complain about the added scheduling complexity, we have long had that issue with hyperthreading. In fact, maybe a future version of the Thread Director could even provide better scheduling of HT-enabled threads, by figuring out which are int-dominant vs. fp-heavy.
Alder Lake is a heterogeneous x86 beta test for the masses (Lakefield was the alpha test).
Considering that gaming will pretty much be locked to 8 cores for several years due to the XSX/PS5 generation, the CPUs with 6-8 P-cores should just run games on those automatically and largely avoid touching the E-cores. The user should not have to disable the E-cores to avoid lower 1% lows and other problems.
The concept of adding area and power-efficient E-cores, doubling them with Raptor Lake, and doubling them again after that is a sound one. The early adopters will just get clobbered until it works right.
I am not surprised, core count does much better than white-hot core. as cloud can utilize any amount of cores, I am not surprised, they want 8 performance for OS and as much as you can for VM's of slower, power efficient ones. now we can get any amount of cores, its not a problem to utilize 200 over 50 but when those 200 cores can do same work with less consumption, clouds would love it.
Cloud providers are not looking at little cores. they can easily run multiple servers off of the P cores, and the server parts based on ADL have no e cores to be seen.
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mode_13h - Thursday, December 30, 2021 - link
Something about Amazon's Graviton 3 and its use of Neoverse V1 cores deserves a mention....and speaking of ARM and efficient cores, the absence of a successor to the Cortex-A35 springs to mind. In fact, given how the X-series cores seem to have demoted the A700-series to mid-tier, should the A510 really be seen as something more than the A35's de facto successor?
nandnandnand - Thursday, December 30, 2021 - link
Pretty sure I already made the 5 tier joke in reply to you.Yeah, who knows. I think phones could definitely add an A35 successor for standby alongside Cortex-X2, A710 and A510, but I don't remember seeing any recent SoCs that had any A35 cores anyway. Maybe they don't get reported on as much. I do see that the Snapdragon Wear 5100 uses 4x Cortex-A53 for some strange reason.
mode_13h - Friday, December 31, 2021 - link
> Pretty sure I already made the 5 tier joke in reply to you.Yeah, and it kinda reminds me of the way automobiles were adding ever more speeds to their transmissions, so that the engine could always operate near the optimal efficiency-point.
The most tiers of cores in a single SoC that seem justified would probably be 3. The top & mid tiers should handle latency-sensitive workloads, while the bottom tier is useful for background tasks and idle-mode operation.
Kangal - Saturday, January 1, 2022 - link
I agree.But the efficiency and performance of the Cortex-A53 is pretty disappointing for today's standards. With the newer A55 and the A510 being not much better. The Cortex-A35 was pretty awesome in its hey-day as it offered a new 64bit-platform, high efficiency, for those low-power needs.
So I can actually see something like a miniaturised A510 on an 8nm, being a spiritual successor to the old 16nm A35 standing. What we really need is a much better "small core". Something that's OoO, small, and highly efficient. For instance, a Cortex-A73, updated for ARMv9 protocol, and miniaturised on 4nm for phones. Only then can Android devices begin competing properly against iOS devices. Since the lack of need to flip through both core types will save a lot of energy and latency times.
We also need a revolution on the large cores, since Apple's A13-P cores are still ahead of the latest X2 cores. I think we'll pass that threshold with the European X3 cores (second-gen ARMv9). I'd also add that the 4+4 design isn't that efficient, as the third and fourth large cores use up lots of power without being necessary contributing much computing. And we should skip the (1+3)+4 design too. We should just go with a 3+5 design instead, and either use three X3 cores if they're efficient enough, or use it's derivative (eg Cortex-A730) cores but with more cache and thermal headroom.
mode_13h - Saturday, January 1, 2022 - link
You start by saying you agree, but then you seem to argue for the opposite.I think the lowest tier cores should be optimized for energy-efficiency, period. They only need to be fast enough and supplied in quantities big enough to complete most of the background processing in a reasonable amount of time. This is purely about battery life.
I'd speculate that Apple is only using 2-tiers because they lack bandwidth in their design team to do a 3rd tier.
Kangal - Sunday, January 2, 2022 - link
I agree that the:A510 is the (spiritual) successor to the Cortex-A35, which was the successor to the Cortex-A7.
The original Cortex-A53 was great for its time in 2014, was quiet obsolete and lacklustre in 2017 or beyond. For all practical purposes, we didn't actually get a true successor. The A55 is a joke and so is the A510, if we are talking about using them as "small cores" in phones (excluding cheap budget/entry level).
We don't need more "speed tiers". Our software isn't advanced enough, and our use cases don't warrant it. It is far more ideal to reduce latency, and having a more simplified system. That's the route Apple takes, and they've been leading the market since the iPhone 5S in 2013. The Hypothetical SoC that I listed above is far better than your Hypothetical SoC with three or four different cpu types. For instance:
(3+5) X1-A73.... versus.... (1+3+3+1) X1-A78-A55-A35
(3+5) A78-A73.... versus... (4+2+2) A78-A55-A35
mode_13h - Sunday, January 2, 2022 - link
> We don't need more "speed tiers". Our software isn't advanced enough,> and our use cases don't warrant it.
That's nonsense. The OS knows which app(s) is/are running in the foreground. That's enough to prioritize their threads (at least, when the screen is unlocked) to run on the faster cores.
> That's the route Apple takes
Just because apple went with 2 tiers doesn't make it the right thing to do, you know? They could have other reasons than what's technically best.
I know you wish ARM would just design Apple-grade cores and you think that would be good enough. I'm trying to think about the problem in the abstract, and beyond simply wishing that ARM was more like Apple.
> your Hypothetical SoC with three or four different cpu types.
WTF? I clearly said, in 2 different posts, that I thought 3 tier was ideal.
Kangal - Monday, January 3, 2022 - link
Well, it's not non-sense and you're wrong. There is latency when shuffling processes from one core or complex to another. Some Apps don't require much performance, but then you run it, and later they require it. Running Apps always on the fast cores is not the solution, and nor is the opposite. So what we have right now, is the scheduler usually goes into performance mode when you interact with the screen or start up an App. Then it understands which category it needs to go into. Then it moves the process into that complex. And after a minute, it might migrate that thread back into the large cores. This behaviour is very common in something like your Web Browser.Why do you think the Helio X30 was such a flop?
Apple's philosophy is totally different. Remember these guys invented/popularised the Personal Computer. They have their own language, their own software, their own user interface, and their own hardware. And decades of experience there, but without the baggage of legacy code in iOS. So there's a big difference compared to Google.
I didn't state that ARM should just get Apple's cores. When you think about it, there's no magic in their cores. Just take the 16nm Cortex-A73, then miniaturise it in a 4nm node, modernise its feature-set without making it more complex, make it run from low-to-mid voltage, voila. Sure, it might use more power than Apple's E-cores AND it might run slower too. But it will be more inline with the current software requirements and performance demands of the main/small cores on a phone. And that translates to both a better experience than the current A53 cores, and overall better efficiency. And for the large cores, grab the Cortex-A78, add more cache and extra branch predictions, there you have an X1 core. Not as good as Apple's P-cores, but it is acceptable for its time.
Large X1 - Mini 73 (3+5) design, will run circles around the QSD 888's design of X1, A78, A55 (1+3+4) processor. It might not show it on the synthetic benchmarks, but in real-world use, it will be faster AND use less energy. And the idea of adding more "speed tiers" is just going to exasperate that.
" WTF? I clearly said, in 2 different posts, that I thought 3 tier was ideal. "
sigh. Now I know you're discussing this in bad-faith. Since you can clearly read that I said THREE or four. I did clearly read your comments, and others. Case in point, you have not commented on the comparison I made:
(3+5) A78-A73.... versus... (4+2+2) A78-A55-A35
mode_13h - Tuesday, January 4, 2022 - link
> There is latency when shuffling processes from one core or complex to another.Maybe a microsecond or so. As long as it's fairly infrequent, it's negligible.
What's costly, in terms of power, is to take a core out of sleep. And running background jobs means repeatedly doing exactly that. So, it's not only the energy used during execution that you need to think about. Therefore, background and I/O-limited threads should run on the smallest and most-efficient core possible.
> Some Apps don't require much performance, but then you run it,
> and later they require it. Running Apps always on the fast cores is not the solution,
> and nor is the opposite.
That's too simplistic, of course. It's more like this: when a thread is using its entire timeslice and it's part of a foreground app, then boost the clock speed of the core or move the thread to a more powerful core. If the thread is part of a backgrounded app or service, demote its priority, so that it'll tend to stay on the most efficient cores, even if it's compute-bound. Then, if it holds a resource blocked on by a higher-priority thread, give it the priority of the blocked thread.
Even that is a bit over-simplified, but the point is that this isn't an intractable or even a new problem. Boosting the priority of threads belonging to foreground apps is a technique that's been used for decades, on various operating systems.
> Why do you think the Helio X30 was such a flop?
I don't know anything about it, but a product can have a whole range of different issues that undermine it, such as thermal issues, inappropriate cache configuration, or even memory controller bugs that hamper performance.
> Apple's philosophy is totally different.
You don't actually know why they do what they do. To interpret their decisions without that knowledge is a bit like looking at chicken entrails. Nobody knows exactly what they mean, so they're completely open to interpretation.
> Remember these guys invented/popularised the Personal Computer.
No, they aren't. These are different people working for a company which has undergone 4+ decades of evolution. Different people; different company (effectively); very different product.
> They have their own language, their own software, their own user interface,
> and their own hardware.
So does Microsoft. And Google, even.
> but without the baggage of legacy code in iOS.
Oh, I bet there is!
> I didn't state that ARM should just get Apple's cores.
But you want to blindly follow Apple's strategy. I'm arguing that 3-tier is better, and you haven't given a good argument why it's not (except that Apple doesn't do it).
> Now I know you're discussing this in bad-faith.
> Since you can clearly read that I said THREE or four.
I never said four. That's not bad faith on *my* part. Don't make it sound like I'm saying something I'm not, and then we won't have a problem.
> Case in point, you have not commented on the comparison I made:
What do you want me to say? I'm not obligated to weigh in on a point I don't have data or the confidence to take a position on. If you want to talk about *specific* core configurations, that is a very data-driven argument, and also depends on cache + DRAM configuration.
All I'm saying is that I'd have probably 2 cores that are strictly optimized for energy-efficiency and nothing else.
movax2 - Thursday, December 30, 2021 - link
As nandnandnand says, there aren't many SoC based on A35. ( and I did laugh loud on his 5 tier joke x) . Who knows maybe we will see 4- or 5-tiers.Mediatek has tried to push A35 but SoC based on it weren't popular.
It's seems like A35 maked sense at 28nm node where A53 wasn't enough power efficient.
On 10 nm and newer, battery impact on A35 and A53 should be very similar.
RSAUser - Friday, December 31, 2021 - link
Mostly a case of diminishing returns, at such a small node size it's basically gotten to the point that the idle power of both is very similar, while peak performance for the task is higher at a similar/slightly better power efficiency.That's why watches don't have the high performance cores, since it's more important that the battery lasts longer, people don't generally use it for e.g. a game where a high single performance core for orchestration would have a large impact.
nandnandnand - Friday, December 31, 2021 - link
As I mentioned, the Snapdragon Wear 5100 got 4x Cortex-A53 instead of something like 2x Cortex-A35.wr3zzz - Thursday, December 30, 2021 - link
I haven't been this concerned about stock CPU heat since the early days of Pentium/Athlon. My 5900x could never CPU boost on all cores to 4.5Ghz and usually back down to 4.1 because of thermal. That's inside a Fractal Design 7C case with Noctua d15 CPU cooler inside a cool room.whatthe123 - Thursday, December 30, 2021 - link
sounds like bad contact. AMD's IHS quality is all over the place. my 5900x stays around 4.5~4.6 with 75C~ temps. I don't think my cooler would be 15C superior to a D15 so it's probably not a cooler problem.RSAUser - Friday, December 31, 2021 - link
Try reapplying thermal paste and reseat, sounds like the cooler is not making proper contact, since that cooler and case should have no issue cooling it (unless you've messed with the fan profiles).mode_13h - Thursday, December 30, 2021 - link
Also, I noticed that while you linked to the article, you didn't mention anything about Bergamo or its "Zen 4c" cores, which appear to be AMD's answer to Intel's Gracemont E-cores.For those who missed it, the link is: https://www.anandtech.com/show/17055/amd-gives-det...
BillBear - Thursday, December 30, 2021 - link
>Gaming is also an afterthought really, until Apple designs its own discrete GPUs.Gaming is an afterthought until studios support ARM and Metal directly. Emulation is a performance killer.
Blizzard has a native ARM and Metal version of World of Warcraft, and it runs just fine.
The PC equivalent is having AVX-512 instructions available on your CPU but your software doesn't support using those instructions.
id4andrei - Thursday, December 30, 2021 - link
WOW was already developed for mac. Transition is easy. Overwatch was not. Apple too has to support game devs and their demands regarding API features and Apple does not care. Apple expects everyone to make games for Metal, ios compatible and other platforms might just not exist.StuntFriar - Thursday, December 30, 2021 - link
This is not as big a deal as you think. For big game studios with their own bespoke engines, the engines are written with platform abstraction in mind. So when a new platform appears, the engine team will just get to work. This is how it's been for more than 20 years.And if you're using off-the-shelf engines like Unity or Unreal Engine, those already support the MacOS, iOS, ARM and Metal.
In short, there aren't any real technical limitations to developers getting their games onto Mac OS.
The real issue is that of publishing. I.e. is there any point?
Games have traditionally sold very poorly on Mac OS, so most publishers don't see the point of spending money on platform integration, QA, platform submission, etc... only to end up with about a hundred sales.
This is a ball that Apple needs to start rolling with acquisitions, 1st-party titles, exclusives if they are keen on entering the gaming market - but it doesn't look like they're that keen on it. Besides, iOS gaming is doing really well for them so there's no incentive.
Flunk - Friday, December 31, 2021 - link
This is not a very realistic opinion. Most large studies build their engines to support the major platforms only, which right now is Xbox Series, PlayStation 5 and Windows. It costs a lot of money to support additional platforms, because of all the platform-specific tuning. For off the shelf engines, it's less work provided the engine supports the platform. Not all off the shelf engines have great platform support, Unreal & Unity as two examples do, but many don't.Mac OS is not a very popular gaming platform so it's not worth developers time to develop Mac ports based on the expected sales. Add the current total lack of discrete GPU hardware (or some sort of massive GPU-centric SoC like the ones the consoles use) and you have even less reason to release Mac versions of games.
And don't get me started on the fact that Mac OS doesn't support Vulkan, that's the stupidest thing Apple has done recently. Don't support the open standard and build an inferior proprietary standard so everyone has to rewrite their rendering engines. Apple is blatantly developer hostile, which is why in most cases companies have to pay Apple devs more, because no one wants that job.
name99 - Thursday, December 30, 2021 - link
Define "gaming"...https://venturebeat.com/wp-content/uploads/2018/04...
Mobile gaming is already 59% of the market. I suspect Apple is more or less OK with the current situation...
At some point the types of gamers who are most vocal on the internet need to accept that they're a minority species, just not very important in anyone's business calculations. Some car companies see value in playing with formula one and selling muscle cars; some don't -- that's just life when you have minority tastes.
Farfolomew - Thursday, December 30, 2021 - link
The new M1 MacBooks, despite being able to run IOS Games (Mobile games, as referred in your article) don't have touchscreens, which severely their limit capability on said games. Thus, combined with the bad emulation performance, the M1-equipped laptops are really not that good for gaming, either mobile or classical.fishingbait15 - Thursday, December 30, 2021 - link
Since this article is about PC chips then obviously the definition is PC gaming, which excludes mobile gaming. Also, if you must talk about mobile games on PCs, lots more people play mobile games on Chromebooks than they do on Macs. Why? For 3 reasons. 1. Few iOS developers have agreed to allow or support iOS games on macOS where all Android games are on ChromeOS. 2. They are only available on M1 Macs - which are a small minority of Macs in the wild - where Android games run on both x86 and ARM Chromebooks. 3. The biggest reason: ChromeOS supports touchscreens where macOS doesn't. And it gets better - or worse - when Android apps come to Windows 11 next year (with independent solutions provided by Google and Microsoft/Amazon) that will also crush mobile gaming on macOS.So yeah, macOS - due to its under 10% market share (now #3 behind Windows and ChromeOS) and platform limitations imposed by Apple, hasn't been a factor in gaming since the early 90s Sierra Online days and will never be again.
Zoolook - Sunday, January 2, 2022 - link
Bluestacks works well on windows 11 so arguably you can play any android game on windows 11.whatthe123 - Thursday, December 30, 2021 - link
mobile is high revenue from a lower population of users. top spenders or "whales" spend outspend normal users exponentially, so the revenue to user count isn't all that favorable for manufacturers. You can see the results in earnings reports from companies with both gambling games and traditional mobile games. Their traditional mobile games go absolutely nowhere while their microtransaction revenue is through the roof.haukionkannel - Saturday, January 1, 2022 - link
Definitely mobile gaming! Young people own gaming phones, not gaming computers any more. The move to mobile gaming is just starting to move faster!I am old fashion gamer with gaming computer, but I also know that I am a fossil!
Zoolook - Sunday, January 2, 2022 - link
It's not a move it's a different market growing on it's own, it's not hordes of PC gamers "moving", I'm sure some older PC gamers are also playing some mobile games but I'm also sure that very few quits playing games on PC to only play mobile games.It's two very different things, IMHO most of the mobile gaming industry are more like casino gaming than PC gaming, but that's just my opinion.
WaltC - Thursday, December 30, 2021 - link
AMD has been emphasizing efficient cores since Zen2 2.5 years ago--the most efficient core gets the single thread (usually.) This can change, too, based on the software that is being run, etc. For multicore, you want all cores maxed out, of course, also done by AMD since Zen2 debuted.whatthe123 - Thursday, December 30, 2021 - link
by efficient I'm assuming they mean "small" cores with better perf/watt scaling, not simply the same design with higher silicon quality.nandnandnand - Thursday, December 30, 2021 - link
It's possible that AMD could have used the above strategy in perpetuity without adopting a heterogeneous design to counter Intel's small cores. By the time we get down to 2nm or so, it would be possible to put 16-32 big cores in the die area where 8 cores used to be, more than enough for most consumers. Then just have some of them favored to run at higher clock speeds as needed.But now we have confirmation of Zen 4c which supports the rumor of 8x Zen 5 + 16x Zen 4c processors. AMD can shave off some clock speed, cache, and features (apparently not hyperthreading), fit more cores in a smaller area, and hopefully improve both perf/watt and perf/area. Coming in much later than Alder Lake, they can benefit from a couple years of OS/software/game optimizations targeting 8 big cores and 8-16+ slower small cores.
There's x86's ultimate future for most users. 8-16 big cores, and dozens to hundreds of smaller cores. Alongside iGPU, machine learning, and other accelerators.
mode_13h - Friday, December 31, 2021 - link
> By the time we get down to 2nm or so, it would be possible to put 16-32 big> cores in the die area where 8 cores used to be
A while ago, I recall reading about a point where silicon manufacturing can keep getting the features smaller, but the density of gate activity has to be lower to combat leakage, or something like that. If it turns out to be true, then big "small" cores could be a good approach.
> There's x86's ultimate future ... 8-16 big cores, and dozens to hundreds of smaller cores.
We need some software innovations to make use of so many little cores. Innovation in thread synchronization, communication, scheduling, and management. It would have to span all the way from the silicon to the OS and userland threading APIs. All solvable problems, but I'm not aware of a lot of movement in most of these areas.
nandnandnand - Friday, December 31, 2021 - link
Well if anything is going to spur that movement, it should be Alder Lake and Raptor Lake. Raptor Lake i9 in particular, that will have 16 efficiency cores which is a lot to leave on the table. Heterogeneous AMD could launch over a year after Raptor Lake.mode_13h - Friday, December 31, 2021 - link
It needs a concerted industry push, whereas you're describing a "build it and they will come" approach. We already have 256-thread CPUs and even *that* didn't lure software parties to do the necessary work.Intel contributed TBB, which was a big help in app multithreading. However, it's not enough.
When a process wants to spin up worker threads, this is something that should be managed by the kernel. That keeps the CPU from getting swamped with too many worker threads fighting each other, it lets the kernel dynamically apportion them, and it also enables the kernel to schedule them to run as a group.
Google has been working on some threading improvements, but their progress seems glacial.
Hulk - Thursday, December 30, 2021 - link
Can somebody explain this sentence to me? It seems to be implying processor performance has decreased over the year?"Now at the end of the year, processors are plentiful, but the needle has swung in the other direction when it comes to performance."
RSAUser - Friday, December 31, 2021 - link
No, it means they are not targeting performance anymore, rather they are targeting power efficiency.Tbh, the statement is a bit iffy, most of the power efficiency is due to having hit the limit of silicon at the node size, so upping power etc. will yield minimal performance gains, so rather make it more efficient in power usage, so can then up the power envelope again, both increasing performance.
techjunkie123 - Saturday, January 1, 2022 - link
I believe they're talking about the fact that Intel holds the CPU performance crown over AMD right now, with the release of Alder Lake. AMD was the winner when Zen 3 was launched, and stayed the winner against Intel 11th gen (which was a joke tbf). Now Intel's recently launched 12th gen is generally superior to Zen 3 and also offers a big improvement over their lackluster 11th gen parts.Mike Bruzzone - Thursday, December 30, 2021 - link
British humor? 10-core Comet Lake processor, built on the Skylake++++ platform, that Intel created 'because its Core i9-11900K was too high a frequency to bin enough hardware to provide the number of units demanded by the ecosystem'". Demanded by the ecosystem? Before or after Rocket initial application performance reports. Intel could have spent more silicon area on the part to overcome some performance limits. Ultimately Rocket is an AVX 512 developer's appliance if only Intel had positioned as such would have caused far less conundrum. W 1390 sells albeit in tiny volume v Core while Core 11th sits on the shelf."but in Intel’s recent financial calls, the demand for the high-end 40 core parts wasn’t really there, with customers preferring to stay around the 28-core. There are suggestions that this might be because Intel’s yields on the 40-core are low, however it will be interesting to see how strong Intel will suggest its 2022 platform, 4th Gen Sapphire Rapids, as a direct replacement to those sticking on 1st/2nd gen hardware."
Astute observation [how fast] Sapphire Rapids movement into = / > 32 core market? 40 Core Ice represents 3% of Xeon Ice lake full run volume and adding 38C 6%. Yield, hard to say, Ice is an intermediate technology in relation what came before and what will come after. Fact is AMD purposely focuses Epyc supply at 32C and above equals 48% of all Milan volume over the full run. Designed to keep Intel out of hyperscale volume wise, albeit, AMD total Milan volume in q3 2021 was 17% of Intel in quarter production.
On the Intel ecosystem stuck at 28 cores its applications driven and primarily by enterprise. 28C is a sweet spot on incremental upgrade. Across the Xeon Scalable platform market as a whole the primary core grades being replaced on channel data are 14C and 20C. Channel is supplying Skylake and Cascade 24 through 26C. Then the question is what's happening greater than 26C? On that question whether wait and see and who's platform; Intel or AMD. AMD hyperscale is an adequately evolving niche stronghold on AMD supply constraint. The key question is which way the enterprise market will lean. mb
demian_thorne - Thursday, December 30, 2021 - link
Astute post Mike. Few people here that are not fanboys of something.Myself, being involved in enterprise procuring, let me chime in my $0.02
Enterprise looks at the cost of the new platform plus performance. Power costs are not that important.
If AMD provides very competitive pricing and the particular software runs well, they will get more market share. Enterprise procurers tend to be less cutting edge and more conservative than their hyperscale counterparts since they protect their own employment first and then the companies best interests :)
You know what is a valid question? Give that AMD does have some supply constraints, do they really want to get to the enterprise now or focus more on solidifying their hyperscaler dominance?
If I was running the biz, I would throw the kitchen sink to get so deep in the hyperscalers that INTC would have way too much difficulty to unseat me in the future. Looking at how Lisa prioritizes the production so far, I am guessing she is in agreement with my thinking :)
Mike Bruzzone - Thursday, December 30, 2021 - link
@ demian, Solidifying hyperscaler dominance. I think we're all in agreement. mbFarfolomew - Thursday, December 30, 2021 - link
Regarding your first point, I think it was a typo on Ian's part, and he meant to refer to the 10900K, not the 11900K. At the time of the article for the 10850K in question, Rocket Lake hadn't even been released yet.Mike Bruzzone - Thursday, December 30, 2021 - link
mbeastcoast_pete - Thursday, December 30, 2021 - link
I know that it would be a nightmare to get it right, but a BIOS and main board that could accept both DDR4 and DDR5 RAM (not mixed on the same board) would help with AL acceptance. Many of us have a pair of DDR4 modules from current builds, and if I could use those while I wait for DDR5 prices to come down to planet Earth, I might upgrade. Just a thought. And yes, I know that having 4 or 6 slots of mixed standards is a headache in the making, but still, might be worthwhile.Wereweeb - Thursday, December 30, 2021 - link
Yeah, honestly, there's not much reason to populate the four DIMM slots that come in most ATX motherboards. One can easily have 128GB of RAM by using 2x64GB DIMMs. For 99% of users that's already an obscene amount of RAM.Four DIMMs are more useful if you want to build a dual-channel system and later upgrade the RAM amount without waste.
2xDDR4 and 2xDDR5 slots on the same motherboard would increase it's useful life for those willing to buy one.
RSAUser - Friday, December 31, 2021 - link
Because it would add quite a bit of cost in terms of testing and support, there also isn't much point as performance difference between DDR4 and 5 is minimal, so the only reason right now for 5 is larger DIMMs, whereby having 4 DDR4 DIMMs would satisfy near all use-cases so why make 2 of them 5?.mode_13h - Saturday, January 1, 2022 - link
Depending on how much cost it would add to the board, you might not even be much better off than if you started with an entry-level DDR4 board and later upgraded to a DDR5 board, if/when you wanted to switch.TheinsanegamerN - Monday, January 3, 2022 - link
See the moves from SD to DDR, DDR to DDR2, DDR2 to DDR3, and DDR3 to DDR4. Every single one of these generations had combo boards to help adoption.DDR5 isnt magic, it has the same issue, and surpise surprise intel decided to disallow it this time and DDR5 acceptance is slow compared to dDR4. Whoda thunk it?
GeoffreyA - Saturday, January 1, 2022 - link
My Pentium 166's motherboard had 4 SIMM slots and 1 DIMM that could take SDRAM. The SIMMs had 48 MB of EDO RAM across four sticks.mode_13h - Saturday, January 1, 2022 - link
Wow, that's nuts! I've never seen or heard of a board like that!GeoffreyA - Sunday, January 2, 2022 - link
I'll try to find the manual, but the case and parts are still in my room, where it's become a makeshift bookstand. In all likelihood, the SIMMs and DIMM couldn't be used at the same; and I never did get the DIMM working, because I tried 100 MHz SDRAM but the bus was 66 MHz. I believe it was the i437 chipset. This is almost exactly what it looked like except that it was green:https://thumbs.worthpoint.com/zoom/images1/1/1017/...
shabby - Saturday, January 1, 2022 - link
A few months ago there was an article here that said al can support both on the same mobo but intel won't allow it. Maybe intel will change their mind now seeing how asus is developing a ddr4 to ddr5 card.Farfolomew - Thursday, December 30, 2021 - link
@Ian, I believe there's a typo when you refer to the 11900K when comparing it to the 10850K. I believe you meant to say 10900K?[email protected] - Thursday, December 30, 2021 - link
Confused. You can throttle individual cores of the same type and be effcient. Or you can create complexity with 2 types of cores - one regular and one efficient. Is this an Intel die size issue going from 14nm to something smaller? Something has happened with Intel and die size?kwohlt - Thursday, December 30, 2021 - link
Gracemont is not just efficient, it's also physically much smaller than Zen cores.The idea being that CPUs in the near future will be a few "high performance cores", and then dozens of small, efficient cores, various workload and AI accelerators, a beefy iGPU, etc.
Having an architecture that has a single core performance of "good enough" while being ridiculously small and power efficient allows Intel to stick with a few power hungry cores and then tacking on a boatload of small cores.
AMD will eventually shift to multiple core types as well, just like every other CPU manufacturer has.
TheinsanegamerN - Monday, January 3, 2022 - link
Th eissue here is that a downclocked P core can easily outperform the E core while also drawing less power. The E core has failed at its primary task, that being more efficient.Oxford Guy - Monday, January 3, 2022 - link
Marketing magic. More cores = Mhz myth.mode_13h - Tuesday, January 4, 2022 - link
> downclocked P core can easily outperform the E core while also drawing less power.Source? Intel's marketing materials for Lakefield did show a cross-over point, beyond which Tremont cores @ max clock speed were less efficient than Sunny Cove cores. So, it's conceivable that's still true of Gracemont and Golden Cove.
https://www.anandtech.com/show/15877/intel-hybrid-...
However, what you're forgetting about (at least for desktop applications) is perf/area which effectively means perf/$. And there, we know Gracemont offers about 2x the perf/area of Golden Cove. So, it turns out that for the same area as an 8+8 ALD die, you could only have a 10+0 die that would have lower all-thread performance than the 8+8 configuration. Indeed, the benchmarks confirm this, although results are lower than the 12+0 -equivalence predicted by linear scaling.
mode_13h - Friday, December 31, 2021 - link
One way to think about Intel's E-cores is in terms of area-efficiency. And because cost is roughly proportional to area, that also means more perf/$.So, basically, adding 8 E-cores was a cheaper way for Intel to increase the aggregate performance of Alder Lake than simply adding another 2 P-cores.
wr3zzz - Friday, December 31, 2021 - link
Thanks for the suggestions. The cooler and paste seem fine. The 5900X is sharing the case with RTX3090 and there is too much heat build up during sustained stress. At stock the 5900X throttles back to all core 4ghz almost immediately. I under volt both the CPU and GPU and could hit 4.4Ghz all cores for a few minutes but eventually the RTX3090 will add to the heat and the 5900X will throttle back down to 4.1ghz. The RTX3090 on the other hand always hits above its advertised speed and could sustain the clock without suffering from throttle. It's just not right AMD advertises the 5900X using words like its "maximum" boost is 4.8Ghz when the CPU is so sensitive to heat at stock. I could add more fans to exhaust the case of heat but I shouldn't need to in order to just to hit the "stock" boost is what I am saying.Makaveli - Friday, December 31, 2021 - link
Are you cooling both CPU and GPU with air?wr3zzz - Saturday, January 1, 2022 - link
Yes. NH-D15 for CPU and stock MSI 3 blower fan for the 3090. Two system fans front and back.mode_13h - Friday, December 31, 2021 - link
Rather than add more exhaust fans, do you have room to add any more intake fans? Years ago, I remember seeing some claim from a case manufacturer that positive-pressure not only gave you better dust filtration (if your case even *has* dust filters, that is), but also resulted in better air circulation and therefore lower temps.Qasar - Saturday, January 1, 2022 - link
the 5900x i have with the NH-D15 cooler under load is 66c and, according to cpuz is running @ 4.5 and ryzen master says all core @ 4.3-4.4. maybe you didnt lucky with the silicon lottery ?wr3zzz - Saturday, January 1, 2022 - link
After under volt, idle temp is 45c and regular tasks rarely went above 65c. I could run all cores @ 4.5Ghz at ~85-87c stressing only the CPU drawing but 125W in HandBrake. However, once the 3090 is engaged which is needed for all my heavy load tasks, 5900x will hit the 90c throttle and could sustain only 4.1Ghz. This is after under volt, at stock the 5900x will hit 90c right away and throttle back to 4.1Ghz even with 3090 at idle.This is my point. "Stock speed" used to be the floor but now is actually more a ceiling with current gen of AMD. Nvidia stock clock is still the floor with my 3090 as my GPU boosts way above its stock clock. I don't know what it's like for Intel.
Qasar - Sunday, January 2, 2022 - link
sounds like not enough airflow to me then. have you maybe tried taking the side cover off, putting a fan beside and seeing what happens ?cause if it does that when the 3090 starts dumping its heat in to the case, then that could be it.
i have no issues with throttleing with my 5900x
TheinsanegamerN - Monday, January 3, 2022 - link
The lack of side fans on modern cases is becoming a major issue wit the power draw of modern hardware. Take an old HAF case, like the 922 or 932, put a modern build in it, and it will smoke anything new on the market in terms of temps.the temp drop from moving to a 932 was a huge deal in my case. The old case had 2 front and 2 top fans, but count keep up in any shape or form to the 932.
Bring back the side fans!
Qasar - Monday, January 3, 2022 - link
tell that to the case makers who are making the sides with side windowsmy tj07 has no side fans, and i have no cooling issues, but i also dont have a 3090 dumping all that heat in to the case, which is probably the problem with his throttling issues.
Oxford Guy - Monday, January 3, 2022 - link
I am continually amazed that such an obviously inefficient form factor continues to be the standard. No GPU waste heat should be exhausted into a case.mode_13h - Tuesday, January 4, 2022 - link
Nobody wants 3U GPUs, which is what you'd need to get rid of GPU waste heat without sounding like a hairdrier. There's a reason 2U blower-style GPUs aren't popular.mode_13h - Tuesday, January 4, 2022 - link
Sorry, I meant 3-slot / 2-slot.Oxford Guy - Tuesday, January 4, 2022 - link
Since SLI and Crossfire are dead you’re overstating the dislike of 3-slot GPUs as well. Knickers didn’t get twisted from running two two-slot cards. Even designs that exhaust waste heat into cases are much better in 3-slot form, since they help to combat the absurdity of using tiny fans for the cooling.Oxford Guy - Tuesday, January 4, 2022 - link
There are other form factors. Blowers are not required nor desired.mode_13h - Tuesday, January 4, 2022 - link
> Bring back the side fans!And how about all-aluminum cases with no windows, while we're at it? Windows are even less heat-conductive than steel.
croc - Saturday, January 1, 2022 - link
Pet peeve time. I am PRETTY sure I read of someone at AMD saying that trx40 would not be a one processor socket.... Seems AMD can lie with a straight face. Our good Doctor Cutress could ask this rather embarrassing question of Doctor Su, if only he could grow a pair. Given how he feels about Intel, maybe he could ask Doctor Gelsinger when a desktop (hedt) product of Intel's would have 32+ PCIe 4.0 lanesI worked at NASA/ Johnson Space Center Houston until Feb 1 1986.Doctorates were kinda like a dime a dozen back then. Hell, I even have two.
Qasar - Saturday, January 1, 2022 - link
and where did you read this ? sounds like a um, croc to memode_13h - Sunday, January 2, 2022 - link
Intel put out an Ice Lake line of Xeon W, if you want an Intel high core-count workstation with PCIe 4.0.https://ark.intel.com/content/www/us/en/ark/produc...
Given the lower clock speed of Ice Lake, they probably decided there wouldn't be enough demand for a HEDT version. We'll see whether they do another X-series release for Sapphire Rapids.
mode_13h - Sunday, January 2, 2022 - link
> I am PRETTY sure I read of someone at AMD saying that trx40> would not be a one processor socket.... Seems AMD can lie with a straight face.
Before you accuse them of lying and insult Ian, you should probably put in at least the minimal effort needed to get your facts straight and find an actual source to cite.
Such a lack of rigor, for a dual-doctorate! Tsk tsk. I sure hope you were more diligent in the work you did at NASA!
Qasar - Sunday, January 2, 2022 - link
maybe thats why he isnt at nasa any moresvan1971 - Saturday, January 1, 2022 - link
The efficiency cores aren't the bling, it's the high performance cores they are tied to that everyone cares about.mode_13h - Sunday, January 2, 2022 - link
They're what push Alder Lake into the realm of being competitive with top-tier AMD Ryzens, because they have greater performance-density than the P-cores. Consider the charts at the bottom of these two pages:* https://www.anandtech.com/show/17047/the-intel-12t...
* https://www.anandtech.com/show/17047/the-intel-12t...
With only 8 P-cores, the i9-12900K scored 62.8/73.9 (Spec2017 int/fp), whereas Ryzen 9 5900X scored 72.5/62.3. And if you used the area of those two E-core clusters for 2 more P-cores and assume linear scaling (which it wouldn't), then the Alder Lake should score 78.5/92.4 rather than the 79.1/79.8 that it got with the E-cores.
So, even with perfect scaling, it'd still have lower int performance than it gets with the E-cores. And that's without even considering whether powering those extra P-cores would induce (further) thermal or power-based throttling.
Intel knew what they were doing, when they added those E-cores. And for people who complain about the added scheduling complexity, we have long had that issue with hyperthreading. In fact, maybe a future version of the Thread Director could even provide better scheduling of HT-enabled threads, by figuring out which are int-dominant vs. fp-heavy.
TheinsanegamerN - Monday, January 3, 2022 - link
So you shove a bunch of slow integer cores into a design and integer score goes up. Fantastic.Adding those cores also adds a ton of latency issues. This can be seen in games where disabling the e cores dramatically raises the 1% lows.
nandnandnand - Monday, January 3, 2022 - link
Alder Lake is a heterogeneous x86 beta test for the masses (Lakefield was the alpha test).Considering that gaming will pretty much be locked to 8 cores for several years due to the XSX/PS5 generation, the CPUs with 6-8 P-cores should just run games on those automatically and largely avoid touching the E-cores. The user should not have to disable the E-cores to avoid lower 1% lows and other problems.
The concept of adding area and power-efficient E-cores, doubling them with Raptor Lake, and doubling them again after that is a sound one. The early adopters will just get clobbered until it works right.
deil - Monday, January 3, 2022 - link
I am not surprised, core count does much better than white-hot core. as cloud can utilize any amount of cores, I am not surprised, they want 8 performance for OS and as much as you can for VM's of slower, power efficient ones.now we can get any amount of cores, its not a problem to utilize 200 over 50 but when those 200 cores can do same work with less consumption, clouds would love it.
TheinsanegamerN - Monday, January 3, 2022 - link
Cloud providers are not looking at little cores. they can easily run multiple servers off of the P cores, and the server parts based on ADL have no e cores to be seen.nandnandnand - Monday, January 3, 2022 - link
Hundreds of E-cores would be great for servers and hyperscalers. That's why AMD is branding its own implementation as "Zen 4c" for "cloud".mode_13h - Tuesday, January 4, 2022 - link
> Cloud providers are not looking at little cores.That's sort of what ARM's Neoverse N1 cores are. Amazon has transitioned the majority of its servers over to its ARM-based Graviton series of CPUs.
Raven437 - Monday, January 3, 2022 - link
To paraphrase Hemingway, Them that can does, them that can't "efficiency cores".mode_13h - Tuesday, January 4, 2022 - link
LOL. So, that's why AMD is introducing its own Zen 4c "efficiency cores"?Everyone is looking for better perf/$ and perf/W. Like them or not, efficiency cores are part of the solution.
alieenmeyer - Monday, February 7, 2022 - link
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