Is it really "cloud-optimized" or is that a buzzphrase?
If they make changes to Zen 4c and call it Zen 4d, then they can't use different binning of the same chiplet for both the Bergamo and Granite Ridge product lines.
I can see AMD using 4c, although more for mobile than for AM5. I'm not sure why Zen 5 has a relation to this. If 4c is useful alongside 5, won't it be just as useful (if not more) alongside 4? Perhaps it's just a matter of time to market, but that would only work out if Zen 4 is not Q4 2022, or Zen 5 is not that far behind 4c.
That makes sense but previous Epyc products share the same chiplets as Ryzen/Threadripper despite having more features, so why call them two different things? I guess there could be some additional tweaks to the amount of cache and such.
You look at something like Renoir, it has half the L3 of Cezanne, and 1/4 as much available to each core, but it's not awful. A 16-core Zen 4c/d chiplet should still have a decent amount of cache, presumably organized into two 8-core CCXs.
The amusing thing is that AMD is using the same IO die. If the Zen 4c chiplets use one link to the IO die like normal Zen 4 chiplets, then a 192 core package is feasible. I suspect physical space and power limitations are the reasons why AMD isn't aiming that high.
hey IAN, that slide about process offers 2x density, 2x power efficiency, and >1.25x silicon performance over the regular N7reffers to Genoa with Zen 4 cores not Bergamo Zen4c cores
also HPC variant means "high performace" so not neccesserily trade density at the expense of high-end frequency. At least that sentence you wrote doesn´t make sense at all. Either you use HPC process which means usually higher clock with less density or use more dense process which comes at the expense of higher frequency...
Zen 3 is Milan with up to 64 cores and 128 threads without 3D v cache Zen 3D is Milan-X with up to 64 cores and 128 threads with 3D v cache Zen 3+ is Zen3 with B2 stepping without 3D v cache Zen 3+D is Zen3 with B2 stepping with 3D v cache Zen 4 is Genoa with up to 96 cores and 192 threads without 3D v cache Zen 4D is Genoa-X with up to 96 cores and 192 threads with 3D v cache Zen 4c is Bergamo with up to 128 cores and 256 threads without 3D v cache Zen 4cD is Bergamo-X with up to 128 cores and 256 threads with 3D v cache Zen 5 is Turin with up to 192 cores and 384 threads without 3D v cache Zen 5D is Turin-X with up to 192 cores and 384 threads with 3D v cache Zen 5c codename is unknown or might be Turin with up to 256 cores and 512 threads without 3D v cache Zen 5cD is unknown or might be Turin-X with 128 cores and 256 threads with 3D v cache
Of course, rumors, but there are claims that there will be hybrid designs with Zen 5 + Zen 4c. Will they be on same CCD? Or will they mix CCDs? Consumer variants? Mobile?
Indeed: I suspect Zen 4c will be facing off against systems built with Gracemont cores and Sapphire Rapids' multi-die technology to get more than 200 x86 cores in a socket. I don't know how many memory controllers Intel will be wielding at that point - pin counts and motherboard traces are already getting inconvenient at 8-way DDR5.
Gracemont is garbage vs Zen 4C. The former is SKL Idk all you guys do not read AT or what ? go to 12900K review check out the E core performance where they clearly mention how it is it's competing against a 6700K CPU.
Zen 4C is sharing socket with damn Zen 4 which Lisa Su flat out mentioned in the press brief that it will be world's fastest GPC, General Purpose Compute CPU. That already defines Sapphire Rapids is going to get rekt.
The only reason they are doing it is ARM processors, usually ARM CPUs have high thread density without Hyperthreading a.k.a no SMT2 so AMD is going on them with Zen 4c Bergamo with massive 128 Core design.
There's no Multi Die Technology going on at Intel, Sapphire Rapids is 14C/Tile with 4 Tiles totaling to 56Core design on a single PCB with EMIB Foveros with same Golden Cove P cores that power Alder Lake but with lower Clocks ofc.
Also AMD clearly last time mentioned they are not interested in Big.little formula recently that too. I don't think AMD is going to copy Intel's weak Client strategy. Intel 7 a.k.a Intel 10nmESF is either 3rd or 4th iteration of 10nm - Lakefield (10nm), Tigerlake (10nmSF) and it cannot contain Golden Cove P cores at 5GHz also if you see the power consumption and heat of the ADL 12900K CPU you will see how 200W of ADL = 90C, vs 200W of CML = 75C. That's super dense so they cannot package them more than 8C at 5GHz which is why Intel got the new big little bs formula and they do not need them because they can get away with P core performance.
Ultimately my guess is AMD Is going for 2 SKU approach rather than bumbling the core formula, I really wish infact they do that. Like give the AM5 a full fat beefy Zen 4 CPU 16C32T called 7950X and the Zen 4c based 7850C at 32T but it doesn't serve any purpose, maybe they will create 7550H which has 24T of Zen 4c to combat ADL.
Zen 3+ has been used to refer to an allegedly cancelled refresh of Zen 3 Vermeer, called "Warhol", as well as the cores in Rembrandt APUs, which should be announced in January.
AMD was claiming some massive performance increases for Milan-X, but I didn't hear them give an average % increase. 768 MB of cache is clearly a different ballgame from 192 MB though.
2x density and 2x efficiency should allow AMD to make 16 core CCDs with an area below 80mm² at the same power consumption as the current 8 core CCDs. A 128 core CPU would look similar to the current 64 core CPUs.
Yes but the performance per core would suffer a lot. 1.25x performance per area. But I think they were only referring to Bergamo which is tailored for cheap cloud instances.
I hope they are able to make real improvements in cloud. Amazons epyc 7000 based instances offer disappointing performance value compared to Intel for us (enterprise java applications). Our perf tests show them offering about 30% less throughput for 90% of the price. I assume this must be cache or cloud architecture limitations because obviously those CPUs do much better than that in most benchmarks.
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nandnandnand - Monday, November 8, 2021 - link
https://videocardz.com/newz/zen-4-dense-zen4d-migh...The name change is probably for the best.
Zen 5 + Zen 4c coming in 2023.
Silver5urfer - Monday, November 8, 2021 - link
4C is cloud optimized. How is that leak from MLID is going to be 100% accurate that the Zen 5 + 4c is coming to Consumer platforms ?nandnandnand - Monday, November 8, 2021 - link
Is it really "cloud-optimized" or is that a buzzphrase?If they make changes to Zen 4c and call it Zen 4d, then they can't use different binning of the same chiplet for both the Bergamo and Granite Ridge product lines.
ET - Monday, November 8, 2021 - link
I can see AMD using 4c, although more for mobile than for AM5. I'm not sure why Zen 5 has a relation to this. If 4c is useful alongside 5, won't it be just as useful (if not more) alongside 4? Perhaps it's just a matter of time to market, but that would only work out if Zen 4 is not Q4 2022, or Zen 5 is not that far behind 4c.Matthias B V - Monday, November 8, 2021 - link
It is interesting that they can double core count by cutting cache. Intel at the same time developed a specific core to achieve similar.This really shows how bad cache is scaling and why we might see L3 been taken off the chiplets and completely stacked one day!
Wondering if Zen4C and Zen4D are the same and just incorrect leaks or if AMD differs between servers 4C and consumers 4D...
nandnandnand - Monday, November 8, 2021 - link
That makes sense but previous Epyc products share the same chiplets as Ryzen/Threadripper despite having more features, so why call them two different things? I guess there could be some additional tweaks to the amount of cache and such.You look at something like Renoir, it has half the L3 of Cezanne, and 1/4 as much available to each core, but it's not awful. A 16-core Zen 4c/d chiplet should still have a decent amount of cache, presumably organized into two 8-core CCXs.
nandnandnand - Monday, November 8, 2021 - link
I looked at the latest MLID video and it looks like he just replaced 4D with 4c. It could have been a last minute name change by AMD.Dodozoid - Tuesday, November 9, 2021 - link
Or AMD seeded different parts of the company with different variations of the name to see where the leaks are coming from...atomt - Monday, November 8, 2021 - link
96 cores to 128 cores is not quite a doubling, though? :)Kevin G - Wednesday, November 10, 2021 - link
The amusing thing is that AMD is using the same IO die. If the Zen 4c chiplets use one link to the IO die like normal Zen 4 chiplets, then a 192 core package is feasible. I suspect physical space and power limitations are the reasons why AMD isn't aiming that high.AdrianBc - Tuesday, November 9, 2021 - link
They will not double core count.According to the rumors, Genoa will have 96 cores.
Bergamo will have 128 cores, so only +33%.
The doubling is only over the current Zen 3, which is in the much less dense 7 nm process.
nandnandnand - Tuesday, November 9, 2021 - link
Double the core count per chiplet, with a similar chiplet size, while using less chiplets.del42sa - Monday, November 8, 2021 - link
hey IAN, that slide about process offers 2x density, 2x power efficiency, and >1.25x silicon performance over the regular N7reffers to Genoa with Zen 4 cores not Bergamo Zen4c coresIan Cutress - Monday, November 8, 2021 - link
Nope. We asked about it in our briefing. What they said is what I've writtendel42sa - Monday, November 8, 2021 - link
then it differ from what SU said in the videodel42sa - Monday, November 8, 2021 - link
also HPC variant means "high performace" so not neccesserily trade density at the expense of high-end frequency. At least that sentence you wrote doesn´t make sense at all. Either you use HPC process which means usually higher clock with less density or use more dense process which comes at the expense of higher frequency...ksec - Tuesday, November 9, 2021 - link
Yes it seems strange because it should be Zen 4 being based on HPC, and 4c on something else. I may need to look it up myself.ParhamXTX - Monday, November 8, 2021 - link
Zen 3 is Milan with up to 64 cores and 128 threads without 3D v cacheZen 3D is Milan-X with up to 64 cores and 128 threads with 3D v cache
Zen 3+ is Zen3 with B2 stepping without 3D v cache
Zen 3+D is Zen3 with B2 stepping with 3D v cache
Zen 4 is Genoa with up to 96 cores and 192 threads without 3D v cache
Zen 4D is Genoa-X with up to 96 cores and 192 threads with 3D v cache
Zen 4c is Bergamo with up to 128 cores and 256 threads without 3D v cache
Zen 4cD is Bergamo-X with up to 128 cores and 256 threads with 3D v cache
Zen 5 is Turin with up to 192 cores and 384 threads without 3D v cache
Zen 5D is Turin-X with up to 192 cores and 384 threads with 3D v cache
Zen 5c codename is unknown or might be Turin with up to 256 cores and 512 threads without 3D v cache
Zen 5cD is unknown or might be Turin-X with 128 cores and 256 threads with 3D v cache
The Hardcard - Monday, November 8, 2021 - link
Of course, rumors, but there are claims that there will be hybrid designs with Zen 5 + Zen 4c. Will they be on same CCD? Or will they mix CCDs? Consumer variants? Mobile?Makaveli - Monday, November 8, 2021 - link
Thanks for writing that out.flyingpants265 - Monday, November 8, 2021 - link
How much of this stuff really matters?nandnandnand - Monday, November 8, 2021 - link
AMD can use a new chiplet like Zen 4c to do their own take on big.LITTLE.The 3D V-Cache is nice too, even better for Epyc than Ryzen.
TomWomack - Monday, November 8, 2021 - link
Indeed: I suspect Zen 4c will be facing off against systems built with Gracemont cores and Sapphire Rapids' multi-die technology to get more than 200 x86 cores in a socket. I don't know how many memory controllers Intel will be wielding at that point - pin counts and motherboard traces are already getting inconvenient at 8-way DDR5.Silver5urfer - Monday, November 8, 2021 - link
Gracemont is garbage vs Zen 4C. The former is SKL Idk all you guys do not read AT or what ? go to 12900K review check out the E core performance where they clearly mention how it is it's competing against a 6700K CPU.Zen 4C is sharing socket with damn Zen 4 which Lisa Su flat out mentioned in the press brief that it will be world's fastest GPC, General Purpose Compute CPU. That already defines Sapphire Rapids is going to get rekt.
The only reason they are doing it is ARM processors, usually ARM CPUs have high thread density without Hyperthreading a.k.a no SMT2 so AMD is going on them with Zen 4c Bergamo with massive 128 Core design.
There's no Multi Die Technology going on at Intel, Sapphire Rapids is 14C/Tile with 4 Tiles totaling to 56Core design on a single PCB with EMIB Foveros with same Golden Cove P cores that power Alder Lake but with lower Clocks ofc.
Also AMD clearly last time mentioned they are not interested in Big.little formula recently that too. I don't think AMD is going to copy Intel's weak Client strategy. Intel 7 a.k.a Intel 10nmESF is either 3rd or 4th iteration of 10nm - Lakefield (10nm), Tigerlake (10nmSF) and it cannot contain Golden Cove P cores at 5GHz also if you see the power consumption and heat of the ADL 12900K CPU you will see how 200W of ADL = 90C, vs 200W of CML = 75C. That's super dense so they cannot package them more than 8C at 5GHz which is why Intel got the new big little bs formula and they do not need them because they can get away with P core performance.
Ultimately my guess is AMD Is going for 2 SKU approach rather than bumbling the core formula, I really wish infact they do that. Like give the AM5 a full fat beefy Zen 4 CPU 16C32T called 7950X and the Zen 4c based 7850C at 32T but it doesn't serve any purpose, maybe they will create 7550H which has 24T of Zen 4c to combat ADL.
mode_13h - Monday, November 8, 2021 - link
What is Zen 3+ and when is it expected?nandnandnand - Monday, November 8, 2021 - link
Zen 3+ has been used to refer to an allegedly cancelled refresh of Zen 3 Vermeer, called "Warhol", as well as the cores in Rembrandt APUs, which should be announced in January.Take Parham's list with a lot of salt.
nandnandnand - Monday, November 8, 2021 - link
AMD was claiming some massive performance increases for Milan-X, but I didn't hear them give an average % increase. 768 MB of cache is clearly a different ballgame from 192 MB though.lightningz71 - Monday, November 8, 2021 - link
It's also substantially lower latency than HBM cache based designs...Rudde - Monday, November 8, 2021 - link
2x density and 2x efficiency should allow AMD to make 16 core CCDs with an area below 80mm² at the same power consumption as the current 8 core CCDs. A 128 core CPU would look similar to the current 64 core CPUs.Wrs - Monday, November 8, 2021 - link
Yes but the performance per core would suffer a lot. 1.25x performance per area. But I think they were only referring to Bergamo which is tailored for cheap cloud instances.PixyMisa - Monday, November 8, 2021 - link
Yes, very workload dependent. Zen 4 is what you'll want for general-purpose servers.DougMcC - Saturday, November 20, 2021 - link
I hope they are able to make real improvements in cloud. Amazons epyc 7000 based instances offer disappointing performance value compared to Intel for us (enterprise java applications). Our perf tests show them offering about 30% less throughput for 90% of the price. I assume this must be cache or cloud architecture limitations because obviously those CPUs do much better than that in most benchmarks.Makste - Monday, November 29, 2021 - link
Software optimisation problem?