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  • Chaitanya - Monday, May 31, 2021 - link

    Good to see AMD keeping FSR platform agnostic.
  • Smell This - Tuesday, June 1, 2021 - link


    Doc Su and her team has "roped the dopes," again. Nicely done, AMD ... it's not just FidelityFX, though the cross-platform open approach is a winner all-around.

    AMD is taking on the industry's best __ with each industry's best stuff __ and raising the performance and efficiency bar, incrementally and on-map. Whether HPC, mobile, enterprise, desktop or gaming. Good for them and good for all of us.

    Competition is a good thing. Can't wait to hear more about V-Cache, 'TSMC 3d fabric,' and chiplet (GloFo 12nm?) design.
  • Byte - Tuesday, June 1, 2021 - link

    Probably genius FidFX works on both. Game devs will probably just focus on that as they can optimize on the consoles and port easier to PC with that one tech. AMD can hardware accelerate it and might perform worst on Nvidia showing them leading in many benchmarks.
  • flashmozzg - Tuesday, June 1, 2021 - link

    It worked for FreeSync, they hope it'll work for FSR.
  • nandnandnand - Monday, May 31, 2021 - link

    Zen 3+ = mostly the same as Zen 3 but with 3D V-Cache?
  • Makaveli - Monday, May 31, 2021 - link

    That does make sense.
  • SaturnusDK - Monday, May 31, 2021 - link

    Most likely.

    Consider the implications when used with 8 CCDs on a Zen3+ based EPYC. 1536MB of L3 cache!
  • Yournotme - Monday, May 31, 2021 - link

    It would be 768MB for 8 chiplets. The 192MB was for 2 chiplets.
  • SaturnusDK - Monday, May 31, 2021 - link

    I was talking about a 2P platform though.
  • Kamen Rider Blade - Monday, May 31, 2021 - link

    So 96 MiB for 8x Cores then?

    That boils down to 12 MiB of L3$ per Core?
  • SaturnusDK - Monday, May 31, 2021 - link

    Depends on how many cores are used on the CCD. AMD doesn't cut L3 cache with lower amounts of CPU cores used. For example the EPYC 72F3 is an 8 core model with 256MB L3 cache. So that means that each CCD only uses one CPU core but has the full 32MB L3 cache.
    So you could see EPYC models with up to 96MB L3 cache per core.
  • Sahrin - Tuesday, June 1, 2021 - link

    16MB for 5900X.
  • Kamen Rider Blade - Monday, May 31, 2021 - link

    192 MiB L3 $ thanks to 3D vCache in 12C/24T is going to be AWESOME!

    That comes out to 16 MiB of L3 $ per Core.

    What a time to be alive.
  • croc - Tuesday, June 1, 2021 - link

    No threadripper. No CPU roadmap. No Chagall. I think that my predictions of not performing at 7nm are more truth than rumor, now. I think that it is telling that on the HEDT front, there is this huge sound of silence. No credible leaks, no engineering CPU benchmarks, just a big... Nothingness.

    Two years this November.

    Maybe NOW the good Doctor can get a bit more pointed in his questioning.
  • nandnandnand - Tuesday, June 1, 2021 - link

    No competition to Threadripper.
  • TheinsanegamerN - Tuesday, June 1, 2021 - link

    No excuse for laziness. Resting on their laurels is exactly what got AMD in deep shit with athlon 64. Once the core 2s came out it took AMD 15 years to catch up, and very nearly going bankrupt.

    They cant afford to do this again. Intel will respond eventually. AMD needs to put as much room between themselves and intel right now, make as much money and build as much software infastructure as possible before Big Blue drops another big one.
  • The Hardcard - Tuesday, June 1, 2021 - link

    What laziness though. AMD has established that they are advancing in packaging and stacking, so competing with EIMB and Foveros. Roadmaps and leaked info are out for Zen 4 and Zen 5.

    As far as money, AMD is getting the full asking price for every die they can produce at TSMC. In fact, that is why there is no rush on Chagall. Threadrippers are just a separate configuration of EPYC and Milan is out, so croc’s post implying technical reasons makes no sense.

    EPYCs get AMD more revenue and profit. Currently they getting top dollar on their full production capacity, so there is no point in releasing new less money Threadrippers. Especially when, they dominate the HEDT market with Zen 2 Threadrippers.
  • Jinkguns - Tuesday, June 1, 2021 - link

    Why would AMD update Threadripper and divert chiplet production from AMD Ryzen and EYPC, which they cannot keep stocked? And it would also compete with the Radeon RDNA2 GPUs, which they could also keep stocked? An updated Threadripper makes sense to wait for TSMC 5nm, so at least it isn't competing with the Xbox/PS CPU supply on 7nm. They made the right decision as a business, I'm sorry you were personally hurt by this.
  • Qasar - Tuesday, June 1, 2021 - link

    or maybe zen 3 based TR, isnt ready yet..
  • Rezurecta - Tuesday, June 1, 2021 - link

    Gotta agree with this statement. Releasing Threadripper doesn't make sense when they can't produce enough of that silicon in the first place.
    It would be a slap in the face when you can't buy it and there is no stock.
  • Byte - Tuesday, June 1, 2021 - link

    Maybe they can skip Zen 3 to TR and go straight to Zen 4 to just blow everything out of the water with all that cache. But then again why not cash in on the Zen3 TR upgrade and give the extra year lagtime like Intel does to their HEDT platform.
  • HardwareDufus - Tuesday, June 1, 2021 - link

    Would a Ryzen Zen3+ R9 5950+ have 256MB of L3 v-cache? (4x64, where as the 12core is 3x64=192)? It's four chiplets to get to 16 cores, no? Would come end of 2021, beginning of 2022? Get to recycle the existing AM4 socket motherboards.
  • SaturnusDK - Tuesday, June 1, 2021 - link

    No, it's 2 CCDs and one IO die on both 5900X and 5950X.
  • HardwareDufus - Tuesday, June 1, 2021 - link

    ah. thanks... that's right.. they moved to 6/8 cores per CCD a while ago.... and I missed the part about the cache being stacked on the io die as well... need to improve my reading comprehension.
  • davidefreeman - Wednesday, June 2, 2021 - link

    @SaturnusDK was restating the layout of a Ryzen 9.

    A CCD is now composed of 8 core, and each chiplet only has one CCD. With this revision, there is an additional 64MB L3 cache per chiplet.

    Unlike Intel, AMD scales L3 independently of core count, so it's entirely possible that you could get a 12-core Ryzen with the full 384MB L3 cache.
  • iranterres - Wednesday, June 2, 2021 - link

    Am I precipited or is AMD just starting to rule?
  • GeoffreyA - Thursday, June 3, 2021 - link

    One Zen to rule them all and in the PC bind them. In the land of Intel, where the shadows lie.
  • GeoffreyA - Thursday, June 3, 2021 - link

    Don't mean to kick Intel while they're down but visually, AMD's keynote looks a lot better and more stylish than Intel's.
  • Spunjji - Friday, June 4, 2021 - link

    "Starting production end of the year" is an interesting one. Wonder if that's Zen 3+ or Zen 4. Either way, looks like Intel won't have long with Alder Lake before it starts getting its door kicked down!
  • nandnandnand - Friday, June 4, 2021 - link

    Rembrandt should be in production around that time, and that's rumored to be Zen 3+. But since 3D cache is unlikely to be found in an APU, I assume we'll see a Zen 3-based refresh (maybe Warhol back from the dead).
  • RomanPixel - Friday, June 4, 2021 - link

    I wonder if 3D V-Cache will also be shared between cores?
  • Altuzza - Monday, July 19, 2021 - link

    Tools or even data are no longer stored in one place. Some basic data still remains in the backend: prices, sales, catalog. But PIM (Product Information Management), CRM (Customer Relationship Management) and even Inventory Management System may not be integrated into the backend. Thanks to the headless architecture, many business tasks can be delegated to independent software products, often cloud-based, see for yourself - https://digitalsuits.co/blog/the-key-benefits-of-h...

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