Really curious to see GAA in real appliction chips and if it is as massive of an improvement as it looks.
Probably not for density but performance and power consumption.
Also I am not sure if I got it right from Samsung but does it scale / perfroms especially better for SRAM than FinFET does? That would be a massive advantage!
Exactly this. Display power generally dominates total system power consumption. Whoever wrote up that bio is trying too hard to create. Plus, IBM's stock has been receding since around 2012. So whenever they make some big promise about such and such, I take it with a boulder of salt. Making a one-off prototype is one thing. That happens sometimes as early as a decade in advance to real-world production! Actually delivering it consistently and competitively is a whole other matter entirely. The other big thing that has the alarm bells going off in my head for me right now is that their transistor density for 2nm is suspiciously close to TSMC's 3nm. I would not be surprised if Intel, through IBM, is trying to one up TSMC in perceived competitive edge who has used differing specifications to quote node size. And I would not be surprised if they are trying to reclaim their node leadership by stretching the truth a bit. Besides, TSMC's 3nm is already entering into production in 2022. When is IBM/Intel's 2nm even coming? If it's 2027, they might as well throw in the towel because TSMC will have already beat them to market with their comparable 3nm process by a good half a decade.
IBM has continued semiconductor R&R not with an aim in commercialization but rather to license the technology to others (via direct technology transfer or via patents).
The patents product of this effort affect TSMC as much as anybody else so IBM doesn't care much about who beats who to market as they get their licensing fees anyway.
Already understood, but thanks for the explanation. I still suspect that Intel is somehow going to purchase rights to this, only to still be found trailing in manufacturing prowess by 3-5 years.
Intel might not be as far behind as they seem. They've always been more stringent with their node specs than most of the rest of the industry. Its hard to compare one fab's node to another because there are so many variables, but at least in terms of density; you can see Intel's 10nm node is actually slightly better than TSMC's 7nm node.
Maybe their transition to 7nm will go more smoothly than their transition to 10nm. Sometimes fab's just stumble on a transition.
From what I've heard, Intel's problems may be more insidious. I've heard the company culture is pretty toxic which demotivates everyone and can't be turned around so easily.
Anyway, supposedly Intel plans to start offering it's fab services to more third parties which means they have to market their tech better, so they'll probably loosen their stringent specifications for what qualifies as say, a 7nm or 5nm node. In the future I expect an Intel 5nm node to more closely resemble a TSMC 5nm node instead of a TSMC 3nm node for instance.
"but at least in terms of density; you can see Intel's 10nm node is actually slightly better than TSMC's 7nm node."
Not quite. Intel's 10nm process node has a slightly higher peak density than TSMC's first-gen (non-EUV) 7nm process node, but TSMC's 2nd gen 7nm+ node (with 6 EUV layers) has a markedly higher density of 114 MTr/mm2.
The table of the article is from Wikichip and does not report the peak densities of TSMC's 7nm+ node and Samsung's 5nm node. The following article from SemiWiki does though; SemiWiki also claims a slightly higher peak density of TSMC's 1st gen 7nm node at 96.5 Mtr/mm2 and TSMC's 5nm node at 173.1 Mtr/mm2 : https://semiwiki.com/semiconductor-manufacturers/s...
GAA is used extensively in radio chips (some of the chips in your average cell station are GAA) . GAA is capable of much higher frequencies than silicon. But it costs significantly more and it's toxic to handle and lithograph. The end result is it costs multiples more than silicon and is only used where it's higher frequencies make up for the cost impacts.
Since IBM used to work with GF / SAMSUNG in the past and now also seems to collaborate more with Intel it would be interesting if / how this turns out for them taking on TSMC and if especially SAMSUNGs bet on GAA pays out...
For me it looks like they didn't want to play catch up and just focused on 3nm GAA and less on 5nmLPE which is more of a 7nmLPU+. However if the numbers are right and the reduction of 50% for 3GAAE vs 7LPP is correct it would only be between TSMC 5 nm and TSMC3 nm but closer to their 5nm and similar to intels 7nm if you compare MTr/mm2 but maybe other factors are much better. Or they just take it safe and go more agressive with GAAP.
Also curious if Intel can manage their 5nm GAA by 2024/25 and therefore catch up with TSMC GAA...
IBM's been neutral in semiconductor development, working with anyone that's willing to pay them for more than 20 years. They've been focused on the back end research for decades, their only fabs were mostly for specialized DOD chips or other products where the buyer could afford 10X the market rate for security of the chip design remaining in the US.
TSMC was not really that far ahead because of these differences in transistor densities, but now TSMC 5nm is close to where Intel is trying to get, but Intel is 3 years behind.
It does suggest that most of the advantage Apple have gained over the competition has merely been from buying up all of another company's capacity than from their own work.
Apple's IPC lead is generations ahead of the competition, and even if they were on 7nm the power efficiency loss would not be enough to eliminate their performance and efficiency lead. Also, Apple heavily invests in TSMC's new nodes, allowing them to partake as essentially beta testers for new nodes, so they aren't "buying up all of another company's capacity than from their own work" when they are investing in and working with the other company to get their leading architectures to perform well while transitioning the node from a beta release to a full release.
A14, which is the basis for the M1, has 8 wide decode, and as per Anandtech: Featuring an 8-wide decode block, Apple’s Firestorm is by far the current widest commercialized design in the industry. IBM’s upcoming P10 Core in the POWER10 is the only other official design that’s expected to come to market with such a wide decoder design, following Samsung’s cancellation of their own M6 core which also was described as being design with such a wide design.
Other contemporary designs such as AMD’s Zen(1 through 3) and Intel’s µarch’s, x86 CPUs today still only feature a 4-wide decoder designs (Intel is 1+4) that is seemingly limited from going wider at this point in time due to the ISA’s inherent variable instruction length nature, making designing decoders that are able to deal with aspect of the architecture more difficult compared to the ARM ISA’s fixed-length instructions.
Fundamentally Apple's HW has been 8 wide since 2019, 7 wide since 2017, and besides that, features a huge re-order buffer and execution units: A +-630 deep ROB is an immensely huge out-of-order window for Apple’s new core, as it vastly outclasses any other design in the industry. Intel’s Sunny Cove and Willow Cove cores are the second-most “deep” OOO designs out there with a 352 ROB structure, while AMD’s newest Zen3 core makes due with 256 entries, and recent Arm designs such as the Cortex-X1 feature a 224 structure.
On the Integer side, whose in-flight instructions and renaming physical register file capacity we estimate at around 354 entries, we find at least 7 execution ports for actual arithmetic operations. These include 4 simple ALUs capable of ADD instructions, 2 complex units which feature also MUL (multiply) capabilities, and what appears to be a dedicated integer division unit.
On the floating point and vector execution side of things, the new Firestorm cores are actually more impressive as they a 33% increase in capabilities, enabled by Apple’s addition of a fourth execution pipeline. The FP rename registers here seem to land at 384 entries, which is again comparatively massive. The four 128-bit NEON pipelines thus on paper match the current throughput capabilities of desktop cores from AMD and Intel, albeit with smaller vectors. Floating-point operations throughput here is 1:1 with the pipeline count, meaning Firestorm can do 4 FADDs and 4 FMULs per cycle with respectively 3 and 4 cycles latency. That’s quadruple the per-cycle throughput of Intel CPUs and previous AMD CPUs, and still double that of the recent Zen3, of course, still running at lower frequency.
So... process definitely means they can clock lower and consumer less power and pack more transistors in. However, even the 2018 A11 was fundamentally bigger in scope than AMD or Intel CPUs: https://www.anandtech.com/show/13392/the-iphone-xs...
Monsoon (A11) and Vortex (A12) are extremely wide machines – with 6 integer execution pipelines among which two are complex units, two load/store units, two branch ports, and three FP/vector pipelines this gives an estimated 13 execution ports, far wider than Arm’s upcoming Cortex A76 and also wider than Samsung’s M3. In fact, assuming we're not looking at an atypical shared port situation, Apple’s microarchitecture seems to far surpass anything else in terms of width, including desktop CPUs.
Basically every feature you praise is transistor invasive which means 5nm for apple is a need and is a huge advantage for them. Anyway, tremont is amd64 platform implementation and provide 2x 3-wide decoder while Intel noted that this may be combined in custom design into 1x 6-wide decoder. So 4-wide (5-wide Intel except Tremont) is just current implementations limitations on this platform and IIRC some Intel engineers already noted that they have much wider designs already done.
Apple already had an 8 wide in 2019 with the A13 at 7nm: Apple’s microarchitecture being 8-wide actually isn’t new to the new A14. I had gone back to the A13 and it seems I had made a mistake in the tests as I had originally deemed it a 7-wide machine. Re-testing it recently, I confirmed that it was in that generation that Apple had upgraded from a 7-wide decode which had been present in the A11 and 12.
The big changes between A13 and A14 are additional 70 ROB and a 4th FP pipeline. So their 7nm process didn't give them any advantage over Intel's 10nm process (from this article 7nm TSMC only has a 91 MTr/mm2, vs 10nm Intel at 100 MTr/mm2), which means all performance can be attributed to Apple's 8 wide decode vs Intels' 4+1 wide decode, Apple's 560 ROB vs Intel's 352 ROB, Apple's 6 Int and 3 FP pipelines vs Intels combined 10 Int and FP pipelines (best as I can tell from Anandtech's 2019 Ice Lake review) https://www.anandtech.com/show/14514/examining-int...
So... no, not unless you're arguing increasing the ROB from 560 to 630 and adding a 4th FP pipeline are transistor intensive.
@michael2k one thing I always mentally note when I read these things is that Intel's 10nm density claim is from OG 10nm, not 10nm++SFROFL(etc.). I'm a little frustrated there hasn't been more of a detailed investigation into this from the tech press, because in practice even their low-performance designs like Lakefield seem to have a lower density than AMD's high-performance designs on TSMC 7nm.
Yes and no on that first sentence - Apple are definitely building designs that lean on transistor density, but at each respective node their designs have still been wider than competing x86 designs *on the same node*.
"630 deep ROB" Like everything Apple has done, start by forgetting most of what you think you know...
Apple's ROB consists of ~330 "rows". A row has seven slots. "Generic" operations can go into any slot, but only one particular slot of the seven can hold "failable" operations (a branch or a load/store -- basically a thing that can mispredict and cause a flush). So in principle you can pack the ROB with about 2300 NOPs (7*330).
In reality other constraints kick in earlier. The most significant is usually the history file, which has ~624 entries. (History file records every change to register mapping, and is used, along with the closest checkpoint, in rapid recovery from a mispredict).
But you can (I have tested this) create a pattern like (int op, fp op, store op) and pack 310 of these (ie 930 "real" ops) in the ROB. ie a reasonable claim for the size of the ROB is ~930, though use of loads (which fight with int and fp ops for history file space), will reduce this.
(For specialists, you will note that means 310 stores! How's that achieved? Surely not a 310 sized store queue? No, BUT non-speculative loads stores are subject to early completion and release! The next obvious step -- early release of non-speculative registers -- is not present yet but Apple has a 2019 patent on this, and I wouldn't be surprised to see it in the A15. You're still stuck with the HF limit, of course, but it would get you past the ~384+36 physical int and ~432 fp registers in dense int (common) and fp (less common) situations. But Apple has so many register amplification techniques [the way movs are handled, the way immediates are handled, snarfing results off the bypass bus without register allocation for trivial cracked instructions] that physical register file limits are not that pressing -- and the design of Apple's physical register file is very very interesting giving you both that massive capacity and low power usage...)
The biggest constraint I see on "effective ROB size for most realistic code", going forward, is that History File limit, but I suspect that's actually easily fixed.
The real constraint is a "silent" one not visible in any structure -- it doesn't make sense to have a ROB larger than the distance over which you can effectively predict (both branches and load/store aliasing). If I were a designer at Apple, that's how I would analyze the situation -- something needs to be done about the (rare, say one in a few hundred or so) hard-to-impossible to predict branches that essentially form a speculation barrier. Possibilities include - predicating code past such instructions (easy'ish if there are just a few such instructions before the convergence point) or - splitting into two execution streams at those rare but difficult branches. (micro-architecturally this looks much like SMT, only without visible OS/developer control; it's not an OS feature it's a hidden performance feature like branch prediction)
You can compare A14@5nm to A13@7nm. There is one less FP pipeline and the ROB is 70 entries smaller. There is a 10% clock boost and SPECInt shows an 18% performance increase. Therefore architectural changes account for about 8% of the performance difference. That also means the node change allows for a 10% clock boost at no power penalty. I would assume a 7nm M1 would clock at 90% of the 5nm M1
The hypothetical density increase is 1.8x according to TSMC, but that doesn't necessarily translate to 1.8x increase in performance. Both of Apples 5nm chips come in at 133 MT/mm2 vs the 7nm A13 which comes in at 85 MT/mm2 means the real world increase is closer 1.5x.
If you want a more apples-to-apples comparison (pun intended) you can look at the A13 vs. the A14. I think someone found that the M1 cores emulate x86 code
I think someone found the M1 cores emulate x86 cores as fast if not faster than an actual modern x86 core. I mean, node shrinks are great, but they aren't magic.
That's an absurd analysis that shows zero understanding of either Apple's micro-architecture or the large suite of power/performance techniques they have used at the circuit-level.
APPLE is the best company in the world they eat Intel and AMD and TSMC and Samsung for breakfast! Their chips are like 28 years ahead of AMD and they consume 0,00001 W of energy in a DAY. They talk to you and can read your mind and they make coffee while mining bitcoins. Besides that nVIDIA is going to close their business in 1 month because APPLE chips pwn them everywhere.
It's both. The overall design of their M1 is solid, and their ARM design team have consistently out-performed the rest of the industry for years now, both in terms of year-on-year performance increases and overall performance (for the ARM architecture). In addition to that, building a working high-performance design for a cutting-edge node isn't cheap or technically trivial; even if that was all there was to it, it would still be a technical achievement!
I don't hink so, remember these are peak values and sram scales A LOT worse, 5nm sram have only a small increase of 20% over 7nm sram (very last Apple SOC) Actually SOCs and cpus are sram centric, in this condition the shift to 5nm means very little for many. Sure 5nm is not the reason Apple shit to in house silicon for some cheap laptops. Intel does well developing 10nm ++ that allow a more easy manufacturing than "actual EUV" and a 15% power consumption saving over 10nm +, that have a good advantage too over plain 10nm More or less TSMC 5nm is pretty on line with 10nm ++ from an Intel point of wiew, they have a lot of silicon capacity so a loss on logic density is negligible if they can put down the power consumption on a larger node. Better jump on 7nm or 5nm (Intel) when higher yields will are available (reliable pellicles and faster scanners). TSMC 3nm will be even weaker than TSMC 5nm.
Wow. What's in it for you? Why this desperate need to shit on TSMC and boost Intel "7nm or 5nm" which clearly you know nothing about, and nor does anybody who isn't one of the internal team directly working on these techs. Not even most Intel staff know how they will turn out.
If you wanted to be an adult, just say "Intel have some excellent minds and a very powerful tech and R&D team. I'm hoping they can pull out something good for 7nm and 5nm. TSMC have done some excellent stuff and given good competition to Intel. I'm still rooting for Intel though."
See how easy it is to be competitive but still respect the other team?
Intel has low yields on 10nm++(+) node. It's very easy to see as Tiger-Lake 8-cores was delayed again and again.
"More or less TSMC 5nm is pretty on line with 10nm ++" .... what kind of biased statement it is? TSMC 5nm is considerably densier than Intel 10nm++(+).
"More or less TSMC 5nm is pretty on line with 10nm ++" Wrong. 10nmSF is comparable to TSMC 7nm. TSMC 5nm is far ahead in density and may well be better in power characteristics, though those are difficult to compare.
"they have a lot of silicon capacity so a loss on logic density is negligible" Not even close. Where are all the 8-core Tiger Lake chips? 🤷♂️
I highly dought that 5nm was what made apple switch but it is an advantage, I mean the time they planned this stuff they were releasing stuff like the iPhone 7/8 and earlier probably tbh
Intel is not 3 years behind. There are a few considerations that have to be made.
Firstly, you are comparing TSMC's small chip, low power chip production with Intel's large chip, high powered production. Also, when Intel unveils a process it's when chips are being released on volume from it. TSMC talks about chips going into volume production. The Ryzen 3000 series and the Radeon 5000 series launched in July 2019, and with volume that wouldn't be enough for an Intel launch. Intel launched 10 nm chips for volume in September 2020 with Tiger Lake, although with a slower rollout than Intel would normally have for a new node (desktop won't be on 10 nm until 2H 2021). I'm sure there are various arguments to be made, but Intel's 10 nm is roughly equivalent to TSMC's 7 nm. So Intel is, at its worst, a year and a half behind TSMC by that metric, the metric of high powered chip availability, which is the metric that matters to Intel. (Intel has not been trying to push out a high volume, lower-powered node as soon as possible. That may change with their new foundry push.)
Secondly, Intel is not happy with the financial characteristics of their 10 nm node and so they have not latched onto it full force. But judging by AMD and TSMC's margins, TSMC's 7 nm is also an expensive node. Intel was not willing to sacrifice financial performance and attempted to defend its market share in other ways (with its platform approach, with the volume it can promise, and knowing that AMD would only have a limited volume to work with). AMD, on the other hand, is in a different market position. Going from 10% to 20% market share instead of 10% to 15% is much more important to them than going from 90% to 80% instead of 90% to 85% is to Intel, once the financial cost of the alternatives are considered. To defend that 5% market share, Intel would have to suffer the financial implications of the more expensive node on a lot more than just 5% of their production. Chip makers don't have much choice but to use TSMC's 7 nm node, because TSMC are not creating special version of their 16 nm node for customers the way Intel does for itself on its 14 nm node. (NVIDIA did choose to go for Samsung's 8 nm node, which is a version of their 10 nm node.)
It's these sort of considerations, for example, the market position the companies hold and what their goals are, that need to be taken into account to make a more accurate judgment on the technical position of TSMC compared to Intel.
Now, in terms of next gen, Intel's 7 nm should be compared with TSMC's 5 nm, although in this case Intel's 7 nm looks a bit ahead on paper. It's somewhere between TSMC's 5 nm and 3 nm, density-wise. Intel plans for volume chips availability of high powered chips on the 7 nm node in 2023. TSMC has 5 nm low powered chips out now and they've had them since September 2020. But as far as I know there won't be high volume availability of large, high-powered 5 nm chips until 2022. That puts TSMC about a year ahead of Intel in terms of timing, but with a process that's behind. In other words, if Intel manages to execute according to their current plan (admittedly something to give pause for doubt in light of their recent difficulties) Intel and TSMC will be roughly even.
Intel doesn't have a 7nm process to compare to TSMC's 5nm, hence Intel is behind by your very own logic. Trying to argue high powered vs low powered doesn't have any value when Intel has neither high nor low powered at 7nm. If Intel's HP 5nm is a 2023 design and TSMC's LP 5nm N5P (their second iteration of N5) is a late 2020 design, that's a 3 year gap. And given Intel might still hit delays, even 3 years might be optimistic; it could be 4 years.
N5 was a 15% improvement in performance over N7, and N5P is a 23% improvement in performance over N7, holding power steady.
"Intel doesn't have a 7nm process to compare to TSMC's 5nm, hence Intel is behind by your very own logic."
Intel's 7nm is beyond TSMC's 5 nm. Of course they have one. Stop trying to sound fancy "by your own logic". It doesn't make any sense.
Neither TSMC nor Intel are producing large, high volume, high powered chips on 5 (TSMC) or 7 (Intel) nm at the moment. But that doesn't mean they don't have them. They have those respective processes. We just don't know what state they are in. But the idea that we can talk about what will comin in the future with TSMC but not with Intel because, because why? because you prefer it that way? Because TSMC is producing low voltage chips on 5 nm?
We are talking about the future here, about expectations. That goes for both Intel and TSMC. It's normal to talk about expectations. It doesn't lead to a logical contradiction or to a black hole that swallows us all.
You are again comparing apples and oranges by talking about when Intel will release a large volume of large, high voltage chips to when TSMC began high volume manufacturing of small, low voltage chips. No matter how much you want to stamp your feet and insist, that is an improper comparison. Intel isn't even completing in your competition.
"N5 was a 15% improvement in performance over N7, and N5P is a 23% improvement in performance over N7, holding power steady." And that less than stellar improvement is exactly what allows Intel to move from being 1 1/2 years behind to close to even.
Intel has no shipping 7nm products. Intel planned to turn Fab 42 into a 7nm node in 2017, but is currently a 10nm node. Intel has already told shareholders that 7nm will be delayed until 2022: https://hexus.net/tech/news/cpu/144355-intel-q2-ea...
Regarding large, high volume, high powered chips: TSMC is shipping an 88 sqmm A14 with 11.8b transistors and 120 sqmm M1 with 16b transistors. The two easily resulted in tens of millions of sales these past two quarters (and nearly 10 million the very first weekend the iPhone 12 was available!)
Ice Lake 122 sqmm for a quad core part. Tiger Lake 145 sqmm for a quad core part.
You're trying to create an imaginary boundary (Not me, but you) to say TSMC isn't competing with Intel because TSMC is shipping small, low voltage chips that can't compare to Intel's non shipping similarly sized similarly low voltage chips.
You keep trying to claim Intel is catching up. Fine, in late 2022 to early 2023, Intel will catch up to TSMC. I don't disagree they will catch up, after all, because that is the proof that they are behind.
Intel will ship 7 nm parts in 2023. That's when they will be close to even. The M1 chips are not large, high voltage parts. The A14 is certainly not. Again, you are not considering the differences in the businesses of Apple, TSMC, and Intel.
How about this. In 2023 compare Intel's 7nm chips to AMD's competing chips at the time, and wonder how if TSMC is so far ahead of Intel that Intel is suddenly on par with AMD again? Then when you want to figure out the mystery, come back and read my messages. On the other hand you say you don't disagree with that, so I don't know why you've spent so much time arguing against it.
"...because that is the proof they are behind" This is a strange thing to say..as if your pleasure in life is that Intel is behind. I started out by saying that Intel is behind. You said they were 3 years behind, I said they were 1 1/2 years behind. You first said they won't catch up, now you say they will catch up 3 years worth of time in 2 years. I say they will catch up 1 1/2 years worth of time in 2 years.
How do you define large? M1 is a 120 sqm die, half again larger than a Zen 3 chiplet. M1X/M2 is expected to be a fair bit larger. If you adjust for the difference in density (TSMC 5nm is ~4.57x as dense as Intel 14nm), M1 is more than double the size of Intel's biggest desktop Rocket Lake CPU.
Intel's 7nm process is moderately higher density than TSMC's 5nm, but TSMC will be in mass production of their 3nm process (late 2021/early 2022) around a year before Intel's 7nm, and that's much more comparable (TSMC is then ~10% denser, so pretty close). So I'd say that if Intel's 7nm is on time, they'll have narrowed the gap, and they will only be a year and a half behind when 7nm hits mass production. If Intel's 7nm sees more delays, that's another story.
Today: Intel ships no 7nm, TSMC ships 5nm, ergo Intel's target 2023 date puts them 3 years behind TSMC
Today: M1 chips are large, at 120 sqmm. It runs as high a voltage as needed to hit 3.2GHz, by design, as any more is a waste of power. Intel, also by design, varies voltage up to clock higher. An i7 scales voltage to hit different frequencies (an 1185 scales between 12W to 28W, 1 core to 4 cores, 1.2GHz to 4.4GHz) The A14, similar to the M1, can run all cores at 96% of max speed; lon story short, it doesn't matter that M1 chips aren't high voltage, because Apple can beat Intel's performance today with lower voltage parts.
So, no we aren't going to compare 2023 parts because it isn't 2023. We are comparing 2021 parts because it's 2021. Right now Intel is 3 years behind as their competing 7nm parts won't be available until 2023, 3 years after the competitive and competing 5nm M1 was released.
Disagree isn't even the point. You're speculating on a part that doesn't exist yet. It could be 2024, making Intel 4 years behind, for example.
As for pleasure, yeah, I enjoy the technical details and I'm technically right. Until Intel ships they are behind. How far behind? We both agree 2023 is a reasonable target, and when that occurs we can compare which technology stack is most similar. Of course, 2023 is also the target date for TSMC's 3nm node, which would mean Intel won't have caught up even then because the 3nm node is ever so slightly more dense than Intel's 7nm, though at least it is far more competitive than comparing Intel 14nm to TSMC 10nm, or Intel 10nm to TSMC 7nm
There's a lot of special pleading involved here that, on closer inspection, doesn't make sense.
Your insistence on only counting a node as /really/ launching when it supports high-powered chip production is pretty arbitrary, and penalises TSMC for its partners' decisions about when to move to the newest processes. By the same token it favours Intel, who have every incentive to start pushing designs on their latest processes even when they're not performing or yielding very well (e.g. Ice Lake on 10nm+), because they are their own biggest customer.
Let's look at like-for-like. If you're counting Intel's 10nm as having been online since Ice Lake launched in September 2019 (as Intel do - RIP Cannon Lake) then by those same standards TSMC 5nm has been online since November 2020. The numbers: Ice Lake on Intel's 10nm+ is ~122.52 mm² at a ~15-28W TDP. M1 on TSMC N5 is ~120.5 mm² at a ~10-25W TDP.
On the other hand, if the benchmark for a process coming online is volume production of large / high power dies, then Intel 10nm+ only actually came online with Ice Lake SP in April 2021, starting at 370mm² with the LCC die. 10nm+ is arguably inferior to TSMC N7, and AMD launched Vega VII at 330mm² on N7 back in February 2019 - by your "big die" standard, that puts Intel around 2 years and 2 months behind TSMC on the current most relevant nodes. That's a fair bit of catching up to do.
If Intel 7nm arrives in 2023, and if it is roughly a half node ahead of TSMC 5nm (I'd expect that it will be), that's still arriving roughly a year behind TSMC's N3 and 18 months behind their N4 which ought to be roughly comparable (unless N4 sucks and 7nm rocks, which is possible!).
So: if Intel and TSMC hit their targets, Apple keep executing early on TSMC's new nodes, and Intel launch their new process with U-class chips, then on a like-for-like basis Intel will still be roughly 18 months behind TSMC when 7nm launches.
TL;DR: I don't agree with your thesis that Intel are catching up as much as you say, because you've cooked the books on the comparison between nodes by moving the goalposts on what you're comparing.
Oh it is very impressive. That however was part of the issue scaling to high power chips. Intel simply pushed things to far. They have had to loosen those densities up for high power 10nm chips and introduce some extra tricks like SuperFin.
Yeah, intel 10nm++(+) is so impressive than even Rocket-Lake was still 14nm+++++. And Alder-Lake 10nm+++(+) will still have 8 big cores comparing to Zen3 16 cores. Yeah , very "impressive"
Impressive --- and irrelevant. Intel does not make any device even CLOSE to those limits. Which makes you wonder WTF they bothered to try to reach them. The best they hit right now is ~50MTr/mm^2 https://www.anandtech.com/show/15877/intel-hybrid-...
Will Xe be better? Who knows? The rough guesses we can make from the iGPUs on existing Intel chips certainly don't suggest that Intel's GPUs run at substantially higher density that the CPUs.
So -- kill your process so you can boast of >100MTr/mm^2 -- then ship devices that only exploit half that value? Still unclear to me quite what the strategy behind that is...
(FWIW for 7nm we have multiple vendors confirming then hit >90% of TSMC's promised density.
For 5nm the situation is unclear. - The Apple results are (IMHO) meaningless because A14/M1 were clearly rushed in the sense that the ONLY priority was getting the x86/mac stuff working. The core that's not relevant to that is barely altered, the GPU is barely altered. I don't expect much effort at all was put into physical optimization. I don't think we'll have "reasonable" Apple results till at least the A15/M2. - Huawei only produced a few chips on 5nm before US Govt forced them off the process. I have seen lots of claims about the Huawei density, but they all strike me as BS, as repeating the baseline TSMC 5nm density. Not a single independent measurement or something equivalent. - We have no QC or anyone else on TSMC 5nm yet
So if someone tells you they know what achievable TSMC 5nm density is [or associated results, like the claim of *substantially* worse SRAM scaling] treat them as charlatans. So far this info is simply not public; all that is public is a lot of loud voices and ill-informed speculation.)
of most interest: how much of the production machinery is bespoke by IBM? or do they use the same ASML, et al commodity machines? IOW, is IBM really all that far ahead of the curve?
They use pretty much the same equipment as everyone else.
For EUV the Albany campus had one-off machines like a custom Micro Exposure Tool and the first Alpha Demo Tool from ASML, but right now they are using the NXE3400 from ASML.
The smallest X-Y dimension here is the 12 nm gate-length that was likely made using the NXE3400's 13 nm resolution plus some "resolution enhancement" via etching
You can currently get 1TB Micro SD cards that are a similar size to most people's fingernails. That's a more valid comparison - this process couldn't be used to make non-volatile storage,
I have 5900X lying at home, unopened. According to all the reviews - amazing processor, fast and energy efficient. Then one starts to read user experience - WHEA Errors, constant reboots, BSODs. One has to tinker for hours, days, months to get a Zen3 system stable. The AMD QC seems to be absolute garbage, push as many cpus out as possible, RMA the bad ones, and the user is the unpaid beta tester. My i7-2600K runs flawless since 10 years, on the other hand. I never had to tweak or troubleshoot anything, and I am a complete build-and-forget novice.
Intel has failed me. I do not want AMD, I want Intel, but I do not want slow and extremely hot chip. It is sad.
3900x here. 100% stable in a critical work environment granted I am using ECC ram.
Pretty sure a lot of these AMD "issues" involve unstable IMC's and RAM being pushed higher than it should. I know a lot of people want to run DDR4 3600 due to infinity fabric performance, but I think things like disconnect issues and what not stem from the IMC not being stable enough per sample basis.
AMD claims DDR4 3200(SR)/2993(DR) is supported, but they make no note of JEDEC or otherwise.
Intel has been much more conservative with official DDR4 specs even though they have a better memory controller, but it makes sense from this perspective.
Ryzen 3000/5000 cant really clock past 1900 FCLK and even this is potentially rare without overriding the voltage on some chips. Most seem to peak around 1800 FCLK, but I would expect some people to have instability. The 2700X I tested prior to my 3900x wouldn't even do 3200 with B-die ram. Went back to 7700k until 3000 series was released.. Glad I waited since the core count helps work flow.
Current Rocket lake pushes further with a 1:1 memory clock setting relative to Ryzen 3000/5000 and Skylake IMC on late 10th is technically superior to both.. at least in terms of overall latency. Rocket lake is a little more stable past 4400mhz.
You conflate the IMC with overall memory system. Yes, Comet Lake has better memory latency, but that has to do with its monolithic and more integrated architecture. Same for Rocket Lake, which *does* feature a better IMC, but actually does not go further in 1:1 mode; most RKL IMCs have trouble pushing past 3200, with 3600 being quite rare. Ryzen 3000 series very commonly pushes 3600, and 5000 series reaches 1900 quite easily, with some even reaching 2000.
However, this is moot as the gear ratios between the two architectures are substantially different. The fact remains that 3000 and 5000 series can fairly easily support memory speeds in excess of 5000 MT/s; the gearing ratio is largely independent of the actual IMC and has more to do with infinity fabric limits. Also, if you look at the monolithic designs for Ryzen, you will find that (until RKL), Renoir was the king of memory overclocking.
Of course, Intel has effectively retaken that crown with RKL, as its gearing ratio has a smaller impact on performance than AMD, and can still reach incredible speeds with excellent timings, edging out even R5000 series in that regard.
I suppose they just trade off in different areas and my mistake as I do not own and never used a RKL CPU. Just see a lot of different things going on with the chip.
We can agree that SKL and the revised CML variation is sort of the king when it comes to overall latency between high clocked memory and its controller (intel ring). RKL seems to generally go higher due to offset gearing and better PCB quality (Layer count and better memory tracing on later boards)
I didn't know rocket lake struggled on 1:1 as I've seen some chips do 2000mhz memory clock but that might be one off results. I know theres a lot of hwbot records being broken with geardown which is why I assumed. Does make sense though.. 11900K was originally spec'd as the only chip that had an official 3200 1:1 spec (2933 for everything else), but I guess they updated marketing/product pages later on. Perhaps microcode updates boosted internal voltage? Not sure.
From what I understand about Ryzen, is that the I/O Die for both 3000 and 5000 is the same but global foundries should be getting better consistency with chips over time. AMD claimed the 5000 IMC can do up to 2000 FCLK 1:1 but no one seems to be able to push it over 1900, at least consistently enough for daily use.
Ryzen still has a larger latency penalty relative to Both Skylake and Rocketlake regardless of gearing which is unfortunate, but 5000 improves it by 10 or so ns due to the more monolithic 8 core die per chiplet.
And yes I agree, Sweet spot for Ryzen seems to be high clocked 3600-3800 ram in 1:1 mode due to IF, but I do think people might not realize certain instabilities of the I/O die resulting in WHEA errors assuming bad luck with the silicon lottery.
so you suggest running at 3200, do you? When I read overclock.net thread (75 pages) that I have linked below, where people have tried everything to get their Ryzen 5000x stable, including stock bios settings for everything (including RAM), I get a different feeling. Some people have had their chips replaced through RMA, put them into their systems, without any changes between chip changes, and suddenly things worked fine.
More than those WHEA RMA BSODs the bigger issue with X570 is the USB problems on the chipset. It's not fixed with the latest AGESA. People still have that damn issue, fck even Optimum Tech guy mentions that he has a problem with USB on his main rig which is a 5900X and an Nvidia RTX 3090 FE on Custom Loop.
That issue is not going to be fixed for sure, my guess AMD fucked up the QC on their chipset and processors and boosted them to max and failed to provide a proper validation on top you don't have any friggin documentation on the AMD processors. ZERO.
I am a happy AMD user aswell. Every day use of machine, regular stuff like surfing, documents and spreadsheets, very little programming and some quite serious gaming and everything work great.
When i build my machine i always check EXACTLY what RAM is supported by my motherboard. I guess that can be the reason for problems for many people - they just check memory speed and that is all. Nope, that is not all, unfortunatelly.
There are a lot of people who get WHEA errors and crashes stock. They replaced the CPU and it worked. Some had to replace twice or three times before it worked. AMD has issues, but the fanboy force is just too powerful. They will defend everything. Remember when the USB issues (which had been going on for years) made the big news. All of the sudden thousands of people spoke up. IDK what it is with AMD fanboyism, but its not good for AMD.
Too much hassle. I still have 3 weeks to return it to the shop. I am not decided yet if I want to take my chances on it being one of the problematic ones or not.
I have purchased a 5600X, 2 of 5800X, a 5900X, and a 5950X. All of them have worked out of the box, and with particularly taxing 4-stick (dual rank) Samsung B Die that I have overclocked to 3733 14-15-14.
There are bad samples, yes. But that applies to anything.
In every sense. Your first link is marked SOLVED and the second is a thread and poll that predates AMD's fixes for the issues, and contains dozens of people saying the problems are now resolved for them (or tacitly admitting that they were overclocking when they encountered the issues in the first place).
Nice work making sure those links get spread around to as many place as possible though, you're a good little shill.
If you look at the solution in the first thread, would you call this a solution? I expect a new chip to work at stock settings, and for some people it does not. I like to tinker, but quite a lot of people do not, they just want their CPUs to work off the bat, I do not think it is too much to ask. Maybe AMD chips are for enthusiasts, who like to spend days, weeks, or months trying to "stabilize" their systems by changing all kinds of BIOS settings and exchanging everything in their hardware but CPU. I am not one of these, I do not have MBs, different RAMs, PSUs, graphics cards etc lying around. But I will take my chances on my 5900 now. If I get BSODs and WHEAs in stock BIOS settings I will RMA it immediately.
You have mental problem, quite obviously. I actually read all 75 pages of that thread so I know what people done and whether they overclocked or not. You did not, but you assumed things, and called me a shill. :-D Spunji you are a pathetic nobody. :-D
"You have mental problem, quite obviously." Yes, obviously. You are qualified to diagnose this and have definitely had sufficient interactions with me to enable you to do so.
"Spunji you are a pathetic nobody. :-D" Aren't we all?
Oh boy, it's another "random" commenter who just happened to wonder into a totally unrelated article and whine about AMD bugs. It must be a day ending in a Y.
You're claiming to have bought a $550 CPU and then left it lying around without even trying it because of stuff you read online. The options here are that you're a fool, a liar, or both.
As soon as I open the box I have to go through a return process, if I do not open the box I can return it and get cash back immediately. I know this is hard to understand for you, that some people gather info before they start on a project.
Yes, I bought the CPU because I got the chance, they are hard to come by otherwise.
Also, my time is valuable, and I do not want to spend it on "stabilizing" systems. But I will take a leap of faith now and build AMD system, maybe I get lucky and have no WHEA/BSOD/reboots.
Many people reporting issues coming up after months of running stable, though. Without ever changing anything. Thats ultimately why I decided against it. I am like you. I build and forget for 5 to 6 years. If crap like that turns up makes me mad. I got warned, I took the warning. Built a transition system now. Not nearly as powerful as the 5950x I planned to buy, but at least its super stable. I guess Ill wait for Alder Lake, or AMD to fix their issues...
"I know this is hard to understand for you, that some people gather info before they start on a project." But you're saying you did the research *after* you started on the project...
"Also, my time is valuable, and I do not want to spend it on "stabilizing" systems." But you're happy to spend it buying things you haven't researched, reading 75-page threads about them before building a system, leaving something you bought in the box, *posting about it on Anandtech* and then flinging insults at me?
Yeah, this all seems super smart and sensible, how dare I question your genius I guess.
What is so hard to believe? I was almost in the same position. I would have bought the CPU first (since they were so hard to get) and then get mainboard and the rest. But I read about those issues shortly before I bought. Decided against it after that. If I had the CPU already here, I would have left it unopened too, instead of wasting more money with a mainboard (and regrettably RAM - which has to be selected specifically with AMD in mind).
Why is it so hard to believe this first poster claims to be cautious enough not to build a system because they read a thread, but not cautious enough to read the thread before buying the CPU, and has insufficient time for testing systems but plenty of time to post about systems they haven't built on Anandtech? I dunno really, you tell me. Glad they have you to back them up though, a totally independent account who just happens to do the exact same things in these comment sections.
I did not say that. I said there is a probability given what I read in different forums. I decided to take my chances and build an AMD system now, but that's primarily because current Intel chips are way behind AMD in performance and way too hot, otherwise I would use Intel as I had good experience with them.
i havent had any issues with zen3, it was one of the easist transition honestly. b450m pro 4 bios update then i jsut plopped it in and dne easy as that
If Intel is so much denser why don't they just lower their number as is common in IT industry (well, they usually up their number for a spelling change - Google Chrome 9765778).
Firefox was behind Chrome's ultra-fast version number system so Mozilla suddenly inflated the version number. Now, as far as I know, Google is the #1 source of funding for Mozilla.
Perhaps there is something to be gleaned from that anecdote.
Intel's 14nm is roughly equivalent to TSMC's 10nm, and Intel's 10nm is roughly equivalent to TSMC's 7nm. It isn't the naming that is the problem.
The problem is that Intel 14nm shipped in 2014 with Broadwell and is still shipping in Cypress Cove in 2021! Intel 10nm shipped with Palm Cove in 2018, but that was discontinued and replaced by Sunny Cove, then Willow Cove, and now Golden Cove this year.
To put that in comparison, Apple shipped the 10nm A11 in 2017, 3 years after Intel had already been shipping 14nm parts. Apple moved to 7nm in 2018, the same year Intel's first 10nm part shipped, but due to internal delays, Intel couldn't actually transition all their products to 10nm; coupled with Apple's architectural designs, resulting in the A12 being thoroughly competitive with Intel in 2018. In 2020 Apple was able to release the A14 at 5nm, and alongside more architectural changes was thoroughly trouncing Intel (see the M1)
So changing the numbers in the name don't help Intel leapfrog any, their process is still 3 years behind. Intel 7nm is on track for a 2023 release, finally matching and beating TSMC's 2020 5nm release.
And of course, TSMC expects to theoretically beat Intel with 3nm in 2022. That assumes no delays on anyone's part.
TSMC did and is doing shuttle runs of their 4nm process in Mar 2021 and Aug 2021. They also have a shuttle run of their 3nm process in Aug 2021. Shuttle runs are wafers made for multiple customers who each buy a portion of run, with wafers shared among all of the customers. For the 5nm shuttle runs, it is currently taking nearly half a year to get chips back, so the 4nm and 3nm shuttle runs probably take that long or longer.
This is all just a way of saying that TSMC 4nm and 3nm parts are in process, but these things take time to deliver.
'nothing about transistor dimensions resembles a traditional expectation of what 2nm might be.'
Thank you for pointing this out to readers. As someone who values accuracy in terminology more than marketing emotion, it's nice to see someone state the facts rather than just the emotional appeal from marketing departments.
Perhaps putting quotes around 2nm in the headline is a good idea.
If you know nothing about instruction capability and processing power, circuit design & complexity, then you don't know anything worth knowing about the "2nm chip." Reminds me of a university study I read years ago about this college that designed and manufactured a 1,000,000 MHz chip back when CPUs were clocking at hundreds of MHz. The catch? It did exactly one instruction per clock...;) Which actually made it fairly slow at the time. I also remember when Intel was advertising that it was using 90nm in production at a time when everyone was stuck at 130nm...;) The catch? Intel used it to manufacture ram--but CPUs @ 90nm were a year or two away. There's always a catch...;)
Just because you are first doesn't mean you'll be the best. Sucks to be IBM they don't have any manufacturing capability. The only money they can make off this is the licensing deals, but does Samsung or TMSC really need it? I would say not. To take any advantage IBM would need to get these designs into someone's chip software and manufacturing. So the reality is that the only thing this is good for is "Hey, look at us! We cool!" While in reality they suck.
"Sucks to be IBM they don't have any manufacturing capability."
but... isn't that exactly the same place Apple is?
in general, all of this discussion amounts to what Gates said upwards of 40 years ago: 'Windows is slow? let the hardware fix it.' how much of 'innovation' is different from 'widen this' and 'lengthen that'? it's all just throwing more transistors at the problem. in the political world, that's just "they're just throwing money at the problem, not fixing it." of course, if you're getting the money (transistors) you're happy. sometimes the only tool you have is a sledge.
Keep in mind these are peak numbers, not average or worst case.
Frankly I don't believe there is ever a point where the transistors are as dense as Intel claims.
Intel gave out transistor count in the past when a CPU was released, they quit doing that and I think the reason why is they're making claims that they can't back up.
Intel's 14nm is not twice as dense as TSMC's 14nm on average. Their SRAM density is pretty close on all companies from 14nm down to 7nm and that's the densest part of the chip.
What are they going by to say they're twice as dense as their competitors on the same process when SRAM density is generally within 20%, even across multiple lithographies?
I remember that article from AT __ something like design *structural vs functional* densities? I don't recall if it incorporated transistor 'cell libraries' (but there was another article at about the same time concerning dense cell libraries on AMD Excavator __ maybe 'short cells' for uncore/graphics ?) ...
This isn't real. They can't produce any actual processors using this 2nm node, nor can anyone else. IBM frequently touts dramatic technological advances like this, but they never materialize as real products humans get to use. I've lost track of all their memory and storage breakthroughs, and Watson turned out to be a dud too. They're the "battery breakthrough" company of the semiconductor world – endless announcements from cloistered labs, never any products.
All of IBM's partners are the B-team right now, just a list of underperforming companies who haven't had any recent successes. Partnering with Intel will get them exactly nowhere. For reasons I don't understand, Samsung can't keep up with TSMC, and can't even design SoCs that are half as good as Apple's or 90% as good as Qualcomm. It's strange.
The purported 45% performance boost over 7nm is pretty low given that this is three generations or shrinks later. Two consecutive 20% improvements in performance, two shrinks, gives you a 44% net improvement. So 7nm to 5nm to 3nm should give you that under conservative assumptions. If going from 3nm to 2nm offers no improvement at all, well that's not a win. It's strange that they're claiming a true density improvement over 3nm processes, but performance is actually zero improvement. And that's going with their marketing numbers, so best case... And that's assuming this is a real process node that will exist in our world, which it certainly will not.
"They can't produce any actual processors using this 2nm node" They don't intend to, either. This is a tech demo to build their patent portfolio that they'll share with partners. The partners may or may not use the tech in their final processes. You'll have no idea either way, so it's not clear how you're so certain that this has never happened before?
"For reasons I don't understand, Samsung can't keep up with TSMC" Semiconductor manufacturing is *really hard*. That's it.
Wow a lot of crazy comments in here. Was just reading from Anand's chart that TSMC's 5nm is shipping for almost a year now, and already is almost tied to where Intel is trying to be 3 years from now. Not trying to start a flame war.
I do find it hilarious someone said "TSMC" has low volume, haha, that's a good joke. Just because it is hard to buy doesn't mean supply is limited, the demand is incredible. Apple is making all their Macs, and iPhones, and iPads, all on 5nm now. That is not low volume. And M1 is not a "small" chip at all.
Globalfoundries should get busy building a 2 nm fab in order to start manufacturing these. I want to see them catch up to TSMC. Easier said than done though I'm sure.
From the photo, the die size looks pretty big, ~ 800 mm2 maybe? Then the transistor density is ~62.5 MTr/mm2.
The nanosheets are quite wide, going up to 70 nm. I think these are coarser pitch than Fins, maybe even comparable to 22 nm active area pitch, so the EUV advantage is not clear over here. The usual LELE double patterning would still work.
The point of nanosheets was not to increase density but to allow gate pitch to shrink, but it seems that did not happen (44 nm).
"It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns."
This bit is very important, since most people are unaware that the listed transistor densities of fabs are just the "peak densities" for non logic parts of dies which provide the highest density and energy efficiency but the lowest performance. For instance Intel has no less than three cell libraries at 10nm, ranging from I believe ~55 million to ~100 million transistors per sq. mm. They only broadly advertise the highest density library, which is barely used, and probably not used at all for S-series desktop parts. I strongly doubt the highest density library of TSMC's 7nm process node is even used for the high performance "big" cores of mobile phone ARM processors. It might or might not be employed on the small cores which are clocked up to 2 GHz tops.
As for your table with the projected peak transistor densities I thought Intel said they were going to be more conservative with the scaling of their 7nm node and "only" target a x2 density over their 10nm node. That would place the peak density of their 7nm node at ~200 million transistors per mm^2. ~237 million transistors is a scaling of x2.37, not x2. I think wikichip calculated Intel's peak density at 7nm based on their previous x2.35 - x2.40 scaling (from 14nm to 10nm), not on their new more conservative target.
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
118 Comments
Back to Article
Matthias B V - Thursday, May 6, 2021 - link
Really curious to see GAA in real appliction chips and if it is as massive of an improvement as it looks.Probably not for density but performance and power consumption.
Also I am not sure if I got it right from Samsung but does it scale / perfroms especially better for SRAM than FinFET does? That would be a massive advantage!
Hifihedgehog - Thursday, May 6, 2021 - link
Exactly this. Display power generally dominates total system power consumption. Whoever wrote up that bio is trying too hard to create. Plus, IBM's stock has been receding since around 2012. So whenever they make some big promise about such and such, I take it with a boulder of salt. Making a one-off prototype is one thing. That happens sometimes as early as a decade in advance to real-world production! Actually delivering it consistently and competitively is a whole other matter entirely. The other big thing that has the alarm bells going off in my head for me right now is that their transistor density for 2nm is suspiciously close to TSMC's 3nm. I would not be surprised if Intel, through IBM, is trying to one up TSMC in perceived competitive edge who has used differing specifications to quote node size. And I would not be surprised if they are trying to reclaim their node leadership by stretching the truth a bit. Besides, TSMC's 3nm is already entering into production in 2022. When is IBM/Intel's 2nm even coming? If it's 2027, they might as well throw in the towel because TSMC will have already beat them to market with their comparable 3nm process by a good half a decade.Arsenica - Friday, May 7, 2021 - link
IBM has continued semiconductor R&R not with an aim in commercialization but rather to license the technology to others (via direct technology transfer or via patents).The patents product of this effort affect TSMC as much as anybody else so IBM doesn't care much about who beats who to market as they get their licensing fees anyway.
Hifihedgehog - Friday, May 7, 2021 - link
Already understood, but thanks for the explanation. I still suspect that Intel is somehow going to purchase rights to this, only to still be found trailing in manufacturing prowess by 3-5 years.Abe Dillon - Saturday, May 15, 2021 - link
Intel might not be as far behind as they seem. They've always been more stringent with their node specs than most of the rest of the industry. Its hard to compare one fab's node to another because there are so many variables, but at least in terms of density; you can see Intel's 10nm node is actually slightly better than TSMC's 7nm node.Maybe their transition to 7nm will go more smoothly than their transition to 10nm. Sometimes fab's just stumble on a transition.
From what I've heard, Intel's problems may be more insidious. I've heard the company culture is pretty toxic which demotivates everyone and can't be turned around so easily.
Anyway, supposedly Intel plans to start offering it's fab services to more third parties which means they have to market their tech better, so they'll probably loosen their stringent specifications for what qualifies as say, a 7nm or 5nm node. In the future I expect an Intel 5nm node to more closely resemble a TSMC 5nm node instead of a TSMC 3nm node for instance.
Santoval - Sunday, October 24, 2021 - link
"but at least in terms of density; you can see Intel's 10nm node is actually slightly better than TSMC's 7nm node."Not quite. Intel's 10nm process node has a slightly higher peak density than TSMC's first-gen (non-EUV) 7nm process node, but TSMC's 2nd gen 7nm+ node (with 6 EUV layers) has a markedly higher density of 114 MTr/mm2.
The table of the article is from Wikichip and does not report the peak densities of TSMC's 7nm+ node and Samsung's 5nm node. The following article from SemiWiki does though; SemiWiki also claims a slightly higher peak density of TSMC's 1st gen 7nm node at 96.5 Mtr/mm2 and TSMC's 5nm node at 173.1 Mtr/mm2 :
https://semiwiki.com/semiconductor-manufacturers/s...
rahvin - Sunday, May 9, 2021 - link
GAA is used extensively in radio chips (some of the chips in your average cell station are GAA) . GAA is capable of much higher frequencies than silicon. But it costs significantly more and it's toxic to handle and lithograph. The end result is it costs multiples more than silicon and is only used where it's higher frequencies make up for the cost impacts.shiva_c - Wednesday, May 12, 2021 - link
I think you are referring to a Galium based compound semiconductor while in the article GAA stands for Gate All Around.Matthias B V - Thursday, May 6, 2021 - link
Since IBM used to work with GF / SAMSUNG in the past and now also seems to collaborate more with Intel it would be interesting if / how this turns out for them taking on TSMC and if especially SAMSUNGs bet on GAA pays out...For me it looks like they didn't want to play catch up and just focused on 3nm GAA and less on 5nmLPE which is more of a 7nmLPU+. However if the numbers are right and the reduction of 50% for 3GAAE vs 7LPP is correct it would only be between TSMC 5 nm and TSMC3 nm but closer to their 5nm and similar to intels 7nm if you compare MTr/mm2 but maybe other factors are much better. Or they just take it safe and go more agressive with GAAP.
Also curious if Intel can manage their 5nm GAA by 2024/25 and therefore catch up with TSMC GAA...
Someone got insights on those?
rahvin - Sunday, May 9, 2021 - link
IBM's been neutral in semiconductor development, working with anyone that's willing to pay them for more than 20 years. They've been focused on the back end research for decades, their only fabs were mostly for specialized DOD chips or other products where the buyer could afford 10X the market rate for security of the chip design remaining in the US.Alistair - Thursday, May 6, 2021 - link
TSMC was not really that far ahead because of these differences in transistor densities, but now TSMC 5nm is close to where Intel is trying to get, but Intel is 3 years behind.Alistair - Thursday, May 6, 2021 - link
5nm is great, not surprised that Apple switched to Apple Silicon because of 5nm.Tams80 - Thursday, May 6, 2021 - link
It does suggest that most of the advantage Apple have gained over the competition has merely been from buying up all of another company's capacity than from their own work.But hey, an advantage is an advantage!
Otritus - Thursday, May 6, 2021 - link
Apple's IPC lead is generations ahead of the competition, and even if they were on 7nm the power efficiency loss would not be enough to eliminate their performance and efficiency lead. Also, Apple heavily invests in TSMC's new nodes, allowing them to partake as essentially beta testers for new nodes, so they aren't "buying up all of another company's capacity than from their own work" when they are investing in and working with the other company to get their leading architectures to perform well while transitioning the node from a beta release to a full release.michael2k - Thursday, May 6, 2021 - link
That's pretty false, especially if you read Anandtech:https://www.anandtech.com/show/16226/apple-silicon...
A14, which is the basis for the M1, has 8 wide decode, and as per Anandtech:
Featuring an 8-wide decode block, Apple’s Firestorm is by far the current widest commercialized design in the industry. IBM’s upcoming P10 Core in the POWER10 is the only other official design that’s expected to come to market with such a wide decoder design, following Samsung’s cancellation of their own M6 core which also was described as being design with such a wide design.
Other contemporary designs such as AMD’s Zen(1 through 3) and Intel’s µarch’s, x86 CPUs today still only feature a 4-wide decoder designs (Intel is 1+4) that is seemingly limited from going wider at this point in time due to the ISA’s inherent variable instruction length nature, making designing decoders that are able to deal with aspect of the architecture more difficult compared to the ARM ISA’s fixed-length instructions.
Fundamentally Apple's HW has been 8 wide since 2019, 7 wide since 2017, and besides that, features a huge re-order buffer and execution units:
A +-630 deep ROB is an immensely huge out-of-order window for Apple’s new core, as it vastly outclasses any other design in the industry. Intel’s Sunny Cove and Willow Cove cores are the second-most “deep” OOO designs out there with a 352 ROB structure, while AMD’s newest Zen3 core makes due with 256 entries, and recent Arm designs such as the Cortex-X1 feature a 224 structure.
On the Integer side, whose in-flight instructions and renaming physical register file capacity we estimate at around 354 entries, we find at least 7 execution ports for actual arithmetic operations. These include 4 simple ALUs capable of ADD instructions, 2 complex units which feature also MUL (multiply) capabilities, and what appears to be a dedicated integer division unit.
On the floating point and vector execution side of things, the new Firestorm cores are actually more impressive as they a 33% increase in capabilities, enabled by Apple’s addition of a fourth execution pipeline. The FP rename registers here seem to land at 384 entries, which is again comparatively massive. The four 128-bit NEON pipelines thus on paper match the current throughput capabilities of desktop cores from AMD and Intel, albeit with smaller vectors. Floating-point operations throughput here is 1:1 with the pipeline count, meaning Firestorm can do 4 FADDs and 4 FMULs per cycle with respectively 3 and 4 cycles latency. That’s quadruple the per-cycle throughput of Intel CPUs and previous AMD CPUs, and still double that of the recent Zen3, of course, still running at lower frequency.
So... process definitely means they can clock lower and consumer less power and pack more transistors in. However, even the 2018 A11 was fundamentally bigger in scope than AMD or Intel CPUs:
https://www.anandtech.com/show/13392/the-iphone-xs...
Monsoon (A11) and Vortex (A12) are extremely wide machines – with 6 integer execution pipelines among which two are complex units, two load/store units, two branch ports, and three FP/vector pipelines this gives an estimated 13 execution ports, far wider than Arm’s upcoming Cortex A76 and also wider than Samsung’s M3. In fact, assuming we're not looking at an atypical shared port situation, Apple’s microarchitecture seems to far surpass anything else in terms of width, including desktop CPUs.
kgardas - Thursday, May 6, 2021 - link
Basically every feature you praise is transistor invasive which means 5nm for apple is a need and is a huge advantage for them.Anyway, tremont is amd64 platform implementation and provide 2x 3-wide decoder while Intel noted that this may be combined in custom design into 1x 6-wide decoder. So 4-wide (5-wide Intel except Tremont) is just current implementations limitations on this platform and IIRC some Intel engineers already noted that they have much wider designs already done.
michael2k - Thursday, May 6, 2021 - link
Apple already had an 8 wide in 2019 with the A13 at 7nm:Apple’s microarchitecture being 8-wide actually isn’t new to the new A14. I had gone back to the A13 and it seems I had made a mistake in the tests as I had originally deemed it a 7-wide machine. Re-testing it recently, I confirmed that it was in that generation that Apple had upgraded from a 7-wide decode which had been present in the A11 and 12.
The big changes between A13 and A14 are additional 70 ROB and a 4th FP pipeline. So their 7nm process didn't give them any advantage over Intel's 10nm process (from this article 7nm TSMC only has a 91 MTr/mm2, vs 10nm Intel at 100 MTr/mm2), which means all performance can be attributed to Apple's 8 wide decode vs Intels' 4+1 wide decode, Apple's 560 ROB vs Intel's 352 ROB, Apple's 6 Int and 3 FP pipelines vs Intels combined 10 Int and FP pipelines (best as I can tell from Anandtech's 2019 Ice Lake review)
https://www.anandtech.com/show/14514/examining-int...
So... no, not unless you're arguing increasing the ROB from 560 to 630 and adding a 4th FP pipeline are transistor intensive.
Spunjji - Friday, May 7, 2021 - link
@michael2k one thing I always mentally note when I read these things is that Intel's 10nm density claim is from OG 10nm, not 10nm++SFROFL(etc.). I'm a little frustrated there hasn't been more of a detailed investigation into this from the tech press, because in practice even their low-performance designs like Lakefield seem to have a lower density than AMD's high-performance designs on TSMC 7nm.Spunjji - Friday, May 7, 2021 - link
Yes and no on that first sentence - Apple are definitely building designs that lean on transistor density, but at each respective node their designs have still been wider than competing x86 designs *on the same node*.name99 - Thursday, May 6, 2021 - link
"630 deep ROB"Like everything Apple has done, start by forgetting most of what you think you know...
Apple's ROB consists of ~330 "rows". A row has seven slots. "Generic" operations can go into any slot, but only one particular slot of the seven can hold "failable" operations (a branch or a load/store -- basically a thing that can mispredict and cause a flush).
So in principle you can pack the ROB with about 2300 NOPs (7*330).
In reality other constraints kick in earlier. The most significant is usually the history file, which has ~624 entries. (History file records every change to register mapping, and is used, along with the closest checkpoint, in rapid recovery from a mispredict).
But you can (I have tested this) create a pattern like (int op, fp op, store op) and pack 310 of these (ie 930 "real" ops) in the ROB. ie a reasonable claim for the size of the ROB is ~930, though use of loads (which fight with int and fp ops for history file space), will reduce this.
(For specialists, you will note that means 310 stores! How's that achieved? Surely not a 310 sized store queue? No, BUT non-speculative loads stores are subject to early completion and release!
The next obvious step -- early release of non-speculative registers -- is not present yet but Apple has a 2019 patent on this, and I wouldn't be surprised to see it in the A15.
You're still stuck with the HF limit, of course, but it would get you past the ~384+36 physical int and ~432 fp registers in dense int (common) and fp (less common) situations.
But Apple has so many register amplification techniques [the way movs are handled, the way immediates are handled, snarfing results off the bypass bus without register allocation for trivial cracked instructions] that physical register file limits are not that pressing -- and the design of Apple's physical register file is very very interesting giving you both that massive capacity and low power usage...)
The biggest constraint I see on "effective ROB size for most realistic code", going forward, is that History File limit, but I suspect that's actually easily fixed.
The real constraint is a "silent" one not visible in any structure -- it doesn't make sense to have a ROB larger than the distance over which you can effectively predict (both branches and load/store aliasing).
If I were a designer at Apple, that's how I would analyze the situation -- something needs to be done about the (rare, say one in a few hundred or so) hard-to-impossible to predict branches that essentially form a speculation barrier. Possibilities include
- predicating code past such instructions (easy'ish if there are just a few such instructions before the convergence point) or
- splitting into two execution streams at those rare but difficult branches. (micro-architecturally this looks much like SMT, only without visible OS/developer control; it's not an OS feature it's a hidden performance feature like branch prediction)
Spunjji - Friday, May 7, 2021 - link
Thanks for that analysis. I'm not sure I fully understood it, but I feel a little more informed for having read it!Tams80 - Friday, May 7, 2021 - link
But TSMC 5nm is roughly twice as dense TSMC 7nm.The *performance* of the M1 is great, but it is not so far ahead that it shows node shrink advantage and an architecture advantage.
No doubt its performance is a mix of the two, but I doubt Apple's architecture design is that far ahead.
Anyway, there's no M1 on TSMC 7nm to compare it to.
michael2k - Friday, May 7, 2021 - link
You can compare A14@5nm to A13@7nm. There is one less FP pipeline and the ROB is 70 entries smaller. There is a 10% clock boost and SPECInt shows an 18% performance increase. Therefore architectural changes account for about 8% of the performance difference. That also means the node change allows for a 10% clock boost at no power penalty. I would assume a 7nm M1 would clock at 90% of the 5nm M1https://www.anandtech.com/show/16192/the-iphone-12...
Abe Dillon - Saturday, May 15, 2021 - link
The hypothetical density increase is 1.8x according to TSMC, but that doesn't necessarily translate to 1.8x increase in performance. Both of Apples 5nm chips come in at 133 MT/mm2 vs the 7nm A13 which comes in at 85 MT/mm2 means the real world increase is closer 1.5x.If you want a more apples-to-apples comparison (pun intended) you can look at the A13 vs. the A14. I think someone found that the M1 cores emulate x86 code
Abe Dillon - Saturday, May 15, 2021 - link
(sorry, hit send accidentally)I think someone found the M1 cores emulate x86 cores as fast if not faster than an actual modern x86 core. I mean, node shrinks are great, but they aren't magic.
melgross - Thursday, May 6, 2021 - link
No, their IP is better. Don’t you read the articles about their chips here?name99 - Thursday, May 6, 2021 - link
That's an absurd analysis that shows zero understanding of either Apple's micro-architecture or the large suite of power/performance techniques they have used at the circuit-level.Kuhar - Friday, May 7, 2021 - link
APPLE is the best company in the world they eat Intel and AMD and TSMC and Samsung for breakfast! Their chips are like 28 years ahead of AMD and they consume 0,00001 W of energy in a DAY. They talk to you and can read your mind and they make coffee while mining bitcoins. Besides that nVIDIA is going to close their business in 1 month because APPLE chips pwn them everywhere.Spunjji - Friday, May 7, 2021 - link
@Kuhar sarcastic exaggeration for satire only really works as a rebuttal if the other person *isn't* making a reasonable point.Linustechtips12#6900xt - Monday, May 10, 2021 - link
That hurt the few brain cells I have left after reading that, Jesus damn christ.Abe Dillon - Saturday, May 15, 2021 - link
...you keep beating that straw man, buddy. We're all very impressed.Spunjji - Friday, May 7, 2021 - link
It's both. The overall design of their M1 is solid, and their ARM design team have consistently out-performed the rest of the industry for years now, both in terms of year-on-year performance increases and overall performance (for the ARM architecture). In addition to that, building a working high-performance design for a cutting-edge node isn't cheap or technically trivial; even if that was all there was to it, it would still be a technical achievement!Gondalf - Thursday, May 6, 2021 - link
I don't hink so, remember these are peak values and sram scales A LOT worse, 5nm sram have only a small increase of 20% over 7nm sram (very last Apple SOC)Actually SOCs and cpus are sram centric, in this condition the shift to 5nm means very little for many. Sure 5nm is not the reason Apple shit to in house silicon for some cheap laptops.
Intel does well developing 10nm ++ that allow a more easy manufacturing than "actual EUV" and a 15% power consumption saving over 10nm +, that have a good advantage too over plain 10nm
More or less TSMC 5nm is pretty on line with 10nm ++ from an Intel point of wiew, they have a lot of silicon capacity so a loss on logic density is negligible if they can put down the power consumption on a larger node. Better jump on 7nm or 5nm (Intel) when higher yields will are available (reliable pellicles and faster scanners).
TSMC 3nm will be even weaker than TSMC 5nm.
Tomatotech - Thursday, May 6, 2021 - link
Wow. What's in it for you? Why this desperate need to shit on TSMC and boost Intel "7nm or 5nm" which clearly you know nothing about, and nor does anybody who isn't one of the internal team directly working on these techs. Not even most Intel staff know how they will turn out.If you wanted to be an adult, just say "Intel have some excellent minds and a very powerful tech and R&D team. I'm hoping they can pull out something good for 7nm and 5nm. TSMC have done some excellent stuff and given good competition to Intel. I'm still rooting for Intel though."
See how easy it is to be competitive but still respect the other team?
Qasar - Thursday, May 6, 2021 - link
whats in it for him? nothing he just loves intel.movax2 - Thursday, May 6, 2021 - link
Intel has low yields on 10nm++(+) node. It's very easy to see as Tiger-Lake 8-cores was delayed again and again."More or less TSMC 5nm is pretty on line with 10nm ++" .... what kind of biased statement it is?
TSMC 5nm is considerably densier than Intel 10nm++(+).
melgross - Thursday, May 6, 2021 - link
You have problems sir.Spunjji - Friday, May 7, 2021 - link
"More or less TSMC 5nm is pretty on line with 10nm ++"Wrong. 10nmSF is comparable to TSMC 7nm. TSMC 5nm is far ahead in density and may well be better in power characteristics, though those are difficult to compare.
"they have a lot of silicon capacity so a loss on logic density is negligible"
Not even close. Where are all the 8-core Tiger Lake chips? 🤷♂️
Linustechtips12#6900xt - Monday, May 10, 2021 - link
I highly dought that 5nm was what made apple switch but it is an advantage, I mean the time they planned this stuff they were releasing stuff like the iPhone 7/8 and earlier probably tbhYojimbo - Thursday, May 6, 2021 - link
Intel is not 3 years behind. There are a few considerations that have to be made.Firstly, you are comparing TSMC's small chip, low power chip production with Intel's large chip, high powered production. Also, when Intel unveils a process it's when chips are being released on volume from it. TSMC talks about chips going into volume production. The Ryzen 3000 series and the Radeon 5000 series launched in July 2019, and with volume that wouldn't be enough for an Intel launch. Intel launched 10 nm chips for volume in September 2020 with Tiger Lake, although with a slower rollout than Intel would normally have for a new node (desktop won't be on 10 nm until 2H 2021). I'm sure there are various arguments to be made, but Intel's 10 nm is roughly equivalent to TSMC's 7 nm. So Intel is, at its worst, a year and a half behind TSMC by that metric, the metric of high powered chip availability, which is the metric that matters to Intel. (Intel has not been trying to push out a high volume, lower-powered node as soon as possible. That may change with their new foundry push.)
Secondly, Intel is not happy with the financial characteristics of their 10 nm node and so they have not latched onto it full force. But judging by AMD and TSMC's margins, TSMC's 7 nm is also an expensive node. Intel was not willing to sacrifice financial performance and attempted to defend its market share in other ways (with its platform approach, with the volume it can promise, and knowing that AMD would only have a limited volume to work with). AMD, on the other hand, is in a different market position. Going from 10% to 20% market share instead of 10% to 15% is much more important to them than going from 90% to 80% instead of 90% to 85% is to Intel, once the financial cost of the alternatives are considered. To defend that 5% market share, Intel would have to suffer the financial implications of the more expensive node on a lot more than just 5% of their production. Chip makers don't have much choice but to use TSMC's 7 nm node, because TSMC are not creating special version of their 16 nm node for customers the way Intel does for itself on its 14 nm node. (NVIDIA did choose to go for Samsung's 8 nm node, which is a version of their 10 nm node.)
It's these sort of considerations, for example, the market position the companies hold and what their goals are, that need to be taken into account to make a more accurate judgment on the technical position of TSMC compared to Intel.
Now, in terms of next gen, Intel's 7 nm should be compared with TSMC's 5 nm, although in this case Intel's 7 nm looks a bit ahead on paper. It's somewhere between TSMC's 5 nm and 3 nm, density-wise. Intel plans for volume chips availability of high powered chips on the 7 nm node in 2023. TSMC has 5 nm low powered chips out now and they've had them since September 2020. But as far as I know there won't be high volume availability of large, high-powered 5 nm chips until 2022. That puts TSMC about a year ahead of Intel in terms of timing, but with a process that's behind. In other words, if Intel manages to execute according to their current plan (admittedly something to give pause for doubt in light of their recent difficulties) Intel and TSMC will be roughly even.
michael2k - Thursday, May 6, 2021 - link
You contradict yourself.Intel doesn't have a 7nm process to compare to TSMC's 5nm, hence Intel is behind by your very own logic. Trying to argue high powered vs low powered doesn't have any value when Intel has neither high nor low powered at 7nm. If Intel's HP 5nm is a 2023 design and TSMC's LP 5nm N5P (their second iteration of N5) is a late 2020 design, that's a 3 year gap. And given Intel might still hit delays, even 3 years might be optimistic; it could be 4 years.
N5 was a 15% improvement in performance over N7, and N5P is a 23% improvement in performance over N7, holding power steady.
Yojimbo - Friday, May 7, 2021 - link
"Intel doesn't have a 7nm process to compare to TSMC's 5nm, hence Intel is behind by your very own logic."Intel's 7nm is beyond TSMC's 5 nm. Of course they have one. Stop trying to sound fancy "by your own logic". It doesn't make any sense.
Neither TSMC nor Intel are producing large, high volume, high powered chips on 5 (TSMC) or 7 (Intel) nm at the moment. But that doesn't mean they don't have them. They have those respective processes. We just don't know what state they are in. But the idea that we can talk about what will comin in the future with TSMC but not with Intel because, because why? because you prefer it that way? Because TSMC is producing low voltage chips on 5 nm?
We are talking about the future here, about expectations. That goes for both Intel and TSMC. It's normal to talk about expectations. It doesn't lead to a logical contradiction or to a black hole that swallows us all.
You are again comparing apples and oranges by talking about when Intel will release a large volume of large, high voltage chips to when TSMC began high volume manufacturing of small, low voltage chips. No matter how much you want to stamp your feet and insist, that is an improper comparison. Intel isn't even completing in your competition.
"N5 was a 15% improvement in performance over N7, and N5P is a 23% improvement in performance over N7, holding power steady."
And that less than stellar improvement is exactly what allows Intel to move from being 1 1/2 years behind to close to even.
Yojimbo - Friday, May 7, 2021 - link
*Intel isn't even competing in your competition.michael2k - Friday, May 7, 2021 - link
Intel has no shipping 7nm products.Intel planned to turn Fab 42 into a 7nm node in 2017, but is currently a 10nm node.
Intel has already told shareholders that 7nm will be delayed until 2022:
https://hexus.net/tech/news/cpu/144355-intel-q2-ea...
They expect tape-in Q2Y21, so they will probably hit 2022 or 2023 for scale release of 7nm:
https://www.intel.com/content/www/us/en/newsroom/n...
Regarding large, high volume, high powered chips:
TSMC is shipping an 88 sqmm A14 with 11.8b transistors and 120 sqmm M1 with 16b transistors.
The two easily resulted in tens of millions of sales these past two quarters (and nearly 10 million the very first weekend the iPhone 12 was available!)
You can compare to Intel's 10nm die sizes, as reported by Anandtech:
https://www.anandtech.com/show/15380/i-ran-off-wit...
Ice Lake 122 sqmm for a quad core part.
Tiger Lake 145 sqmm for a quad core part.
You're trying to create an imaginary boundary (Not me, but you) to say TSMC isn't competing with Intel because TSMC is shipping small, low voltage chips that can't compare to Intel's non shipping similarly sized similarly low voltage chips.
You keep trying to claim Intel is catching up. Fine, in late 2022 to early 2023, Intel will catch up to TSMC. I don't disagree they will catch up, after all, because that is the proof that they are behind.
Yojimbo - Friday, May 7, 2021 - link
Intel will ship 7 nm parts in 2023. That's when they will be close to even. The M1 chips are not large, high voltage parts. The A14 is certainly not. Again, you are not considering the differences in the businesses of Apple, TSMC, and Intel.How about this. In 2023 compare Intel's 7nm chips to AMD's competing chips at the time, and wonder how if TSMC is so far ahead of Intel that Intel is suddenly on par with AMD again? Then when you want to figure out the mystery, come back and read my messages. On the other hand you say you don't disagree with that, so I don't know why you've spent so much time arguing against it.
"...because that is the proof they are behind"
This is a strange thing to say..as if your pleasure in life is that Intel is behind. I started out by saying that Intel is behind. You said they were 3 years behind, I said they were 1 1/2 years behind. You first said they won't catch up, now you say they will catch up 3 years worth of time in 2 years. I say they will catch up 1 1/2 years worth of time in 2 years.
Guspaz - Saturday, May 8, 2021 - link
How do you define large? M1 is a 120 sqm die, half again larger than a Zen 3 chiplet. M1X/M2 is expected to be a fair bit larger. If you adjust for the difference in density (TSMC 5nm is ~4.57x as dense as Intel 14nm), M1 is more than double the size of Intel's biggest desktop Rocket Lake CPU.Intel's 7nm process is moderately higher density than TSMC's 5nm, but TSMC will be in mass production of their 3nm process (late 2021/early 2022) around a year before Intel's 7nm, and that's much more comparable (TSMC is then ~10% denser, so pretty close). So I'd say that if Intel's 7nm is on time, they'll have narrowed the gap, and they will only be a year and a half behind when 7nm hits mass production. If Intel's 7nm sees more delays, that's another story.
michael2k - Monday, May 10, 2021 - link
You're really playing this game?Today: Intel ships no 7nm, TSMC ships 5nm, ergo Intel's target 2023 date puts them 3 years behind TSMC
Today: M1 chips are large, at 120 sqmm. It runs as high a voltage as needed to hit 3.2GHz, by design, as any more is a waste of power. Intel, also by design, varies voltage up to clock higher. An i7 scales voltage to hit different frequencies (an 1185 scales between 12W to 28W, 1 core to 4 cores, 1.2GHz to 4.4GHz) The A14, similar to the M1, can run all cores at 96% of max speed; lon story short, it doesn't matter that M1 chips aren't high voltage, because Apple can beat Intel's performance today with lower voltage parts.
So, no we aren't going to compare 2023 parts because it isn't 2023. We are comparing 2021 parts because it's 2021. Right now Intel is 3 years behind as their competing 7nm parts won't be available until 2023, 3 years after the competitive and competing 5nm M1 was released.
Disagree isn't even the point. You're speculating on a part that doesn't exist yet. It could be 2024, making Intel 4 years behind, for example.
As for pleasure, yeah, I enjoy the technical details and I'm technically right. Until Intel ships they are behind. How far behind? We both agree 2023 is a reasonable target, and when that occurs we can compare which technology stack is most similar. Of course, 2023 is also the target date for TSMC's 3nm node, which would mean Intel won't have caught up even then because the 3nm node is ever so slightly more dense than Intel's 7nm, though at least it is far more competitive than comparing Intel 14nm to TSMC 10nm, or Intel 10nm to TSMC 7nm
Spunjji - Friday, May 7, 2021 - link
There's a lot of special pleading involved here that, on closer inspection, doesn't make sense.Your insistence on only counting a node as /really/ launching when it supports high-powered chip production is pretty arbitrary, and penalises TSMC for its partners' decisions about when to move to the newest processes. By the same token it favours Intel, who have every incentive to start pushing designs on their latest processes even when they're not performing or yielding very well (e.g. Ice Lake on 10nm+), because they are their own biggest customer.
Let's look at like-for-like. If you're counting Intel's 10nm as having been online since Ice Lake launched in September 2019 (as Intel do - RIP Cannon Lake) then by those same standards TSMC 5nm has been online since November 2020. The numbers:
Ice Lake on Intel's 10nm+ is ~122.52 mm² at a ~15-28W TDP.
M1 on TSMC N5 is ~120.5 mm² at a ~10-25W TDP.
On the other hand, if the benchmark for a process coming online is volume production of large / high power dies, then Intel 10nm+ only actually came online with Ice Lake SP in April 2021, starting at 370mm² with the LCC die. 10nm+ is arguably inferior to TSMC N7, and AMD launched Vega VII at 330mm² on N7 back in February 2019 - by your "big die" standard, that puts Intel around 2 years and 2 months behind TSMC on the current most relevant nodes. That's a fair bit of catching up to do.
If Intel 7nm arrives in 2023, and if it is roughly a half node ahead of TSMC 5nm (I'd expect that it will be), that's still arriving roughly a year behind TSMC's N3 and 18 months behind their N4 which ought to be roughly comparable (unless N4 sucks and 7nm rocks, which is possible!).
So: if Intel and TSMC hit their targets, Apple keep executing early on TSMC's new nodes, and Intel launch their new process with U-class chips, then on a like-for-like basis Intel will still be roughly 18 months behind TSMC when 7nm launches.
TL;DR: I don't agree with your thesis that Intel are catching up as much as you say, because you've cooked the books on the comparison between nodes by moving the goalposts on what you're comparing.
Exotica - Thursday, May 6, 2021 - link
Intel’s 10nm transistor density is looking quite impressive compared to TSMC and Samsung 7nm.duploxxx - Thursday, May 6, 2021 - link
you can call it impressive, but if it ain't scaling performance wise and quality wise than what is the added value?FreckledTrout - Thursday, May 6, 2021 - link
Oh it is very impressive. That however was part of the issue scaling to high power chips. Intel simply pushed things to far. They have had to loosen those densities up for high power 10nm chips and introduce some extra tricks like SuperFin.movax2 - Thursday, May 6, 2021 - link
Yeah, intel 10nm++(+) is so impressive than even Rocket-Lake was still 14nm+++++.And Alder-Lake 10nm+++(+) will still have 8 big cores comparing to Zen3 16 cores.
Yeah , very "impressive"
name99 - Thursday, May 6, 2021 - link
Impressive --- and irrelevant. Intel does not make any device even CLOSE to those limits. Which makes you wonder WTF they bothered to try to reach them.The best they hit right now is ~50MTr/mm^2
https://www.anandtech.com/show/15877/intel-hybrid-...
Will Xe be better? Who knows? The rough guesses we can make from the iGPUs on existing Intel chips certainly don't suggest that Intel's GPUs run at substantially higher density that the CPUs.
So -- kill your process so you can boast of >100MTr/mm^2 -- then ship devices that only exploit half that value? Still unclear to me quite what the strategy behind that is...
(FWIW for 7nm we have multiple vendors confirming then hit >90% of TSMC's promised density.
For 5nm the situation is unclear.
- The Apple results are (IMHO) meaningless because A14/M1 were clearly rushed in the sense that the ONLY priority was getting the x86/mac stuff working. The core that's not relevant to that is barely altered, the GPU is barely altered. I don't expect much effort at all was put into physical optimization. I don't think we'll have "reasonable" Apple results till at least the A15/M2.
- Huawei only produced a few chips on 5nm before US Govt forced them off the process. I have seen lots of claims about the Huawei density, but they all strike me as BS, as repeating the baseline TSMC 5nm density. Not a single independent measurement or something equivalent.
- We have no QC or anyone else on TSMC 5nm yet
So if someone tells you they know what achievable TSMC 5nm density is [or associated results, like the claim of *substantially* worse SRAM scaling] treat them as charlatans. So far this info is simply not public; all that is public is a lot of loud voices and ill-informed speculation.)
Spunjji - Friday, May 7, 2021 - link
I will probably die mad about the constant quoting of the 100MTr/mm^2 number 😅Kuhar - Friday, May 7, 2021 - link
It is impressive indeed but i guess you missed the word "peak" in the article. It is the peak density and quite nicely explained what it means.FunBunny2 - Thursday, May 6, 2021 - link
of most interest: how much of the production machinery is bespoke by IBM? or do they use the same ASML, et al commodity machines? IOW, is IBM really all that far ahead of the curve?Arsenica - Thursday, May 6, 2021 - link
They use pretty much the same equipment as everyone else.For EUV the Albany campus had one-off machines like a custom Micro Exposure Tool and the first Alpha Demo Tool from ASML, but right now they are using the NXE3400 from ASML.
The smallest X-Y dimension here is the 12 nm gate-length that was likely made using the NXE3400's 13 nm resolution plus some "resolution enhancement" via etching
forextor - Thursday, May 6, 2021 - link
I wonder how small my 1.44" floppy disk drive would be (or how much data can it hold) if it is using this technology.Tomatotech - Thursday, May 6, 2021 - link
"Smaller than your fingernail ..."Spunjji - Friday, May 7, 2021 - link
You can currently get 1TB Micro SD cards that are a similar size to most people's fingernails. That's a more valid comparison - this process couldn't be used to make non-volatile storage,storapa - Friday, May 7, 2021 - link
That's a trick question! My answer is: 1.44" (or maybe 3.5" assuming you meant 1440KiB capacity floppy drives).Peskarik - Thursday, May 6, 2021 - link
I have 5900X lying at home, unopened.According to all the reviews - amazing processor, fast and energy efficient.
Then one starts to read user experience - WHEA Errors, constant reboots, BSODs.
One has to tinker for hours, days, months to get a Zen3 system stable.
The AMD QC seems to be absolute garbage, push as many cpus out as possible, RMA the bad ones, and the user is the unpaid beta tester.
My i7-2600K runs flawless since 10 years, on the other hand. I never had to tweak or troubleshoot anything, and I am a complete build-and-forget novice.
Intel has failed me. I do not want AMD, I want Intel, but I do not want slow and extremely hot chip.
It is sad.
Machinus - Thursday, May 6, 2021 - link
My 5950x worked perfectly out of the box. Sell me your 5900,Peskarik - Saturday, May 8, 2021 - link
Decided to take my chances. :-)Will build up my first AMD system now.
jsz - Thursday, May 6, 2021 - link
3900x here. 100% stable in a critical work environment granted I am using ECC ram.Pretty sure a lot of these AMD "issues" involve unstable IMC's and RAM being pushed higher than it should. I know a lot of people want to run DDR4 3600 due to infinity fabric performance, but I think things like disconnect issues and what not stem from the IMC not being stable enough per sample basis.
AMD claims DDR4 3200(SR)/2993(DR) is supported, but they make no note of JEDEC or otherwise.
Intel has been much more conservative with official DDR4 specs even though they have a better memory controller, but it makes sense from this perspective.
Oxford Guy - Thursday, May 6, 2021 - link
'even though they have a better memory controller'Do they? I know that was true in the past but AMD is now on the third iteration of Zen.
jsz - Thursday, May 6, 2021 - link
Ryzen 3000/5000 cant really clock past 1900 FCLK and even this is potentially rare without overriding the voltage on some chips. Most seem to peak around 1800 FCLK, but I would expect some people to have instability. The 2700X I tested prior to my 3900x wouldn't even do 3200 with B-die ram. Went back to 7700k until 3000 series was released.. Glad I waited since the core count helps work flow.Current Rocket lake pushes further with a 1:1 memory clock setting relative to Ryzen 3000/5000 and Skylake IMC on late 10th is technically superior to both.. at least in terms of overall latency. Rocket lake is a little more stable past 4400mhz.
the_eraser1 - Thursday, May 6, 2021 - link
You conflate the IMC with overall memory system.Yes, Comet Lake has better memory latency, but that has to do with its monolithic and more integrated architecture. Same for Rocket Lake, which *does* feature a better IMC, but actually does not go further in 1:1 mode; most RKL IMCs have trouble pushing past 3200, with 3600 being quite rare. Ryzen 3000 series very commonly pushes 3600, and 5000 series reaches 1900 quite easily, with some even reaching 2000.
However, this is moot as the gear ratios between the two architectures are substantially different. The fact remains that 3000 and 5000 series can fairly easily support memory speeds in excess of 5000 MT/s; the gearing ratio is largely independent of the actual IMC and has more to do with infinity fabric limits.
Also, if you look at the monolithic designs for Ryzen, you will find that (until RKL), Renoir was the king of memory overclocking.
Of course, Intel has effectively retaken that crown with RKL, as its gearing ratio has a smaller impact on performance than AMD, and can still reach incredible speeds with excellent timings, edging out even R5000 series in that regard.
jsz - Thursday, May 6, 2021 - link
I suppose they just trade off in different areas and my mistake as I do not own and never used a RKL CPU. Just see a lot of different things going on with the chip.We can agree that SKL and the revised CML variation is sort of the king when it comes to overall latency between high clocked memory and its controller (intel ring). RKL seems to generally go higher due to offset gearing and better PCB quality (Layer count and better memory tracing on later boards)
I didn't know rocket lake struggled on 1:1 as I've seen some chips do 2000mhz memory clock but that might be one off results. I know theres a lot of hwbot records being broken with geardown which is why I assumed. Does make sense though.. 11900K was originally spec'd as the only chip that had an official 3200 1:1 spec (2933 for everything else), but I guess they updated marketing/product pages later on. Perhaps microcode updates boosted internal voltage? Not sure.
From what I understand about Ryzen, is that the I/O Die for both 3000 and 5000 is the same but global foundries should be getting better consistency with chips over time. AMD claimed the 5000 IMC can do up to 2000 FCLK 1:1 but no one seems to be able to push it over 1900, at least consistently enough for daily use.
Ryzen still has a larger latency penalty relative to Both Skylake and Rocketlake regardless of gearing which is unfortunate, but 5000 improves it by 10 or so ns due to the more monolithic 8 core die per chiplet.
And yes I agree, Sweet spot for Ryzen seems to be high clocked 3600-3800 ram in 1:1 mode due to IF, but I do think people might not realize certain instabilities of the I/O die resulting in WHEA errors assuming bad luck with the silicon lottery.
Peskarik - Thursday, May 6, 2021 - link
so you suggest running at 3200, do you?When I read overclock.net thread (75 pages) that I have linked below, where people have tried everything to get their Ryzen 5000x stable, including stock bios settings for everything (including RAM), I get a different feeling.
Some people have had their chips replaced through RMA, put them into their systems, without any changes between chip changes, and suddenly things worked fine.
jsz - Thursday, May 6, 2021 - link
I just know the I/O die is finnicky and sensitive when running high speed ram, granted, I wouldn't rule out faulty chips.Silver5urfer - Monday, May 10, 2021 - link
More than those WHEA RMA BSODs the bigger issue with X570 is the USB problems on the chipset. It's not fixed with the latest AGESA. People still have that damn issue, fck even Optimum Tech guy mentions that he has a problem with USB on his main rig which is a 5900X and an Nvidia RTX 3090 FE on Custom Loop.That issue is not going to be fixed for sure, my guess AMD fucked up the QC on their chipset and processors and boosted them to max and failed to provide a proper validation on top you don't have any friggin documentation on the AMD processors. ZERO.
Kuhar - Friday, May 7, 2021 - link
I am a happy AMD user aswell. Every day use of machine, regular stuff like surfing, documents and spreadsheets, very little programming and some quite serious gaming and everything work great.When i build my machine i always check EXACTLY what RAM is supported by my motherboard. I guess that can be the reason for problems for many people - they just check memory speed and that is all. Nope, that is not all, unfortunatelly.
Beaver M. - Sunday, May 9, 2021 - link
There are a lot of people who get WHEA errors and crashes stock. They replaced the CPU and it worked. Some had to replace twice or three times before it worked.AMD has issues, but the fanboy force is just too powerful. They will defend everything.
Remember when the USB issues (which had been going on for years) made the big news. All of the sudden thousands of people spoke up.
IDK what it is with AMD fanboyism, but its not good for AMD.
Qasar - Monday, May 10, 2021 - link
and the intel fanboy force is just as bad, intel has had their own issues over the years.shabby - Thursday, May 6, 2021 - link
4th word is the answer.Peskarik - Thursday, May 6, 2021 - link
In which sense am I lying?Is this a lie:
https://community.amd.com/t5/processors/ryzen-5900...
https://www.overclock.net/threads/replaced-3950x-w...
Or you are telling me I do not have BG 2110PGS , 100-100000061WOF lying in front of me as I type this?
Qasar - Thursday, May 6, 2021 - link
like machinus said, ill buy that cpu from you.Peskarik - Thursday, May 6, 2021 - link
Too much hassle. I still have 3 weeks to return it to the shop. I am not decided yet if I want to take my chances on it being one of the problematic ones or not.the_eraser1 - Thursday, May 6, 2021 - link
I have purchased a 5600X, 2 of 5800X, a 5900X, and a 5950X. All of them have worked out of the box, and with particularly taxing 4-stick (dual rank) Samsung B Die that I have overclocked to 3733 14-15-14.There are bad samples, yes. But that applies to anything.
Spunjji - Friday, May 7, 2021 - link
"No, you can't meet my girlfriend, she lives in Canada"Spunjji - Friday, May 7, 2021 - link
In every sense. Your first link is marked SOLVED and the second is a thread and poll that predates AMD's fixes for the issues, and contains dozens of people saying the problems are now resolved for them (or tacitly admitting that they were overclocking when they encountered the issues in the first place).Nice work making sure those links get spread around to as many place as possible though, you're a good little shill.
Peskarik - Saturday, May 8, 2021 - link
If you look at the solution in the first thread, would you call this a solution?I expect a new chip to work at stock settings, and for some people it does not.
I like to tinker, but quite a lot of people do not, they just want their CPUs to work off the bat, I do not think it is too much to ask.
Maybe AMD chips are for enthusiasts, who like to spend days, weeks, or months trying to "stabilize" their systems by changing all kinds of BIOS settings and exchanging everything in their hardware but CPU. I am not one of these, I do not have MBs, different RAMs, PSUs, graphics cards etc lying around.
But I will take my chances on my 5900 now. If I get BSODs and WHEAs in stock BIOS settings I will RMA it immediately.
You have mental problem, quite obviously.
I actually read all 75 pages of that thread so I know what people done and whether they overclocked or not.
You did not, but you assumed things, and called me a shill. :-D
Spunji you are a pathetic nobody. :-D
Spunjji - Tuesday, May 18, 2021 - link
"You have mental problem, quite obviously."Yes, obviously. You are qualified to diagnose this and have definitely had sufficient interactions with me to enable you to do so.
"Spunji you are a pathetic nobody. :-D"
Aren't we all?
Spunjji - Friday, May 7, 2021 - link
Oh boy, it's another "random" commenter who just happened to wonder into a totally unrelated article and whine about AMD bugs. It must be a day ending in a Y.You're claiming to have bought a $550 CPU and then left it lying around without even trying it because of stuff you read online. The options here are that you're a fool, a liar, or both.
Peskarik - Saturday, May 8, 2021 - link
As soon as I open the box I have to go through a return process, if I do not open the box I can return it and get cash back immediately. I know this is hard to understand for you, that some people gather info before they start on a project.Yes, I bought the CPU because I got the chance, they are hard to come by otherwise.
Also, my time is valuable, and I do not want to spend it on "stabilizing" systems. But I will take a leap of faith now and build AMD system, maybe I get lucky and have no WHEA/BSOD/reboots.
Now, sod off.
Beaver M. - Sunday, May 9, 2021 - link
Many people reporting issues coming up after months of running stable, though. Without ever changing anything.Thats ultimately why I decided against it. I am like you. I build and forget for 5 to 6 years. If crap like that turns up makes me mad.
I got warned, I took the warning. Built a transition system now. Not nearly as powerful as the 5950x I planned to buy, but at least its super stable. I guess Ill wait for Alder Lake, or AMD to fix their issues...
Spunjji - Tuesday, May 18, 2021 - link
"I know this is hard to understand for you, that some people gather info before they start on a project."But you're saying you did the research *after* you started on the project...
"Also, my time is valuable, and I do not want to spend it on "stabilizing" systems."
But you're happy to spend it buying things you haven't researched, reading 75-page threads about them before building a system, leaving something you bought in the box, *posting about it on Anandtech* and then flinging insults at me?
Yeah, this all seems super smart and sensible, how dare I question your genius I guess.
Beaver M. - Sunday, May 9, 2021 - link
What is so hard to believe? I was almost in the same position. I would have bought the CPU first (since they were so hard to get) and then get mainboard and the rest.But I read about those issues shortly before I bought. Decided against it after that.
If I had the CPU already here, I would have left it unopened too, instead of wasting more money with a mainboard (and regrettably RAM - which has to be selected specifically with AMD in mind).
Spunjji - Tuesday, May 18, 2021 - link
Why is it so hard to believe this first poster claims to be cautious enough not to build a system because they read a thread, but not cautious enough to read the thread before buying the CPU, and has insufficient time for testing systems but plenty of time to post about systems they haven't built on Anandtech? I dunno really, you tell me. Glad they have you to back them up though, a totally independent account who just happens to do the exact same things in these comment sections.andrewaggb - Friday, May 7, 2021 - link
I don't see how you can say your 5900x is unstable if it's unopened.Peskarik - Saturday, May 8, 2021 - link
I did not say that. I said there is a probability given what I read in different forums. I decided to take my chances and build an AMD system now, but that's primarily because current Intel chips are way behind AMD in performance and way too hot, otherwise I would use Intel as I had good experience with them.Linustechtips12#6900xt - Monday, May 10, 2021 - link
i havent had any issues with zen3, it was one of the easist transition honestly. b450m pro 4 bios update then i jsut plopped it in and dne easy as thatSpunjji - Tuesday, May 18, 2021 - link
Alas, the 75 page thread empirically proves you wrong. 🤭Zingam - Thursday, May 6, 2021 - link
If Intel is so much denser why don't they just lower their number as is common in IT industry (well, they usually up their number for a spelling change - Google Chrome 9765778).Oxford Guy - Thursday, May 6, 2021 - link
Firefox was behind Chrome's ultra-fast version number system so Mozilla suddenly inflated the version number. Now, as far as I know, Google is the #1 source of funding for Mozilla.Perhaps there is something to be gleaned from that anecdote.
michael2k - Thursday, May 6, 2021 - link
Intel's 14nm is roughly equivalent to TSMC's 10nm, and Intel's 10nm is roughly equivalent to TSMC's 7nm. It isn't the naming that is the problem.The problem is that Intel 14nm shipped in 2014 with Broadwell and is still shipping in Cypress Cove in 2021!
Intel 10nm shipped with Palm Cove in 2018, but that was discontinued and replaced by Sunny Cove, then Willow Cove, and now Golden Cove this year.
To put that in comparison, Apple shipped the 10nm A11 in 2017, 3 years after Intel had already been shipping 14nm parts. Apple moved to 7nm in 2018, the same year Intel's first 10nm part shipped, but due to internal delays, Intel couldn't actually transition all their products to 10nm; coupled with Apple's architectural designs, resulting in the A12 being thoroughly competitive with Intel in 2018. In 2020 Apple was able to release the A14 at 5nm, and alongside more architectural changes was thoroughly trouncing Intel (see the M1)
So changing the numbers in the name don't help Intel leapfrog any, their process is still 3 years behind. Intel 7nm is on track for a 2023 release, finally matching and beating TSMC's 2020 5nm release.
And of course, TSMC expects to theoretically beat Intel with 3nm in 2022. That assumes no delays on anyone's part.
dwisehart - Thursday, May 6, 2021 - link
TSMC did and is doing shuttle runs of their 4nm process in Mar 2021 and Aug 2021. They also have a shuttle run of their 3nm process in Aug 2021. Shuttle runs are wafers made for multiple customers who each buy a portion of run, with wafers shared among all of the customers. For the 5nm shuttle runs, it is currently taking nearly half a year to get chips back, so the 4nm and 3nm shuttle runs probably take that long or longer.This is all just a way of saying that TSMC 4nm and 3nm parts are in process, but these things take time to deliver.
mmusto - Thursday, May 6, 2021 - link
Let me know when you're in Albany!Arsenica - Thursday, May 6, 2021 - link
Go Steamed Clams!Arsenica - Thursday, May 6, 2021 - link
Also Ian: ask them to let you bite one of the 450mm wafers they have gathering dust over there.Oxford Guy - Thursday, May 6, 2021 - link
'nothing about transistor dimensions resembles a traditional expectation of what 2nm might be.'Thank you for pointing this out to readers. As someone who values accuracy in terminology more than marketing emotion, it's nice to see someone state the facts rather than just the emotional appeal from marketing departments.
Perhaps putting quotes around 2nm in the headline is a good idea.
WaltC - Thursday, May 6, 2021 - link
If you know nothing about instruction capability and processing power, circuit design & complexity, then you don't know anything worth knowing about the "2nm chip." Reminds me of a university study I read years ago about this college that designed and manufactured a 1,000,000 MHz chip back when CPUs were clocking at hundreds of MHz. The catch? It did exactly one instruction per clock...;) Which actually made it fairly slow at the time. I also remember when Intel was advertising that it was using 90nm in production at a time when everyone was stuck at 130nm...;) The catch? Intel used it to manufacture ram--but CPUs @ 90nm were a year or two away. There's always a catch...;)sweetgoals - Thursday, May 6, 2021 - link
Just because you are first doesn't mean you'll be the best. Sucks to be IBM they don't have any manufacturing capability. The only money they can make off this is the licensing deals, but does Samsung or TMSC really need it? I would say not. To take any advantage IBM would need to get these designs into someone's chip software and manufacturing. So the reality is that the only thing this is good for is "Hey, look at us! We cool!" While in reality they suck.iphonebestgamephone - Thursday, May 6, 2021 - link
Probably not as much as youFunBunny2 - Friday, May 7, 2021 - link
"Sucks to be IBM they don't have any manufacturing capability."but... isn't that exactly the same place Apple is?
in general, all of this discussion amounts to what Gates said upwards of 40 years ago: 'Windows is slow? let the hardware fix it.' how much of 'innovation' is different from 'widen this' and 'lengthen that'? it's all just throwing more transistors at the problem. in the political world, that's just "they're just throwing money at the problem, not fixing it." of course, if you're getting the money (transistors) you're happy. sometimes the only tool you have is a sledge.
Oxford Guy - Friday, May 7, 2021 - link
In politics, fixing it means getting the fix made and in.Spunjji - Friday, May 7, 2021 - link
"The only money they can make off this is the licensing deals, but does Samsung or TMSC really need it? I would say not."Are you Samsung or TSMC? If not, why does it matter much what you say?
0ldman79 - Thursday, May 6, 2021 - link
Keep in mind these are peak numbers, not average or worst case.Frankly I don't believe there is ever a point where the transistors are as dense as Intel claims.
Intel gave out transistor count in the past when a CPU was released, they quit doing that and I think the reason why is they're making claims that they can't back up.
Intel's 14nm is not twice as dense as TSMC's 14nm on average. Their SRAM density is pretty close on all companies from 14nm down to 7nm and that's the densest part of the chip.
What are they going by to say they're twice as dense as their competitors on the same process when SRAM density is generally within 20%, even across multiple lithographies?
Smell This - Friday, May 7, 2021 - link
I remember that article from AT __ something like design *structural vs functional* densities? I don't recall if it incorporated transistor 'cell libraries' (but there was another article at about the same time concerning dense cell libraries on AMD Excavator __ maybe 'short cells' for uncore/graphics ?) ...
eastcoast_pete - Thursday, May 6, 2021 - link
Since Intel is apparently going to fab some of IBM's silicon, I wonder if this tech will become part of a Blue/Big Blue partnership.JoeDuarte - Thursday, May 6, 2021 - link
This isn't real. They can't produce any actual processors using this 2nm node, nor can anyone else. IBM frequently touts dramatic technological advances like this, but they never materialize as real products humans get to use. I've lost track of all their memory and storage breakthroughs, and Watson turned out to be a dud too. They're the "battery breakthrough" company of the semiconductor world – endless announcements from cloistered labs, never any products.All of IBM's partners are the B-team right now, just a list of underperforming companies who haven't had any recent successes. Partnering with Intel will get them exactly nowhere. For reasons I don't understand, Samsung can't keep up with TSMC, and can't even design SoCs that are half as good as Apple's or 90% as good as Qualcomm. It's strange.
The purported 45% performance boost over 7nm is pretty low given that this is three generations or shrinks later. Two consecutive 20% improvements in performance, two shrinks, gives you a 44% net improvement. So 7nm to 5nm to 3nm should give you that under conservative assumptions. If going from 3nm to 2nm offers no improvement at all, well that's not a win. It's strange that they're claiming a true density improvement over 3nm processes, but performance is actually zero improvement. And that's going with their marketing numbers, so best case... And that's assuming this is a real process node that will exist in our world, which it certainly will not.
Spunjji - Friday, May 7, 2021 - link
"They can't produce any actual processors using this 2nm node"They don't intend to, either. This is a tech demo to build their patent portfolio that they'll share with partners. The partners may or may not use the tech in their final processes. You'll have no idea either way, so it's not clear how you're so certain that this has never happened before?
"For reasons I don't understand, Samsung can't keep up with TSMC"
Semiconductor manufacturing is *really hard*. That's it.
Alistair - Thursday, May 6, 2021 - link
Wow a lot of crazy comments in here. Was just reading from Anand's chart that TSMC's 5nm is shipping for almost a year now, and already is almost tied to where Intel is trying to be 3 years from now. Not trying to start a flame war.I do find it hilarious someone said "TSMC" has low volume, haha, that's a good joke. Just because it is hard to buy doesn't mean supply is limited, the demand is incredible. Apple is making all their Macs, and iPhones, and iPads, all on 5nm now. That is not low volume. And M1 is not a "small" chip at all.
Spunjji - Friday, May 7, 2021 - link
People have opinions, and like to bend facts to match them.aperson2437 - Friday, May 7, 2021 - link
Globalfoundries should get busy building a 2 nm fab in order to start manufacturing these. I want to see them catch up to TSMC. Easier said than done though I'm sure.Anymoore - Saturday, May 8, 2021 - link
From the photo, the die size looks pretty big, ~ 800 mm2 maybe? Then the transistor density is ~62.5 MTr/mm2.The nanosheets are quite wide, going up to 70 nm. I think these are coarser pitch than Fins, maybe even comparable to 22 nm active area pitch, so the EUV advantage is not clear over here. The usual LELE double patterning would still work.
The point of nanosheets was not to increase density but to allow gate pitch to shrink, but it seems that did not happen (44 nm).
Santoval - Sunday, May 9, 2021 - link
"It’s worth noting that these density numbers are often listed as peak densities, for transistor libraries where die area is the peak concern, rather than frequency scaling – often the fastest parts of a processor are half as dense as these numbers due to power and thermal concerns."This bit is very important, since most people are unaware that the listed transistor densities of fabs are just the "peak densities" for non logic parts of dies which provide the highest density and energy efficiency but the lowest performance. For instance Intel has no less than three cell libraries at 10nm, ranging from I believe ~55 million to ~100 million transistors per sq. mm. They only broadly advertise the highest density library, which is barely used, and probably not used at all for S-series desktop parts. I strongly doubt the highest density library of TSMC's 7nm process node is even used for the high performance "big" cores of mobile phone ARM processors. It might or might not be employed on the small cores which are clocked up to 2 GHz tops.
As for your table with the projected peak transistor densities I thought Intel said they were going to be more conservative with the scaling of their 7nm node and "only" target a x2 density over their 10nm node. That would place the peak density of their 7nm node at ~200 million transistors per mm^2. ~237 million transistors is a scaling of x2.37, not x2. I think wikichip calculated Intel's peak density at 7nm based on their previous x2.35 - x2.40 scaling (from 14nm to 10nm), not on their new more conservative target.