One of the three senior architects of the P6 was Bob Colwell. He wrote this about the other two:
"I can't imagine a team that would be unable to get along with somebody like Glenn Hinton. Glenn is just a great guy to be around. I think David Papworth is too. For somebody at that level, to not have an ego problem is remarkable and those guys don't. It's not that they don't have an ego. They know they're good at it but they don't use that as a stick over anyone else's head. No “shut up, I'm the king". It doesn't happen. So it was really a blast to work with those guys."
The source of that quote is an "Oral History of Robert P. Colwell" PDF, a transcript of an interview with him. I wanted to post a link, but the comment system thought that was spam.
Pity. It's a great and extremely illuminating read, with some fascinating insights into Intel history.
Good grief. No kidding. I'll save this for tonight. A bit humorous that on a random page I flipped to he's discussing how great Rani Borkar was. And it's true. Of course BK chased her away and she's now at Microsoft recruiting whatever talent remains in Hillsboro.
I would've thought you were joking about Rani recruiting whatever talent remains in Hillsboro if I didn't look at LinkedIn connections. Left a while back but goodness, you're right! Many of the so-called design kingmakers from JF has either gone to Microsoft, Apple, or Ampere.
I just spent all afternoon reading that oral history. I haven't had that much fun in a long time! He believes decisions should be data-driven, and that you can't claim that things work, if you haven't tested them. He has ethics, and believes you shouldn't lie to people (who may not know the difference anyway) simply because you're trying to make a point you think is justified. An he's been caught in the crossfire of both academic and corporate politics, but he went around (and above) the roadblocks. It is such a pleasure to read the ruminations of such a brilliant engineer, and all-round interesting guy.
that is not necessarily the end of it. Company loyalists won’t move at all. However, once you switch companies it gets easier to do it again. Not unlike murder.
I continue to be perplexed with this Apple fawning, ARM too for that matter. After centuries of maths and 80-ish years of computing machines, the notion that there are tectonic changes to computing, previously unknown, just waiting for some smart young kiddo to find? Balderdash. The Von Neumann machine still reigns. RISC owns the machine, although buried ever deeper below the 'ol same 'ol ISAs. I'll bet the only difference among all microprocessors within the actual computation engines is syntax/mnemonics. They all do the same maths.
No one, to my knowledge, has figured out how to parallelize single-threaded user space problems on the fly, on the metal. I'd wager that 99.44% of 'innovation' in cpu over the last 3 decades has been three efforts: - smaller transistors - from that, hiding the real machine from the compiler, as above - from that, ever more concentration of function into the 'cpu' chip that isn't computational
or to be brutal, has anyone devised a new ALU, ever? register width doesn't count.
so, it seems that most design these days amounts to deciding how to allocate the burgeoning of transistors (Apple seems to like expanding buffers and caches) and deciding what functions to assemble on the chip. which is not to say that Forrest Gump could do a good job
IOW, what new 'innovations' have been discovered in the fundamental computation process? I'll skip quantum computing, as it's, so far, been found irrelevant to all but a teeny, tiny niche of possible problems.
In the grand scheme of things you are absolutely correct. We are still in the Von Neumann - Moore’s law level. Two observations.
1. I think quantum computing is not to be discarded just that easily. It applies at the moment to some specific NP-problems but they are not trivial (encryption breaks) and it might apply to other areas as it evolves. It is too early to say ....
2. The Von Neumann basic architecture of two level storage -volatile and permanent- is I think going to be converged to one level storage permanent storage at the speeds of currently volatile storage.
Intel has given their Client 2.0 presentation ... stitching and stacking chiplets. They also taped out a stacked SRAM, built with hybrid bonding last year. They also are introducing CXL into the server CPUs and GPUs this year. They also demoed co-packaged photonics last year. The also shipped their first foveros 3d chip design last year.
All these seem to enable new paths for chip designs, including architectures.
I could see CPU cores turning into accelerators with large, biased private caches, for example, as being a natural extension of the CXL XPU designs that are being conceived for ai/hpc processing.
Neural network hardware is not intrinsically Von Neumann, though it can be implemented that way.
I'm not familiar enough with graph analytics processors to say whether they potentially break Von Neumann, as well.
FPGAs are also not intrinsically Von Neumann, though can obviously be used that way.
And what do people think about transport-triggered architectures? Fundamentally asych computing strikes me as fairly non-Von Neumann.
For the sake of completeness, other non-Von Neumann architectures that come to mind are analog and quantum. Analog has some potential for neural computing. I think Intel's Ni1000 was analog?
Anyway, it's always hard for a new technology to usurp an old one. Just look at how long it took for NAND flash to overtake HDDs! You could see it coming for decades, but HDDs just kept improving fast enough to stay ahead of it for quite a while. In a similar way, Dennard scaling enabled Von Neumann architectures to evolve rapidly enough to keep from being overtaken, and software compatibility provided a big enough hurdle that nothing else was able to mount a serious threat. However, as manufacturing tech runs out of steam, perhaps the industry will finally be driven to revisit some of the more fringe computer architecture ideas that've been left by the wayside.
Because in this case the old hands are genuinely good at this. Microprocessor design is not a field where skills rapidly expire. Fresh blood, by contrast, has no proven track record and will likely have to spend time learning what works, from ... the old hands.
Apple's CPU design team also eked out a good degree of their performance by making design compromises that wouldn't be acceptable in the x86 market. Notably, system RAM is integrated into the CPU package. This greatly boosts performance, but also greatly limits capacity and completely negates upgradability. Intel knows about this, and started pulling cache into the processor with the 486, but they can't do the same for main memory. The x86 market wants their DIMM slots, wants to be able to take one CPU and pair it with arbitrary amounts of RAM(where arbitrary<256TB, anyways), so that is a major performance hack that is immediately off the table.
"Notably, system RAM is integrated into the CPU package."
from an RDBMS point of view, likely any transaction, having a true 'single level store' makes ACID come out in the wash, and negates all other store methods. Optane is a step in that direction. this will require 'new' ways to manage transactions, in that currently RDBMS (as an example) will write to some log first (usually, but not necessarily) then to the database. whether such a two-step transactional protocol is still required for a memory-only storage? belt and suspenders?
> Notably, system RAM is integrated into the CPU package. This greatly boosts performance, but also greatly limits capacity and completely negates upgradability.
Use HBM2 as L4 cache and 3D XPoint for expandability. Software can even treat the HBM2 as system RAM and swap to Optane DIMMs.
Why would team membersnot be proud of the Pentium 4, or Bulldozer for that matter?
Those failures were not because of incompetent designers and engineers who just didn’t know what they were doing. They were simply bets that were made at the company level. The staff to be done with a finite amount of resources, a finite amount of money, a finite amount of time, and particular product targets - all if which affect cgances of success.
Nearly every designer and all of those teams could also work on other teams. Not that there aren’t some who are better than others, but they all can work on successful architectures. Just as they can all work on failures, and probably have.
Pentium 4 and Bulldozer required just as much intelligence, imagination, and work ethic as the M1. In the quest for technical leadership, bets like these have to be made. There are no guarantees when you go in.
Bulldozer was a bet that GCN would both reach maturity sooner, and be flexible enough to realistically take over floating point compute, while said GCN products had no good compute API (no, OpenCL does not count as "good").
That's a company failure for sure. It was also a manufacturing failure -- people act like Intel's struggles in manufacturing are unique to it, but AMD was stuck at 32nm/28nm for about as long as Intel has been stuck at 14nm.
P4 micro-op cache was revolutionary, but not yet ready for prime time. Also it was Intel's first SMT architecture! I'd argue the features Intel developed for P4 were essential, but hindered by the mistake of a long pipeline and less-accurate branch prediction.
It's possible the P4 would've gone on a bit more if Northwood had been widened and its stages cut down. But Intel was still under the deep-pipeline/MHz delusion back then, which led to Prescott, whose 31 stages were supposed to usher in 10 GHz. Today's CPUs---Sandy Bridge and upwards, and Zen---have up to 19 stages, pretty close to the P4's 20. The difference is they're much wider, among other things (bigger caches, better branch prediction,* effective micro-op cache, etc.).
* In that era, the Pentium 4's branch prediction was superior to the K8's, but the latter wasn't being handicapped by a lengthy pipeline. Prescott improved on this further, adding the Pentium M's indirect prediction. But all that couldn't overcome the deep pipeline.
Wasn't Prescott forced to deepen its pipelines in order to cope with 64-bit (which ended up not really being enabled until the Pentium D)?
By the time Prescott was designed, I think Intel was well aware that P4 would never come close to 10 GHz. Scaling to 10 GHz was just an initial design goal of the NetBurst uArch, and badly underestimated leakage of the target process nodes is ultimately what sabotaged it. If manufacturing had managed to deliver on that front, then the NetBurst uArch could have upheld its part in enabling those frequencies.
I believe it was due to clock speed mainly, more stages allowing each to be simpler and so clock higher. The idea was that Prescott would carry on Willamette and Northwood's philosophy, adding another 11, just like they added 10 to the Pentium III. Any loss in IPC would be offset by frequency. Unfortunately, it reached only 3.8 GHz and took a lot of power to do so. I remember the Pentium Ds felt terribly slow in Windows too, compared to Willamette and Northwood.
As for x64, I reckon it wasn't that difficult to add. Just widening and adding of registers I believe, along with some other changes.
On a side note, people might wonder how could Intel have been so stupid to come up with Prescott. I think it's rather that Prescott's design was laid down long before it became apparent what a blunder Netburst was, with its deep-pipeline/high MHz/low IPC principle.
> I think it's rather that Prescott's design was laid down long before it became apparent what a blunder Netburst was
Maybe they still thought they could get leakage under control, which would've really let it stretch its legs. People have clocked Prescotts above 6 GHz with LN2 cooling, which shows they were still thinking high clockspeeds were a viable option, as it was being designed.
I remember that Cedar Mill (Prescott's last revision) curtailed power quite a bit, or brought down the TDP to 65W. I need to read up about CM. Curious to see what they did. Don't think it was a die shrink.
It was, for sure. I remember reading about one last die shrink and was eager to see how it would stack up against Core 2, when they were on the same process node. IIRC, the results were still pretty disappointing for the P4. However, I didn't pay much/any attention to perf/W, which it sounds like was the main improvement.
> I believe it was due to clock speed mainly, more stages allowing each to be simpler and so clock higher.
It's true that Prescott did clock higher than Northwood.
> As for x64, I reckon it wasn't that difficult to add. Just widening and adding of registers I believe, along with some other changes.
It also adds more registers, which means widening muxes. More importantly, 64-bit arithmetic increases the critical path, because each bit in result is contributed to by the lower-order bits. Therefore, I wonder if they had to reduce the complexity of some pipeline stages, when going to 64-bit, which would have to be compensated for by adding more of them.
Likely, they used every opportunity available to squeeze 31 stages out of Northwood's 20. How much of a hand 64-bit had in that, I can't say, but doubt whether it was a massive role. Looking at the K8, it had only two more stages than K7's 10. And Core, at 14, was roughly the same as the Pentium M.
> doubt whether it was a massive role. Looking at the K8, it had only two more stages than K7's 10. And Core, at 14, was roughly the same as the Pentium M.
If you're not comparing on the same process node, then it doesn't mean much.
The P4's HT was sunk by lack of a good scheme for dealing with cache contention, IIRC. When Nehalem brought it back, I think that was the main addition.
When I first got my P4, I wrote a little benchmark that ran 2 threads each doing some fundamentally serial computation. The result was almost a perfect 2x speedup. Another case it handled well was one thread doing memcpy() while another did complex computation - I think I got like 85% speedup, there.
No doubt that Nehalem being much wider also made the payoff bigger, for HT. These days, I enjoy it quite a lot when compiling code. However, I find it helps very little, in AVX2-heavy workloads.
That's quite a speedup. To this day, I have never tested HT on a Pentium 4. The only ones I had/have access to were a 1.7 GHz Willamette and 2.4 GHz Northwood.
As for AVX2, I reckon it's because those instructions are already filling the FP units to the edge, so there's not much left for a second thread.
> As for AVX2, I reckon it's because those instructions are already filling the FP units to the edge, so there's not much left for a second thread.
Yes, the code is highly-optimized with AVX2 in the hot loops. Since the CPU's AVX pipelines can filled with a single, well-tuned thread, the result wasn't surprising (but noteworthy, none the less).
Another use of SMT to help hide long memory access latencies, but if your access patterns are sufficiently regular, then the prefetcher in modern CPUs can do that even better.
I've got a feeling that even with AVX512 support in Ice and Rocket Lake, AVX/2 code won't show much of a boost, likely because support is being implemented using two 256-bit halves.
By the way, here's an excellent chart I found some years ago. Some useful data on the Pentium 4 as well.
Thanks for the chart. That's interesting. I gather the P6 is Pentium Pro? Than mostly makes sense, but some things are much bigger than I thought, like the number of issue ports... I could swear it was only 2-way superscalar.
It should be. But I'll take a look into this and return with an answer. Not sure how much changed in the Pentium II and III, beyond MMX, SSE, and cache. And yes, I expected it to have 3 issue ports myself.
According to Agner Fog, there are 5 ports, with various execution units, but owing to register renaming being limited to 3 uops earlier on, in most cases you'll be limited to 3 uops (pp. 76, 80).
Also, hyperthreading could deliver real improvements in responsiveness and usability. Remember that these were single-core CPUs (until Pentium D, at least).
Despite setting out on a misguided philosophy, the Pentium 4 was an excellent piece of engineering, Northwood especially. Heck, even Sandy Bridge borrows some things from the P4, depending on how one looks at it. And I'd say similar things about Bulldozer and its engineers. Also, Hinton worked on P6, and if that's not an exceptional credential, I give up.
Your crotchety comment aside, there are plenty of people who enjoy learning about things that existed before their time. I wasn't interested in p6 when it was current but my interest in old architectures has grown over time.
Seriously, he developed the friggin' P6 architecture, and everyone's just "the Pentium 4 is his crowning achievement". Come ON. Pentium 2/3 were absolutely amazing, and the P4's big claim is "it got Intel out of AMD's way for once".
They need to come up with a proper high IPC big core architecture. Enough with this GHz push nonsense.
When a relative newcomer in CPU space, apple, beats your even the latest arch, willow cove/tiger lake, you should realize it's time for some actual engineering effort.
Agreed. Note you need small, efficient, high IPC cores. When a startup designs a server using standard Neoverse N1 cores that achieves 2.5 times the throughput per socket than your most expensive Xeon Platinum, you know it is time to get back to the drawing board.
Intel could get away with being lazy in the server space as Windows was the most widely used server OS, ran only on x86, and Linux was a non-factor. Those days are long gone.
small, efficient, high IPC cores -- pick 2 from those three. W.r.t. apple beating tiger, well, if you can put 4x number of transistor on the same square like intel, then indeed, you can come with some wider design and still be efficient. No wonder apple is the first on 5nm. Yes, I know, I can't compare 5nm TSMC x4 ~= 10nm Intel, but still. In fact it's a wonder stand tiger is that good even under current circumstances. Thanks for the article, it tells also what I've had in mind for some time that intel does have more designs in house, but is just hurt by their inability to put that through manufacturing well. Pity, but such is life, IIRC TSMC had that @28nm too (or some other node)?
This has been covered MULTIPLE times. Intel claims they have 100 MTr/mm^2 with their 10nm. And yet they ship Lakefield logic die with 49 MTr/mm^2... (FWIW Apple hit ~90 MTr/mm^2 on TSMC 7nm which is likewise rated at 100 MTr/mm^2)
It's THEIR choice to use low logic density. They control the CPU design and the process. Why do they make that choice? Well, you explain it to use since you're such an expert and so dismissive of everyone else's explanations.
lol, is that means there is generation misaligment ? Pat can't effecively work with younger engineers ? Seems that he want not really CEO seat, but full control on new CPU design
Having a meaningful contribution outright is next to impossible. Given that Intel's main problem is being 2 generations late in production, a new CEO can't do much except trying to reassure customers it will be worth it to hang out for a few years.
Why dont they rehire the architects they fired in the last 1 yr, they've already got thousands of architects, a few here or there won't change anything.
I'm hoping for the best for Intel, despite my opinions about their business practices over the last few decades. As far as computing has come, and for all the progress that has been made, I still feel like we are technologically stunted, or blocked, in a lot of ways. The cost of developing and manufacturing CPUs is so high that only a handful of companies and individuals can afford to do it, and invest in it.
Everyone in these companies has to basically bide their time. They are all at the beck and call of the higher ups in the individual companies, that are interested in profits, profits, profits.
Even when a breakthrough is made, there is a strategy employed as to how and when to implement the breakthrough, and how quickly or how slowly to roll it out and implement it into actual productts.
From my point of view, nothing is going to spur innovation and growth, outside of serious, meaningful competition, amongst these companies. If one company isn't performing well, or is, for all intents and purposes, a lame duck, then that places their competitors in a position where they can comfortably slow down, and hold back, where they might otherwise have increased their efforts and pushed forward.
We're in 2021, but to me, the technology isn't 2021 technology, the technology is lagging years behind where it COULD be, or where it MIGHT be.
If there is this hidden gem of IPC improvements and other advances that are out there, just waiting to be set free, nothing is going to set it free like competition and genuine enthusiasm, amongst these companies.
you think too highly of the architects and their employers. 15 to 20% IPC gain in a generation is highly non trivial and is only achieved once every few generations. the amount of engineering that is needed per every single % ipc gain across a wide spectrum of workload is more than you think . it is naturally done rev by rev....
I hope they work on something post x86, as ARM pretty much is cleaning up there. Maybe they can work on something with RISC-V or a new architecture (not that weird Itanium crap..)
At this point, ARM is their main competitor, and the only viable challenger I see to it is RISC-V, with a potential 2x improvement in efficiency compared to ARM.
I also think that for Intel to release some RISC-V SoC on latest Atom level performance would at least a bit undermine ARM movement which would be a good thing for them. Just to buy some time...
Make a wave(s). Intel needs (a) improve manufacturing of 10nm/7nm/etc and (b) a little bit brake ARM. RISC-V may be the right weapon to attack from the bottom. In comparison with current RISC-V SoCs, latest Atom cores are fine.
If Android doesn't already support RISC-V, then it's only a matter of time. Linux has already supported it for a few years, now. That means the kernel and toolchain support are already there.
The main problem with Atom cores is Intel's manufacturing node. Tremont is good and Gracemont will be even better.
Atom isn't supposed to compete with ARM's fastest cores, either. It's mostly making a play for the mid-range of efficiency and performance that you find in Chromebooks and on SBCs. Still, it does suffer from the x86 tax.
"Assuming that Glenn is talking about a fresh project within Intel’s R&D ecosystem, it will be 3-5 years before we see the fruits of the labor"
That seems overly optimistic. From slides presented at Stanford by, ... checks notes ..., Glenn Hinton...: Nehalem started in 2003 (with research even earlier) https://web.stanford.edu/class/ee380/Abstracts/100...
and was released at the very end of 2008. (Of course that was back in the day when "release" meant something like "can buy it within a few weeks", not today's "step 17 of a 37 step fan dance before you will actually own one".)
I'm disappointed to see AnandTech stoop to clickbait. The new CEO hasn't arrived at Intel yet (not until next month), so he did not have any direct role in hiring this engineer. As noted in the article itself, the engineer has been in talks with Intel since November, long before the new CEO arrived. Also, the title says "architects" when in fact this is a single architect. These problems also make the asserition that the new CEO is 'making waves' highly inaccurate.
I think it's reasonable to assume though he hasn't technically started yet, that the new ceo isn't passively awaiting that date by doing nothing. Even his hiring itself was a contributing factor in the fellow returning to Intel, as the article also states. I don't think your argument that this is clickbait is reasonable.
This is rather simple: 1.) The engineer was in negotiations long before CEO announcement and arrival 2.) CEO hasn't started working yet, thus had no direct involvement in hire 3.) Architect, not architects 4.) A singular architect is certainly not 'making waves' in a company with more than 50,000 engineers.
* These people talk. It's *quite likely* that both Hinton and Gelsinger knew of each other's intentions. Gelsinger probably would have returned without Hinton, but it wouldn't surprise me at all that Gelsinger returning sealed the deal for Hinton. It also wouldn't surprise me if Gelsinger has put out feelers to other former Intel folk.
* A single architect absolutely does 'make waves'. Keller certainly made waves when he joined Intel. Not sure what his real impact ended up being, but waves were made. Likewise Raja. Hinton has a long history with Intel engineers. He is well known and well respected.
* A big complaint internally at Intel in recent years has been that upper management isn't listening to its technologists. Who knows, this may even be one reason Murthy is no longer there...... There is every reason to believe that Gelsinger will correct that problem, and I'd imagine that factors heavily into Hinton's willingness to return.
Gelsinger mentioned Hinton explicitly in the financial call today as bringing the talent back to Intel. He's also had time to peer into Intel's 7nm data and projections and make some conclusions on it - Feb 15th is more a date for Bob being out of the door than anything else. We're currently in transition, and Gelsinger has had strong words to say already.
Also, Hinton's own Linkedin thread mentions other engineers returning or potentially returning on this news.
> Keller certainly made waves when he joined Intel. Not sure what his real impact ended up being, but waves were made. Likewise Raja.
How do you know? And if you're not sure about the impact, then what do you mean by "waves"? Do you just mean that we heard it being reported? That's somewhat circular reasoning.
Intel certainly should avail itself of the best processor design talent possible, but this isn't the major issue it faces. The major issue it faces is getting its fabs up to speed on the 10nm and 7nm processes. Outsourcing to TSMC, however attractive that might have seemed a year ago, is now being proved to be a chimera by the shortages of AMD products. Intel products that no one can get their hands on aren't going to help it recover in the competition with AMD.
Architect is a licensed professional that holds a bachelor's degree in Architecture. Please avoid appropriating real degrees with high regard for namesakes of lame computer science degree.
Sorry to inform you: licensing groups do not get to hold the entire world hostage for the definitions of words.
Sure, a person may require a license to legally market his services as a "Building architect" to the public, in most jurisdictions. But an expiring license doesn't magically mean that person is no longer an "architect." It just means he's legally restricted from advertising or certifying work that requires that license.
Furthermore, a "processor architect" never needs to be licensed to design processor architectures. Glenn Hinton isn't an architect because of a "lame computer science degree". He's an architect because he not only performed the work of architecting processors, but became a recognized world leader in that field.
If you or anyone else can't handle someone legitimately being called an architect because you're upset that it's "appropriating real degrees with high regard" then you're in for a lifetime of disappointment outside the ivory towers of your fellow degree snobs.
I can legally advertise myself as a software engineer, precisely because there's no certification required in my state for that job title. Same for computer architect.
Architects design architecture. CPU architecture is an accepted term. Therefore, CPU architects exist, regardless of what building architects want to believe.
I hope for Intel's sake they do not try and resurrect Itanium. Bringing old hands out of retirement is certainly a mark of desperation. Let's hope they have some new ideas--finally--now that AMD has once again started a fire underneath the Intel derrière...;) Rehashing 14nm ancient architectures won't carry them very long from nown, however. Monopolistic thinking and management put Intel where it is today in reference to AMD. It's difficult to teach old dogs new tricks--we'll see how Intel handles being second fiddle. I have zero sympathy for Intel--none at all. OTOH, I have great admiration for AMD--a company of engineers versus the Intel saga of empty suits and bean counters perpetually running the show. The days of having no competitors because Intel ran them out of business are behind Intel now and will never come again--now we'll see what stuff the company is made of--if anything.
I believe the argument is "lol old people made old processorz like itanium". And they don't actually register the Pentium 4 itself as a fiasco, so they reached for it's dearly-departed sister chip.
Assuming they're eventually going to get beyond x86, why do you care what it is? IA64's biggest problems were that it was never out-of-order (though it could've been) and never got imbued with SIMD instructions. Those are both fixable problems and IA64 probably has the broadest software support after ARM, so it makes a lot of sense.
I think that by moving data-dependency analysis out of the hardware, IA64 has a real chance to be more efficient and perhaps even faster than ARM or RISC-V. It just needs a proper implementation, which Intel never did. They burned their entire transistor budget on making it as wide as possible, and by the time they could possibly revisit the decision not to go out-of-order, management had already lost interest.
I see a lot of comments like these, worshipping RISC as if it's automagically the ideal ISA philosophy for all situations. This despite decades of research have conclusively proven.... "it depends." ARM is great, ARM is popular, but it's only 'the future' until another superior approach is validated.
The Gracemont cores in Alder Lake appear to be a reply to the small ARM cores in the M1.
I've read that the x86 decode is all that is comparatively larger than the RISC architectures. From decode it creates effectively RISC like instructions now ... supposedly been this way for many years, so RISC vs CISC arguments have mostly disappeared.
Agreed. The main weakness is x86 instructions being variable-length, which make parallel decoding difficult. ARM being fixed-length makes that part easier. My view is that x86 CPUs are the perfect blend of CISC and RISC, at least in their popular senses. Even ARM is getting more complicated over time.
Everyone is discussing about architectures, which are inportant, I have no doubt about this.
But let's remember a bit about Intel history for the past 15 years. Intel went from 65nm based cpus around 2006-2007 to 45nm and then to 32nm and 22 nm by 2011!
Then , it supposedly had diffciculties at 14nm, and it took 3 years to half-launch cpus at 14nm! Then it had more diffculties advancing further and untill today you need to be lucky to find products at 10nm. Full 7 years after launching 14nm cpus they are not able to effectively mass produce chips at 10! As a parenthesis , people please remember that Paul Otellini was CEO until 2013. Normally , one would accept manufacturing difficulties with good will , if not with some scepticism too. Imo Intel's downfall began right after launching Ivy bridge at 22nm. There was a fab to be made for the new 14nm innovative process that cost 5 billions and there was a change in CEOs.
Seeing however how Intel's competitors, which were behind Intel at 2011, managed to reach and surpass Intel through all these years , goes to show that manufacturing difficulties were not insurmountable. And if it were someone to win this should be Intel, while at its peak and all the talent and money under its umbrella.
Being held back so many years in the manufacturing field was the main reason why Intel eventually lost the ball. I mean , how on earth is it possible to still not be able to master 10 nm which is capable of 100 mtr/mm2 , while TSMC managed to offer 5nm products with a transistor density of 170 mtr/mm2? And TSMC and maybe Samsung are ready to get to the next phase to even smaller nodes. Intel on the other side , seemingly is only able to announce new nodes and architectures only to delay them a few months later.
It is very probable Intel has been facing huge internal organsational and administrative problems through all these years , that no-one dares to admit. Because , to make an analogy with soccer, it had the best goalkeeper facing a penalty , only with the goalkeeper to step aside and do nothing while the opponent player was executing the kick. It scored against its team while at its peak . How this happened is up to Intel to search and find its internal affairs. This much is obvious. It is the details that need to be clarified.
Architecture is good and all, but if it is so important why did not Apple choose 14 or 22 nm to make its silicon? Food for thought.
Speaking of departed CPU architects, why did Jim Keller leave? Will Intel try to bring him back? From all his sudden departures and job changes, I got the impression he might be high maintenance and not someone who can be counted on to actually stick around in any job, but Reuters said: "In June, it lost one of its veteran chip designers, Jim Keller, over a dispute on whether the company should outsource more of its production, sources said at the time."
this bodes well for their future. Heck, even with these massive fab issues they stayed up there with AMD, barely losing to them in the high end while using 14nm process for 6 years and refreshing the same old Skylake design. If it ever was a company capable of doing that, it was Intel. Even after all these years they still have record revenues because the quality of the products is top notch. Sure, the specs are becoming more and more obsolete since you can compete several years with a fantastic silicon (Skylake), but at some point your competitors will catch-up and surpass you. Anyway, I recall that even Jim Keller said he was working on a 800+ OoO instruction window core. That is 3x the size of Tiger Lake and Zen 3. Bigger than the Apple M1 fat core. And I am guessing he was working on a 2023 product.
> they stayed up there with AMD, barely losing to them in the high end while using 14nm process for 6 years and refreshing the same old Skylake design.
You're missing the drubbing Intel is taking on server and workstation chips. The only reason it's not far worse is that AMD is supply-constrained.
But also even Amazon and Ampere's ARM-based CPUs passed Intel by...
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jamesindevon - Thursday, January 21, 2021 - link
One of the three senior architects of the P6 was Bob Colwell. He wrote this about the other two:"I can't imagine a team that would be unable to get along with somebody like Glenn Hinton. Glenn is just a great guy to be around. I think David Papworth is too. For somebody at that level, to not have an ego problem is remarkable and those guys don't. It's not that they don't have an ego. They know they're good at it but they don't use that as a stick over anyone else's head. No “shut up, I'm the king". It doesn't happen. So it was really a blast to work with those guys."
jamesindevon - Thursday, January 21, 2021 - link
The source of that quote is an "Oral History of Robert P. Colwell" PDF, a transcript of an interview with him. I wanted to post a link, but the comment system thought that was spam.Pity. It's a great and extremely illuminating read, with some fascinating insights into Intel history.
Ian Cutress - Thursday, January 21, 2021 - link
Page 144 of http://newsletter.sigmicro.org/sigmicro-oral-histo...Ian Cutress - Thursday, January 21, 2021 - link
This is fun reading. Dang, I had plans to work today.dwbogardus - Thursday, January 21, 2021 - link
Colwell is great fun to read, but even more fun to hear in person. I heard him tell some great "war stories" at two Intel patent award dinners...phr3dly - Thursday, January 21, 2021 - link
Good grief. No kidding. I'll save this for tonight. A bit humorous that on a random page I flipped to he's discussing how great Rani Borkar was. And it's true. Of course BK chased her away and she's now at Microsoft recruiting whatever talent remains in Hillsboro.GTS81 - Saturday, January 23, 2021 - link
I would've thought you were joking about Rani recruiting whatever talent remains in Hillsboro if I didn't look at LinkedIn connections. Left a while back but goodness, you're right! Many of the so-called design kingmakers from JF has either gone to Microsoft, Apple, or Ampere.dwbogardus - Thursday, January 21, 2021 - link
I just spent all afternoon reading that oral history. I haven't had that much fun in a long time! He believes decisions should be data-driven, and that you can't claim that things work, if you haven't tested them. He has ethics, and believes you shouldn't lie to people (who may not know the difference anyway) simply because you're trying to make a point you think is justified. An he's been caught in the crossfire of both academic and corporate politics, but he went around (and above) the roadblocks. It is such a pleasure to read the ruminations of such a brilliant engineer, and all-round interesting guy.mode_13h - Saturday, January 23, 2021 - link
Who? Colwell or Gelsinger?It's rare and precious to work in an environment of such intellectual rigor.
AndrewJacksonZA - Sunday, January 24, 2021 - link
Thank you James.thedillyo - Thursday, January 21, 2021 - link
Should "Given Intel’s successes" be "Given Hinton’s successes"?forextor - Thursday, January 21, 2021 - link
Normally in situation like this people get young fresh blood instead of same 'ol same 'ol... why not steal apple's cpu architects?Valantar - Thursday, January 21, 2021 - link
Because Qualcomm already did? https://www.youtube.com/watch?v=-lq6vZcWLDMThe Hardcard - Thursday, January 21, 2021 - link
that is not necessarily the end of it. Company loyalists won’t move at all. However, once you switch companies it gets easier to do it again. Not unlike murder.mode_13h - Saturday, January 23, 2021 - link
> Not unlike murder.My, what a charming analogy. Not that I doubt it, but not the kind of thing you want to say in person.
FunBunny2 - Thursday, January 21, 2021 - link
I continue to be perplexed with this Apple fawning, ARM too for that matter. After centuries of maths and 80-ish years of computing machines, the notion that there are tectonic changes to computing, previously unknown, just waiting for some smart young kiddo to find? Balderdash. The Von Neumann machine still reigns. RISC owns the machine, although buried ever deeper below the 'ol same 'ol ISAs. I'll bet the only difference among all microprocessors within the actual computation engines is syntax/mnemonics. They all do the same maths.No one, to my knowledge, has figured out how to parallelize single-threaded user space problems on the fly, on the metal. I'd wager that 99.44% of 'innovation' in cpu over the last 3 decades has been three efforts:
- smaller transistors
- from that, hiding the real machine from the compiler, as above
- from that, ever more concentration of function into the 'cpu' chip that isn't computational
or to be brutal, has anyone devised a new ALU, ever? register width doesn't count.
so, it seems that most design these days amounts to deciding how to allocate the burgeoning of transistors (Apple seems to like expanding buffers and caches) and deciding what functions to assemble on the chip. which is not to say that Forrest Gump could do a good job
IOW, what new 'innovations' have been discovered in the fundamental computation process? I'll skip quantum computing, as it's, so far, been found irrelevant to all but a teeny, tiny niche of possible problems.
demian_thorne - Thursday, January 21, 2021 - link
In the grand scheme of things you are absolutely correct. We are still in the Von Neumann - Moore’s law level. Two observations.1. I think quantum computing is not to be discarded just that easily. It applies at the moment to some specific NP-problems but they are not trivial (encryption breaks) and it might apply to other areas as it evolves. It is too early to say ....
2. The Von Neumann basic architecture of two level storage -volatile and permanent- is I think going to be converged to one level storage permanent storage at the speeds of currently volatile storage.
Other than that, I agree with you ....
GeoffreyA - Thursday, January 21, 2021 - link
Agree fully.GeoffreyA - Thursday, January 21, 2021 - link
Or rather for the most part.JKflipflop98 - Friday, January 22, 2021 - link
In the book, Forrest is a mathematical savant. He might well come up with a new APU.JayNor - Friday, January 22, 2021 - link
Intel has given their Client 2.0 presentation ... stitching and stacking chiplets. They also taped out a stacked SRAM, built with hybrid bonding last year. They also are introducing CXL into the server CPUs and GPUs this year. They also demoed co-packaged photonics last year. The also shipped their first foveros 3d chip design last year.All these seem to enable new paths for chip designs, including architectures.
I could see CPU cores turning into accelerators with large, biased private caches, for example, as being a natural extension of the CXL XPU designs that are being conceived for ai/hpc processing.
mode_13h - Saturday, January 23, 2021 - link
Neural network hardware is not intrinsically Von Neumann, though it can be implemented that way.I'm not familiar enough with graph analytics processors to say whether they potentially break Von Neumann, as well.
FPGAs are also not intrinsically Von Neumann, though can obviously be used that way.
And what do people think about transport-triggered architectures? Fundamentally asych computing strikes me as fairly non-Von Neumann.
For the sake of completeness, other non-Von Neumann architectures that come to mind are analog and quantum. Analog has some potential for neural computing. I think Intel's Ni1000 was analog?
Anyway, it's always hard for a new technology to usurp an old one. Just look at how long it took for NAND flash to overtake HDDs! You could see it coming for decades, but HDDs just kept improving fast enough to stay ahead of it for quite a while. In a similar way, Dennard scaling enabled Von Neumann architectures to evolve rapidly enough to keep from being overtaken, and software compatibility provided a big enough hurdle that nothing else was able to mount a serious threat. However, as manufacturing tech runs out of steam, perhaps the industry will finally be driven to revisit some of the more fringe computer architecture ideas that've been left by the wayside.
Lord of the Bored - Friday, January 22, 2021 - link
Because in this case the old hands are genuinely good at this. Microprocessor design is not a field where skills rapidly expire. Fresh blood, by contrast, has no proven track record and will likely have to spend time learning what works, from ... the old hands.Apple's CPU design team also eked out a good degree of their performance by making design compromises that wouldn't be acceptable in the x86 market.
Notably, system RAM is integrated into the CPU package. This greatly boosts performance, but also greatly limits capacity and completely negates upgradability. Intel knows about this, and started pulling cache into the processor with the 486, but they can't do the same for main memory. The x86 market wants their DIMM slots, wants to be able to take one CPU and pair it with arbitrary amounts of RAM(where arbitrary<256TB, anyways), so that is a major performance hack that is immediately off the table.
GeoffreyA - Friday, January 22, 2021 - link
According to infallible modern thinking, old is bad and new is good.FunBunny2 - Friday, January 22, 2021 - link
"Notably, system RAM is integrated into the CPU package."from an RDBMS point of view, likely any transaction, having a true 'single level store' makes ACID come out in the wash, and negates all other store methods. Optane is a step in that direction. this will require 'new' ways to manage transactions, in that currently RDBMS (as an example) will write to some log first (usually, but not necessarily) then to the database. whether such a two-step transactional protocol is still required for a memory-only storage? belt and suspenders?
mode_13h - Saturday, January 23, 2021 - link
> Notably, system RAM is integrated into the CPU package. This greatly boosts performance, but also greatly limits capacity and completely negates upgradability.Use HBM2 as L4 cache and 3D XPoint for expandability. Software can even treat the HBM2 as system RAM and swap to Optane DIMMs.
Rookierookie - Thursday, January 21, 2021 - link
I am excited to see that they are hiring the people who developed Pentium 4.DigitalFreak - Thursday, January 21, 2021 - link
Yeah, I was going to say 'leading microarchitecture development of Pentium 4' isn't something to be proud of.The Hardcard - Thursday, January 21, 2021 - link
Why would team membersnot be proud of the Pentium 4, or Bulldozer for that matter?Those failures were not because of incompetent designers and engineers who just didn’t know what they were doing. They were simply bets that were made at the company level. The staff to be done with a finite amount of resources, a finite amount of money, a finite amount of time, and particular product targets - all if which affect cgances of success.
Nearly every designer and all of those teams could also work on other teams. Not that there aren’t some who are better than others, but they all can work on successful architectures. Just as they can all work on failures, and probably have.
Pentium 4 and Bulldozer required just as much intelligence, imagination, and work ethic as the M1. In the quest for technical leadership, bets like these have to be made. There are no guarantees when you go in.
lmcd - Thursday, January 21, 2021 - link
Bulldozer was a bet that GCN would both reach maturity sooner, and be flexible enough to realistically take over floating point compute, while said GCN products had no good compute API (no, OpenCL does not count as "good").That's a company failure for sure. It was also a manufacturing failure -- people act like Intel's struggles in manufacturing are unique to it, but AMD was stuck at 32nm/28nm for about as long as Intel has been stuck at 14nm.
P4 micro-op cache was revolutionary, but not yet ready for prime time. Also it was Intel's first SMT architecture! I'd argue the features Intel developed for P4 were essential, but hindered by the mistake of a long pipeline and less-accurate branch prediction.
GeoffreyA - Friday, January 22, 2021 - link
It's possible the P4 would've gone on a bit more if Northwood had been widened and its stages cut down. But Intel was still under the deep-pipeline/MHz delusion back then, which led to Prescott, whose 31 stages were supposed to usher in 10 GHz. Today's CPUs---Sandy Bridge and upwards, and Zen---have up to 19 stages, pretty close to the P4's 20. The difference is they're much wider, among other things (bigger caches, better branch prediction,* effective micro-op cache, etc.).* In that era, the Pentium 4's branch prediction was superior to the K8's, but the latter wasn't being handicapped by a lengthy pipeline. Prescott improved on this further, adding the Pentium M's indirect prediction. But all that couldn't overcome the deep pipeline.
mode_13h - Saturday, January 23, 2021 - link
Wasn't Prescott forced to deepen its pipelines in order to cope with 64-bit (which ended up not really being enabled until the Pentium D)?By the time Prescott was designed, I think Intel was well aware that P4 would never come close to 10 GHz. Scaling to 10 GHz was just an initial design goal of the NetBurst uArch, and badly underestimated leakage of the target process nodes is ultimately what sabotaged it. If manufacturing had managed to deliver on that front, then the NetBurst uArch could have upheld its part in enabling those frequencies.
GeoffreyA - Sunday, January 24, 2021 - link
I believe it was due to clock speed mainly, more stages allowing each to be simpler and so clock higher. The idea was that Prescott would carry on Willamette and Northwood's philosophy, adding another 11, just like they added 10 to the Pentium III. Any loss in IPC would be offset by frequency. Unfortunately, it reached only 3.8 GHz and took a lot of power to do so. I remember the Pentium Ds felt terribly slow in Windows too, compared to Willamette and Northwood.As for x64, I reckon it wasn't that difficult to add. Just widening and adding of registers I believe, along with some other changes.
GeoffreyA - Sunday, January 24, 2021 - link
On a side note, people might wonder how could Intel have been so stupid to come up with Prescott. I think it's rather that Prescott's design was laid down long before it became apparent what a blunder Netburst was, with its deep-pipeline/high MHz/low IPC principle.mode_13h - Sunday, January 24, 2021 - link
> I think it's rather that Prescott's design was laid down long before it became apparent what a blunder Netburst wasMaybe they still thought they could get leakage under control, which would've really let it stretch its legs. People have clocked Prescotts above 6 GHz with LN2 cooling, which shows they were still thinking high clockspeeds were a viable option, as it was being designed.
GeoffreyA - Sunday, January 24, 2021 - link
I remember that Cedar Mill (Prescott's last revision) curtailed power quite a bit, or brought down the TDP to 65W. I need to read up about CM. Curious to see what they did. Don't think it was a die shrink.mode_13h - Monday, January 25, 2021 - link
> Don't think it was a die shrink.It was, for sure. I remember reading about one last die shrink and was eager to see how it would stack up against Core 2, when they were on the same process node. IIRC, the results were still pretty disappointing for the P4. However, I didn't pay much/any attention to perf/W, which it sounds like was the main improvement.
GeoffreyA - Tuesday, January 26, 2021 - link
"one last die shrink"You're quite right. It was the 65 nm node.
https://www.anandtech.com/show/1834/2
mode_13h - Sunday, January 24, 2021 - link
> I believe it was due to clock speed mainly, more stages allowing each to be simpler and so clock higher.It's true that Prescott did clock higher than Northwood.
> As for x64, I reckon it wasn't that difficult to add. Just widening and adding of registers I believe, along with some other changes.
It also adds more registers, which means widening muxes. More importantly, 64-bit arithmetic increases the critical path, because each bit in result is contributed to by the lower-order bits. Therefore, I wonder if they had to reduce the complexity of some pipeline stages, when going to 64-bit, which would have to be compensated for by adding more of them.
GeoffreyA - Sunday, January 24, 2021 - link
Likely, they used every opportunity available to squeeze 31 stages out of Northwood's 20. How much of a hand 64-bit had in that, I can't say, but doubt whether it was a massive role. Looking at the K8, it had only two more stages than K7's 10. And Core, at 14, was roughly the same as the Pentium M.mode_13h - Monday, January 25, 2021 - link
> doubt whether it was a massive role. Looking at the K8, it had only two more stages than K7's 10. And Core, at 14, was roughly the same as the Pentium M.If you're not comparing on the same process node, then it doesn't mean much.
mode_13h - Saturday, January 23, 2021 - link
The P4's HT was sunk by lack of a good scheme for dealing with cache contention, IIRC. When Nehalem brought it back, I think that was the main addition.GeoffreyA - Sunday, January 24, 2021 - link
Along with too few execution resources, if I remember right, and compared with the Athlon.mode_13h - Sunday, January 24, 2021 - link
When I first got my P4, I wrote a little benchmark that ran 2 threads each doing some fundamentally serial computation. The result was almost a perfect 2x speedup. Another case it handled well was one thread doing memcpy() while another did complex computation - I think I got like 85% speedup, there.No doubt that Nehalem being much wider also made the payoff bigger, for HT. These days, I enjoy it quite a lot when compiling code. However, I find it helps very little, in AVX2-heavy workloads.
GeoffreyA - Sunday, January 24, 2021 - link
That's quite a speedup. To this day, I have never tested HT on a Pentium 4. The only ones I had/have access to were a 1.7 GHz Willamette and 2.4 GHz Northwood.As for AVX2, I reckon it's because those instructions are already filling the FP units to the edge, so there's not much left for a second thread.
mode_13h - Monday, January 25, 2021 - link
> As for AVX2, I reckon it's because those instructions are already filling the FP units to the edge, so there's not much left for a second thread.Yes, the code is highly-optimized with AVX2 in the hot loops. Since the CPU's AVX pipelines can filled with a single, well-tuned thread, the result wasn't surprising (but noteworthy, none the less).
Another use of SMT to help hide long memory access latencies, but if your access patterns are sufficiently regular, then the prefetcher in modern CPUs can do that even better.
GeoffreyA - Tuesday, January 26, 2021 - link
I've got a feeling that even with AVX512 support in Ice and Rocket Lake, AVX/2 code won't show much of a boost, likely because support is being implemented using two 256-bit halves.By the way, here's an excellent chart I found some years ago. Some useful data on the Pentium 4 as well.
https://images.anandtech.com/reviews/cpu/intel/cor...
mode_13h - Thursday, January 28, 2021 - link
Thanks for the chart. That's interesting. I gather the P6 is Pentium Pro? Than mostly makes sense, but some things are much bigger than I thought, like the number of issue ports... I could swear it was only 2-way superscalar.GeoffreyA - Sunday, January 31, 2021 - link
"I gather the P6 is Pentium Pro?"It should be. But I'll take a look into this and return with an answer. Not sure how much changed in the Pentium II and III, beyond MMX, SSE, and cache. And yes, I expected it to have 3 issue ports myself.
GeoffreyA - Sunday, January 31, 2021 - link
According to Agner Fog, there are 5 ports, with various execution units, but owing to register renaming being limited to 3 uops earlier on, in most cases you'll be limited to 3 uops (pp. 76, 80).https://www.agner.org/optimize/microarchitecture.p...
mode_13h - Sunday, January 31, 2021 - link
Cool. Thanks.lmcd - Thursday, January 21, 2021 - link
The micro-op cache that sucked in P4 is also part of what made Sandy Bridge great. Strongly disagreed with this assertion.GTS81 - Saturday, January 23, 2021 - link
Trace cache and DSB not identical.Makaveli - Thursday, January 21, 2021 - link
lol yep Pentium 4 still leaves a bad taste in your mouth.mode_13h - Saturday, January 23, 2021 - link
It gave us SSE2, which was a lot nicer to program than MMX. That's why I bought one.mode_13h - Saturday, January 23, 2021 - link
Also, hyperthreading could deliver real improvements in responsiveness and usability. Remember that these were single-core CPUs (until Pentium D, at least).GeoffreyA - Thursday, January 21, 2021 - link
Despite setting out on a misguided philosophy, the Pentium 4 was an excellent piece of engineering, Northwood especially. Heck, even Sandy Bridge borrows some things from the P4, depending on how one looks at it. And I'd say similar things about Bulldozer and its engineers. Also, Hinton worked on P6, and if that's not an exceptional credential, I give up.Pewzor - Thursday, January 21, 2021 - link
P6 is before most of the kids time that comments here. They are probably too young and too uninformed to know much they "try" to talk about.lipscomb88 - Thursday, January 21, 2021 - link
Your crotchety comment aside, there are plenty of people who enjoy learning about things that existed before their time. I wasn't interested in p6 when it was current but my interest in old architectures has grown over time.Lord of the Bored - Friday, January 22, 2021 - link
Seriously, he developed the friggin' P6 architecture, and everyone's just "the Pentium 4 is his crowning achievement". Come ON.Pentium 2/3 were absolutely amazing, and the P4's big claim is "it got Intel out of AMD's way for once".
eddman - Thursday, January 21, 2021 - link
They need to come up with a proper high IPC big core architecture. Enough with this GHz push nonsense.When a relative newcomer in CPU space, apple, beats your even the latest arch, willow cove/tiger lake, you should realize it's time for some actual engineering effort.
Wilco1 - Thursday, January 21, 2021 - link
Agreed. Note you need small, efficient, high IPC cores. When a startup designs a server using standard Neoverse N1 cores that achieves 2.5 times the throughput per socket than your most expensive Xeon Platinum, you know it is time to get back to the drawing board.DigitalFreak - Thursday, January 21, 2021 - link
Intel could get away with being lazy in the server space as Windows was the most widely used server OS, ran only on x86, and Linux was a non-factor. Those days are long gone.kgardas - Thursday, January 21, 2021 - link
small, efficient, high IPC cores -- pick 2 from those three. W.r.t. apple beating tiger, well, if you can put 4x number of transistor on the same square like intel, then indeed, you can come with some wider design and still be efficient. No wonder apple is the first on 5nm. Yes, I know, I can't compare 5nm TSMC x4 ~= 10nm Intel, but still. In fact it's a wonder stand tiger is that good even under current circumstances.Thanks for the article, it tells also what I've had in mind for some time that intel does have more designs in house, but is just hurt by their inability to put that through manufacturing well. Pity, but such is life, IIRC TSMC had that @28nm too (or some other node)?
name99 - Thursday, January 21, 2021 - link
This has been covered MULTIPLE times.Intel claims they have 100 MTr/mm^2 with their 10nm. And yet they ship Lakefield logic die with 49 MTr/mm^2... (FWIW Apple hit ~90 MTr/mm^2 on TSMC 7nm which is likewise rated at 100 MTr/mm^2)
It's THEIR choice to use low logic density. They control the CPU design and the process.
Why do they make that choice? Well, you explain it to use since you're such an expert and so dismissive of everyone else's explanations.
TristanSDX - Thursday, January 21, 2021 - link
lol, is that means there is generation misaligment ? Pat can't effecively work with younger engineers ? Seems that he want not really CEO seat, but full control on new CPU designSahrin - Thursday, January 21, 2021 - link
More of the old way of doing things.GeoffreyA - Thursday, January 21, 2021 - link
When the way is lost (like Intel has), one needs to go back to the old paths and from there proceed.Silma - Thursday, January 21, 2021 - link
Having a meaningful contribution outright is next to impossible.Given that Intel's main problem is being 2 generations late in production, a new CEO can't do much except trying to reassure customers it will be worth it to hang out for a few years.
webdoctors - Thursday, January 21, 2021 - link
Why dont they rehire the architects they fired in the last 1 yr, they've already got thousands of architects, a few here or there won't change anything.Lord of the Bored - Friday, January 22, 2021 - link
I'd wager some of those are already having offers tossed their way. But that won't make news like "co-creator of the Pentium II/III" will.Rictorhell - Thursday, January 21, 2021 - link
I'm hoping for the best for Intel, despite my opinions about their business practices over the last few decades. As far as computing has come, and for all the progress that has been made, I still feel like we are technologically stunted, or blocked, in a lot of ways. The cost of developing and manufacturing CPUs is so high that only a handful of companies and individuals can afford to do it, and invest in it.Everyone in these companies has to basically bide their time. They are all at the beck and call of the higher ups in the individual companies, that are interested in profits, profits, profits.
Even when a breakthrough is made, there is a strategy employed as to how and when to implement the breakthrough, and how quickly or how slowly to roll it out and implement it into actual productts.
From my point of view, nothing is going to spur innovation and growth, outside of serious, meaningful competition, amongst these companies. If one company isn't performing well, or is, for all intents and purposes, a lame duck, then that places their competitors in a position where they can comfortably slow down, and hold back, where they might otherwise have increased their efforts and pushed forward.
We're in 2021, but to me, the technology isn't 2021 technology, the technology is lagging years behind where it COULD be, or where it MIGHT be.
If there is this hidden gem of IPC improvements and other advances that are out there, just waiting to be set free, nothing is going to set it free like competition and genuine enthusiasm, amongst these companies.
pxl9190 - Saturday, January 23, 2021 - link
you think too highly of the architects and their employers. 15 to 20% IPC gain in a generation is highly non trivial and is only achieved once every few generations.the amount of engineering that is needed per every single % ipc gain across a wide spectrum of workload is more than you think . it is naturally done rev by rev....
vFunct - Thursday, January 21, 2021 - link
I hope they work on something post x86, as ARM pretty much is cleaning up there. Maybe they can work on something with RISC-V or a new architecture (not that weird Itanium crap..)At this point, ARM is their main competitor, and the only viable challenger I see to it is RISC-V, with a potential 2x improvement in efficiency compared to ARM.
kgardas - Thursday, January 21, 2021 - link
I also think that for Intel to release some RISC-V SoC on latest Atom level performance would at least a bit undermine ARM movement which would be a good thing for them. Just to buy some time...Wilco1 - Thursday, January 21, 2021 - link
What would the point of that be? RISC-V doesn't run on Windows or Android, and latest Atom is far behind recent Arm cores.kgardas - Thursday, January 21, 2021 - link
Make a wave(s). Intel needs (a) improve manufacturing of 10nm/7nm/etc and (b) a little bit brake ARM. RISC-V may be the right weapon to attack from the bottom. In comparison with current RISC-V SoCs, latest Atom cores are fine.mode_13h - Saturday, January 23, 2021 - link
If Android doesn't already support RISC-V, then it's only a matter of time. Linux has already supported it for a few years, now. That means the kernel and toolchain support are already there.mode_13h - Saturday, January 23, 2021 - link
The main problem with Atom cores is Intel's manufacturing node. Tremont is good and Gracemont will be even better.Atom isn't supposed to compete with ARM's fastest cores, either. It's mostly making a play for the mid-range of efficiency and performance that you find in Chromebooks and on SBCs. Still, it does suffer from the x86 tax.
name99 - Thursday, January 21, 2021 - link
"Assuming that Glenn is talking about a fresh project within Intel’s R&D ecosystem, it will be 3-5 years before we see the fruits of the labor"That seems overly optimistic.
From slides presented at Stanford by, ... checks notes ..., Glenn Hinton...:
Nehalem started in 2003 (with research even earlier)
https://web.stanford.edu/class/ee380/Abstracts/100...
and was released at the very end of 2008. (Of course that was back in the day when "release" meant something like "can buy it within a few weeks", not today's "step 17 of a 37 step fan dance before you will actually own one".)
mode_13h - Saturday, January 23, 2021 - link
But that's so long ago... are you certain that design cycles haven't shortened, since then?ThereSheGoes - Thursday, January 21, 2021 - link
I'm disappointed to see AnandTech stoop to clickbait. The new CEO hasn't arrived at Intel yet (not until next month), so he did not have any direct role in hiring this engineer. As noted in the article itself, the engineer has been in talks with Intel since November, long before the new CEO arrived. Also, the title says "architects" when in fact this is a single architect. These problems also make the asserition that the new CEO is 'making waves' highly inaccurate.lipscomb88 - Thursday, January 21, 2021 - link
I think it's reasonable to assume though he hasn't technically started yet, that the new ceo isn't passively awaiting that date by doing nothing. Even his hiring itself was a contributing factor in the fellow returning to Intel, as the article also states. I don't think your argument that this is clickbait is reasonable.ThereSheGoes - Thursday, January 21, 2021 - link
This is rather simple:1.) The engineer was in negotiations long before CEO announcement and arrival
2.) CEO hasn't started working yet, thus had no direct involvement in hire
3.) Architect, not architects
4.) A singular architect is certainly not 'making waves' in a company with more than 50,000 engineers.
phr3dly - Thursday, January 21, 2021 - link
All due respect:* These people talk. It's *quite likely* that both Hinton and Gelsinger knew of each other's intentions. Gelsinger probably would have returned without Hinton, but it wouldn't surprise me at all that Gelsinger returning sealed the deal for Hinton. It also wouldn't surprise me if Gelsinger has put out feelers to other former Intel folk.
* A single architect absolutely does 'make waves'. Keller certainly made waves when he joined Intel. Not sure what his real impact ended up being, but waves were made. Likewise Raja. Hinton has a long history with Intel engineers. He is well known and well respected.
* A big complaint internally at Intel in recent years has been that upper management isn't listening to its technologists. Who knows, this may even be one reason Murthy is no longer there...... There is every reason to believe that Gelsinger will correct that problem, and I'd imagine that factors heavily into Hinton's willingness to return.
ThereSheGoes - Thursday, January 21, 2021 - link
All due respect - none of your statements disputes the fact that the title is factually inaccurate - i.e., clickbait.lmcd - Thursday, January 21, 2021 - link
The posted LinkedIn comment literally says Gelsinger is why Hinton is back, from Hinton's own fingers. What more do you want? Please. RTFA.Ian Cutress - Thursday, January 21, 2021 - link
Thanks for the backup.Gelsinger mentioned Hinton explicitly in the financial call today as bringing the talent back to Intel. He's also had time to peer into Intel's 7nm data and projections and make some conclusions on it - Feb 15th is more a date for Bob being out of the door than anything else. We're currently in transition, and Gelsinger has had strong words to say already.
Also, Hinton's own Linkedin thread mentions other engineers returning or potentially returning on this news.
mode_13h - Saturday, January 23, 2021 - link
> Keller certainly made waves when he joined Intel. Not sure what his real impact ended up being, but waves were made. Likewise Raja.How do you know? And if you're not sure about the impact, then what do you mean by "waves"? Do you just mean that we heard it being reported? That's somewhat circular reasoning.
quadibloc - Thursday, January 21, 2021 - link
Intel certainly should avail itself of the best processor design talent possible, but this isn't the major issue it faces. The major issue it faces is getting its fabs up to speed on the 10nm and 7nm processes. Outsourcing to TSMC, however attractive that might have seemed a year ago, is now being proved to be a chimera by the shortages of AMD products. Intel products that no one can get their hands on aren't going to help it recover in the competition with AMD.JayNor - Friday, January 22, 2021 - link
"Intel products that no one can get their hands on..."Intel stated there are already 150 TGL designs shipping, so they don't seem to be having a current capacity problem with their 10SF process.
Aekitct - Thursday, January 21, 2021 - link
Architect is a licensed professional that holds a bachelor's degree in Architecture. Please avoid appropriating real degrees with high regard for namesakes of lame computer science degree.grant3 - Thursday, January 21, 2021 - link
Sorry to inform you: licensing groups do not get to hold the entire world hostage for the definitions of words.Sure, a person may require a license to legally market his services as a "Building architect" to the public, in most jurisdictions. But an expiring license doesn't magically mean that person is no longer an "architect." It just means he's legally restricted from advertising or certifying work that requires that license.
Furthermore, a "processor architect" never needs to be licensed to design processor architectures. Glenn Hinton isn't an architect because of a "lame computer science degree". He's an architect because he not only performed the work of architecting processors, but became a recognized world leader in that field.
If you or anyone else can't handle someone legitimately being called an architect because you're upset that it's "appropriating real degrees with high regard" then you're in for a lifetime of disappointment outside the ivory towers of your fellow degree snobs.
mode_13h - Saturday, January 23, 2021 - link
Exactly. Thanks for that.I can legally advertise myself as a software engineer, precisely because there's no certification required in my state for that job title. Same for computer architect.
Lord of the Bored - Friday, January 22, 2021 - link
Architects design architecture.CPU architecture is an accepted term.
Therefore, CPU architects exist, regardless of what building architects want to believe.
GeoffreyA - Friday, January 22, 2021 - link
What's more, I wonder what their building architecture software runs on. Fresh air, I suppose.WaltC - Thursday, January 21, 2021 - link
I hope for Intel's sake they do not try and resurrect Itanium. Bringing old hands out of retirement is certainly a mark of desperation. Let's hope they have some new ideas--finally--now that AMD has once again started a fire underneath the Intel derrière...;) Rehashing 14nm ancient architectures won't carry them very long from nown, however. Monopolistic thinking and management put Intel where it is today in reference to AMD. It's difficult to teach old dogs new tricks--we'll see how Intel handles being second fiddle. I have zero sympathy for Intel--none at all. OTOH, I have great admiration for AMD--a company of engineers versus the Intel saga of empty suits and bean counters perpetually running the show. The days of having no competitors because Intel ran them out of business are behind Intel now and will never come again--now we'll see what stuff the company is made of--if anything.grant3 - Thursday, January 21, 2021 - link
Worrying about "resurrecting Itanium" is an oddly specific fear. Why would you even suspect that's a topic of debate at Intel?Lord of the Bored - Friday, January 22, 2021 - link
I believe the argument is "lol old people made old processorz like itanium".And they don't actually register the Pentium 4 itself as a fiasco, so they reached for it's dearly-departed sister chip.
Makste - Friday, January 22, 2021 - link
Your fear of the itanium resurrection feels more than authentic 🤔mode_13h - Saturday, January 23, 2021 - link
Assuming they're eventually going to get beyond x86, why do you care what it is? IA64's biggest problems were that it was never out-of-order (though it could've been) and never got imbued with SIMD instructions. Those are both fixable problems and IA64 probably has the broadest software support after ARM, so it makes a lot of sense.I think that by moving data-dependency analysis out of the hardware, IA64 has a real chance to be more efficient and perhaps even faster than ARM or RISC-V. It just needs a proper implementation, which Intel never did. They burned their entire transistor budget on making it as wide as possible, and by the time they could possibly revisit the decision not to go out-of-order, management had already lost interest.
Burning Up - Thursday, January 21, 2021 - link
Intel is in serious trouble and decline and these hires will not change it. RISC and ARM is the future and not x86.grant3 - Thursday, January 21, 2021 - link
I see a lot of comments like these, worshipping RISC as if it's automagically the ideal ISA philosophy for all situations. This despite decades of research have conclusively proven.... "it depends."ARM is great, ARM is popular, but it's only 'the future' until another superior approach is validated.
Lord of the Bored - Friday, January 22, 2021 - link
RISC has been the future that is dooming x86 for what, forty years now?RanFodar - Friday, January 22, 2021 - link
They can do it, unless Intel has something up in their sleeves. I'm sure they have one.JayNor - Friday, January 22, 2021 - link
The Gracemont cores in Alder Lake appear to be a reply to the small ARM cores in the M1.I've read that the x86 decode is all that is comparatively larger than the RISC architectures. From decode it creates effectively RISC like instructions now ... supposedly been this way for many years, so RISC vs CISC arguments have mostly disappeared.
lmcd - Saturday, January 23, 2021 - link
The Gracemont cores in Alder Lake have likely been planned for 4-5 years.GeoffreyA - Sunday, January 24, 2021 - link
Agreed. The main weakness is x86 instructions being variable-length, which make parallel decoding difficult. ARM being fixed-length makes that part easier. My view is that x86 CPUs are the perfect blend of CISC and RISC, at least in their popular senses. Even ARM is getting more complicated over time.IUU - Saturday, January 23, 2021 - link
Everyone is discussing about architectures, which are inportant, I have no doubt about this.But let's remember a bit about Intel history for the past 15 years.
Intel went from 65nm based cpus around 2006-2007 to 45nm
and then to 32nm and 22 nm by 2011!
Then , it supposedly had diffciculties at 14nm, and it took 3 years
to half-launch cpus at 14nm!
Then it had more diffculties advancing further and untill today
you need to be lucky to find products at 10nm. Full 7 years after
launching 14nm cpus they are not able to effectively mass produce
chips at 10!
As a parenthesis , people please remember that Paul Otellini was CEO
until 2013.
Normally , one would accept manufacturing difficulties with good will , if not
with some scepticism too.
Imo Intel's downfall began right after launching Ivy bridge at 22nm. There
was a fab to be made for the new 14nm innovative process that cost 5 billions
and there was a change in CEOs.
Seeing however how Intel's competitors, which were behind Intel at 2011, managed to reach
and surpass Intel through all these years , goes to show that manufacturing difficulties
were not insurmountable. And if it were someone to win this should be Intel, while at its peak
and all the talent and money under its umbrella.
Being held back so many years in the manufacturing field was the main reason
why Intel eventually lost the ball. I mean , how on earth is it possible to still not be
able to master 10 nm which is capable of 100 mtr/mm2 , while TSMC managed to offer 5nm
products with a transistor density of 170 mtr/mm2?
And TSMC and maybe Samsung are ready to get to the next phase to even smaller
nodes. Intel on the other side , seemingly is only able to announce new nodes and architectures
only to delay them a few months later.
It is very probable Intel has been facing huge internal organsational and administrative problems through all these years , that no-one dares to admit. Because , to make an analogy with soccer, it had the best goalkeeper facing a penalty , only with the goalkeeper to step aside and do nothing while the opponent player was executing the kick. It scored against its team while at its peak . How this happened is up to Intel to search and find its internal affairs. This much is obvious. It is the details that need to be clarified.
Architecture is good and all, but if it is so important why did not Apple choose 14 or 22 nm to make its silicon? Food for thought.
JoeDuarte - Tuesday, January 26, 2021 - link
Speaking of departed CPU architects, why did Jim Keller leave? Will Intel try to bring him back? From all his sudden departures and job changes, I got the impression he might be high maintenance and not someone who can be counted on to actually stick around in any job, but Reuters said: "In June, it lost one of its veteran chip designers, Jim Keller, over a dispute on whether the company should outsource more of its production, sources said at the time."I don't know if that means he was in favor of outsourcing more production, or opposed to it, or why either situation would cause him to leave... (https://www.reuters.com/article/us-intel-thirdpoin...
yeeeeman - Wednesday, January 27, 2021 - link
this bodes well for their future.Heck, even with these massive fab issues they stayed up there with AMD, barely losing to them in the high end while using 14nm process for 6 years and refreshing the same old Skylake design. If it ever was a company capable of doing that, it was Intel. Even after all these years they still have record revenues because the quality of the products is top notch. Sure, the specs are becoming more and more obsolete since you can compete several years with a fantastic silicon (Skylake), but at some point your competitors will catch-up and surpass you. Anyway, I recall that even Jim Keller said he was working on a 800+ OoO instruction window core. That is 3x the size of Tiger Lake and Zen 3. Bigger than the Apple M1 fat core. And I am guessing he was working on a 2023 product.
mode_13h - Thursday, January 28, 2021 - link
> they stayed up there with AMD, barely losing to them in the high end while using 14nm process for 6 years and refreshing the same old Skylake design.You're missing the drubbing Intel is taking on server and workstation chips. The only reason it's not far worse is that AMD is supply-constrained.
But also even Amazon and Ampere's ARM-based CPUs passed Intel by...