SerDes is modern lingo for a device that converts between serial (i.e. on a single wire) and parallel (i.e. on multiple wires) data transmission.
Every complex digital device, e.g. a CPU or a GPU, contains many SerDes, which convert between the internal parallel data transmission and the external serial data transmission, which is usually done on standardized serial interfaces, e.g. Ethernet, PCI Express, SATA, USB and others.
SerDes = Serializer / Deserializer. It's a thing used to take a wide data bus and shove it into a serial link, and then expand it out again on the other side.
Think about DDR or PCIE needing to take all their data an protocol stuff into a funnel just before it leaves the chip and goes out to the board, and then how it needs to expand out again when it gets to its destination.
I noticed from that article that Nvidia is using PAM4 signaling at only 50Gb / second though - so less than half of this Marvell announcement. While they both use PAM4 signaling, this is significantly faster for each link, and in N5.
I know this is great for 400G Ethernet, but why do we not have 5nm SerDes for 10GBse-T Ethernet to try and bring down power consumption per port? Are the 10G Ethernet market that small the is not worth the investment?
Your graph is crap. If the timing was 125ns, you'd be looking at something from Atari ST/AMiga era. It's more likely 125 ps. But what's a mere 1000x between friends ?
I've been designing chips with PAM4 for 5+ years. It's nothing new. It's nice to see more SERDES options to help break the BRCM monopoly on this. This one critical IP is why BRCM retains a lot of their ASIC customers and charges their extortionist rates. Still, it would take a incredibly brave silicon design team to roll the dice MRVL. Every cutting edge SERDES looks great on paper but falls way short when tape-out comes. Wipe that smug smile off your face BRCM.
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DigitalFreak - Tuesday, November 17, 2020 - link
Is SerDes anything like HerpDerp?Holliday75 - Tuesday, November 17, 2020 - link
A quick google search comes up empty.AdrianBc - Tuesday, November 17, 2020 - link
SerDes is modern lingo for a device that converts between serial (i.e. on a single wire) and parallel (i.e. on multiple wires) data transmission.Every complex digital device, e.g. a CPU or a GPU, contains many SerDes, which convert between the internal parallel data transmission and the external serial data transmission, which is usually done on standardized serial interfaces, e.g. Ethernet, PCI Express, SATA, USB and others.
chrysrobyn - Wednesday, November 18, 2020 - link
SerDes = Serializer / Deserializer. It's a thing used to take a wide data bus and shove it into a serial link, and then expand it out again on the other side.Think about DDR or PCIE needing to take all their data an protocol stuff into a funnel just before it leaves the chip and goes out to the board, and then how it needs to expand out again when it gets to its destination.
Mr Perfect - Tuesday, November 17, 2020 - link
"Regular readers may identify that NVIDIA’s RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Micron’s GDDR6X"No, sorry. I haven't read the 30 series Deep Dive yet. :P
Ryan is still doing one, right?
Mr Perfect - Tuesday, November 17, 2020 - link
Okay, I see PAM4 was discussed in the 30 series announcement briefing. Serves me right for being snarky.PeachNCream - Tuesday, November 17, 2020 - link
It doesn't make it any less funny, though it would be nice to see AT covering more high end components AND more low end/budget computers as well.kmob - Tuesday, November 17, 2020 - link
I noticed from that article that Nvidia is using PAM4 signaling at only 50Gb / second though - so less than half of this Marvell announcement. While they both use PAM4 signaling, this is significantly faster for each link, and in N5.azfacea - Tuesday, November 17, 2020 - link
the age of terabit Ethernet is here. meanwhile some1 at intel is strategizing "next Gen" motherboards w/ exciting gigabit ports and moar ME backdoorsksec - Wednesday, November 18, 2020 - link
I know this is great for 400G Ethernet, but why do we not have 5nm SerDes for 10GBse-T Ethernet to try and bring down power consumption per port? Are the 10G Ethernet market that small the is not worth the investment?Ditiris - Wednesday, November 18, 2020 - link
Pretty sure the time interval on that eye diagram should be 125 ps, not 125 ns.Brane2 - Thursday, November 19, 2020 - link
Your graph is crap.If the timing was 125ns, you'd be looking at something from Atari ST/AMiga era.
It's more likely 125 ps.
But what's a mere 1000x between friends ?
Spunjji - Thursday, November 19, 2020 - link
It's not their "graph", it's Micron's. Take it up with them.TimSyd - Saturday, November 21, 2020 - link
"Regular readers may identify that NVIDIA’s RTX 3090 uses PAM4 signaling (on N7) to enable over 1000 GB/s of bandwidth with Micron’s GDDR6X"The RTX 3000 series are all on Samsung 08 not TSMC N7, though Nvidia probably regrets that now ;)
ucwby - Monday, November 23, 2020 - link
I've been designing chips with PAM4 for 5+ years. It's nothing new. It's nice to see more SERDES options to help break the BRCM monopoly on this. This one critical IP is why BRCM retains a lot of their ASIC customers and charges their extortionist rates. Still, it would take a incredibly brave silicon design team to roll the dice MRVL. Every cutting edge SERDES looks great on paper but falls way short when tape-out comes. Wipe that smug smile off your face BRCM.