Do we know how those machines are distributed amongst TSMC sites worldwide? Curious how diversified they are against risks in Taiwan both natural (such as earthquakes) and unnatural (such as China).
In your article you mean "exposures" and not "layers"....i believe. The number of layers is not process related but a Foundry choice to address customers SOC complexity demand. Another matter are the exposures to have a good layer. Modern DUV based silicon (7nm class) require between three and four exposures on critical layers.
The real problem is that a true 5nm a single patterning of EUV could be not enough on critical layers with NA = 0.33. Looking at TSMC 5nm we can see that it is pretty conservative and the density absolutely is not a record this time. Intel is much more aggressive with 7nm and sure they need of two EUV exposures on critical layers. IMO this the reason of Intel delay on 7nm or this is why they will mix a less advanced TSMC/Samsung 5nm process with their leading edge (but expensive) 7nm. Looking at Ponte Vecchio, Intel will utilize their 7nm for cache to have a strong sram footprint reduction, leaving dirty logic to Foundries. Honestly these ASML machines are embarassing, they do not meet the foundries specifics, and i have suspect 5nm output will not be large as 7nm. 3nm looks a real disaster, 2nm a low output process for premium applications.
Any news about the lack of 24/7 availability of these EUV scanners?? Are already true the frequents stops of the scanners due lack of reliability in the long run? This could be a limiting factor for large volume or the reason why TSMC orders a so large number of scanners (backup machines).
"Looking at TSMC 5nm we can see that it is pretty conservative and the density absolutely is not a record this time. Intel is much more aggressive with 7nm and sure they need of two EUV exposures on critical layers."
Actually the projected transistor density of TSMC at 5nm and Intel at 7nm is not that different. Intel is expected to be more aggressive, sure, but not *much* more aggressive. They are targeting a doubling of density at 7nm versus 10nm So, for the highest density cell library of both nodes (which is used for uncore and I/O parts of the doe, *not* for logic) they will move from ~100 million transistors per mm² (MTr/mm²) to ~200 MTr/mm².
TSMC are targeting a transistor density of 173.1 MTr/mm² in the first (N5) iteration of their 5nm node (per SemiWiki anyway, see link below), but they will also release a second denser 5nm node iteration a few quarters later, as they always do, that will get even closer to Intel's 7nm node in density. While that might not be record setting compared to Intel's targets its release will definitely set a density record, by far, since Intel's 7nm node is not anywhere near ready and will rather compete with TSMC's 3nm node... which will be quite denser.
The company that is very conservative at 5nm is actually Samsung. Their 5LPE node will have a density of a mere 126.5 MTr/mm², which is barely denser than TSMC's (partly EUV using) 7nm+/7FFP node. That's because Samsung at 5nm are basically switching from DDB (double diffusion break) to SDB (single diffusion break) and that's it. That's the same change TSMC did with the second gen 7nm+ iteration of their 7nm node to increase density. So Samsung's 5nm node is basically going to be a slightly denser 7nm+ node. The above assume that the data of this article are valid : https://semiwiki.com/semiconductor-manufacturers/s...
Yeah, that’s a great question. I know that’s some bragging rights for their marketing department but it’s got to be raising some eyebrows around the world. Everyone is cheering on Intel’s downfall but we may not want all our eggs in the TSMC/ASML basket in 5 years.
as the author says, ASML currently has a monopoly on these kind of machines, so questions: 1 - are there other vendors for current/DUV machines? 2 - are there other vendors for EUV machines?
IOW, the bottleneck isn't TSMC. if it is true that ASML is the sole source for EUV (and, perhaps, best DUV?), it makes little difference which foundry has the machines, from a customer/cost point of view. since, I'd wager, capital amoritization is the driving cost of wafers, ASML's 'tax' will be built in wherever the wafer comes from.
These machines are insanely complex. They cost nearly $100 million each and are just one tool in a long chain of tools. As you saw in the article there are only a few humans in the world with the technical skills to set them up. Several machines are sitting unused waiting for this tiny group of humans to get round to setting them up.
The tech is insane - these machines work by throwing a tiny droplet of molten tin in the air on an excessively precise trajectory then vaporising it with intense lasers, collecting the light from the plasma (which damages everything it touches) and focusing it to make circuits tinier than anything made before. There are several stages, each of which loses 95%-98% of the power, so from a 500,000w wall supply, only 200w of light is output, and only about 4w of light actually arrives at the wafer to do the masking / lithography work.
ASML is basically supported by a joint agreement between every large chipmaker on the planet. It's not possible to have a second company making these machines, the capacity just isn't there and the expense is too high. Maybe in a few years time when ASML has moved onto creating whatever comes after EUV.
As for 1), Nikon sells 193nm (ArF) immersion scanners suitable for 7nm process technology. At a glance they look comparable to me to what ASML is selling, same resolution etc., but ASML has 90% or so market share there. As for 2) Nope. It has to be said EUV lithography was in development for well over 20 years (and talked about for like 30 years) at various places, and Nikon was investing in it too, but seems to have abandoned those plans quite a while ago. FWIW it's actually not just ASML alone which has a monopoly - key parts of these machines come from Zeiss (optics) and TRUMPF (laser) which aren't exactly typical off-the-shelf parts.
It depends on how you define "vendors". ASML are the only company that sell complete EUV machines, i.e. the deliver the entire package, ready to roll. However they do not make the entire thing themselves. Arguably the most important elements of the scanner are the optics and the EUV light source. Both are made by subcontractors. The optics by Zeiss and the light source by Cymer. EUV masks are also made by plenty of vendors, including ASML.
Yes, there are other DUV vendors, and I mean for the complete package. I think the only surviving ones are Nikon and Canon. Before ASML even existed these two were the big boys of this market; they are the old guard who used to compete with each other during the good ol' days. Then the newcomer ASML arrived and gradually ate almost their entire market share and eventually nearly drove them out of this market. I am lazy to look for hard numbers right now but I doubt you can fab any wafer at a denser node than ~28nm (Intel's 22nm) with a Nikon/Canon scanner. They have long stopped competing with ASML and do not intend to ever make their own EUV machines.
p.s. Cymer's light source could be replaced by that of another contractor - or they could dual source it. That's not where ASML's bottleneck lies though, so there is no need. The bottleneck that delays the delivery of their scanners, from what I've heard, is the optics. And no other company has the expertise and skilled experts to polish mirrors down to a precision of couple of nanometers *at scale* and within tight deadlines. This is why ASML have invested generously in Zeiss in the last decade or so.
The smoothness of the optics is important because it places a limit on how fine the features you print can ultimately be. DUV has much laxer requirements, but EUV requires extremely high precision due to its 13.5nm light and due to the switch from lenses to mirrors. As should be obvious there is a finite speed to how fast a mirror can be polished and still meet the target specs.
So, in all the manufacturing steps of the scanner starting from its design and ending up in assembly and testing, mirror polishing is a step that's an inherent bottleneck. The only to way to speed it up is to do it "in parallel", i.e. hire more mirror polishers (if you can find sufficiently skilled ones), give them more polishing machines to work with and so on. My guess is that this is what Zeiss have been doing to fulfill the high demand.
I realize your comment is meant entirely in jest, but GlobalFoundries and Samsung both have "14nm" nodes as well. Yeah, the 3 aren't equivalent but whatever.
High valuation is the only reason. You're a little late to the party. But that doesn't mean it isn't a good investment. Notice how the companies who design cutting-edge logic chips are stressing "it's the architecture that's important"? That's because it's getting more and more expensive to use the latest logic processes. They are sharing more and more of their revenue with the manufacturing services. And the manufacturing is capital intensive and takes a high degree of technical skill. So foundries and chip equipment makers will capture a greater percentage of the hardware pie. This is why it's important for chip companies to develop platforms to ensure profit margins. For a while now, server and PC makers have made hardly any profit, as all the profit goes to the makers of the chips that demand a lot of work to design, and because it's the chip makers that define the platform, not the server/PC makers. If that margin on chips gets siphoned off to foundries and chip equipment makers the chip makers will especially need vibrant platforms to maintain their margins, but the trend would be that chip equipment makers like ASML should benefit with secular growth and margin expansion.
I have been curious about the availability of EUV equipment based on the reported back log of EUV machines. If AMD, Intel or somebody else wants additional N6 or N5 wafers can TSMC provide them. Here is the comment from the last ASML quarterly conference.
'We are still planning at capacity of 45 to 50 systems next year. They just planned within our existing factory footprint by reducing cycle time in our factory to around 20 weeks by the end of this year, currently have a backlog of 54 systems with 28 system orders for 2021 delivery, covering over half of this capacity, and we expect orders to continue in the second half of the year in support of the 2021 demand.' (Sourced from SA Earnings Call Transcript.)
Based on the 28 machines scheduled for delivery in 2021 it looks like there are still 17-22 EUV machines that could be ordered for deliver in 2021. With a six month set up it could be 2022 before actual additional capacity is on line.
I worked for ASML for 9 years. install for another vendor now. installed and set up, integrated for customer. the wafer and reticle stages are under vacuum allowing them a cost saving by returning to the original interferometer om IMF. customer won't see that. Density wise intels 10 is better than tmsc's 7. I've been to fab 15. 18 wasn't built yet. I've been in Intel D1C,D,and X in building R4. Also fab42 which has capacity of 8 machines but only has 2. 8 are installed in Oregon D1X fab. EUV is all CO2 lasers. Trumph just pumps the signal through 5 separate amplifying cavities to acquire the need gain to reach 260W. But 4 watts at the wafer would burn at 10nm. so 4W using zernike indices they get the imaging down to mere Nanowatts actually being delivered to the photo resist. TSMC right now is smoke and mirrors. dont let the smaller figures fool you. Intel still has a much stronger architecture. With a consistent 99 percent yield TSMC still has some ground to make up.
Weird flexes at several points here: "Density wise intels 10 is better than tmsc's 7" This is not borne out in practice for die size vs. transistor count on Ice Lake or Lakefield. Intel had a theoretical density advantage which they had to burn to get the process to yield. They're notably not talking density for 10++/SF.
"Intel still has a much stronger architecture. With a consistent 99 percent yield TSMC still has some ground to make up." Eh? Intel's yields on 10nm are still dismal. 14nm yields are almost certainly better, but that's not much use when that process is significantly less dense.
I wonder how long it will be before free electron lasers are able to replace the current tin plasma source. (Starting with a laser source should allow a reduction in the number of mirror stages and elimination of plasma damage.)
the collectors in the projection optics box or the POB. thats in the immediate future. athe closer the wafer to the source the clearer the imaging and even closer overlay than 2nm I overlay is at now.
That was the reason why I speculate Intel's delay of 7nm has little to do with their own yield but installation of EUV. Not only are ASML no where near their target, the pandemic has stopped manufacturing of TwinScan for months. Which means there is no chance ASML will be able to catch up with those backlogs.
I speculate that it has to do with getting enough EUV for 7 nm plus an improvement in 10 nm. Intel made a major strategic error forgoing early use of EUV. They implied some years back that they had the option to go with it, i.e., they could have procured the needed machines, but they decided against it. It came along too late for their first attempt at 10 nm, but it looks like they even underestimated its importance for the 7 nm node, where they did plan to insert it from the beginning. Although ASML has been slightly slower than promised in turning out machines, they have been faster than promised in increasing the productivity of the machines. So it's not ASML delays that are to blame. It's Intel's decisions.
I'm not sure why you say the pandemic has stopped manufacturing of TwinScan for months. Do you have any source for that? That would be major news that should plummet ASML's stock. How could ASML have reported strong Q2 sales and a solid Q3 forecast on July 15 if their major product line were shut down? Here is what the CEO said about the pandemic during the July 15 conference call: "Although, we experienced some challenges early in the quarter around supply delays and increased absenteeism, we did not encounter any new disruptions due to COVID-19. We continue to operate with special measures in place around isolation and contamination protocols to ensure the safety of our employees and to reduce risk of operational disruption. Even though this created some initial inefficiencies and production delays, operations capabilities are largely back to normal."
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J0S3R - Thursday, August 27, 2020 - link
Do we know how those machines are distributed amongst TSMC sites worldwide? Curious how diversified they are against risks in Taiwan both natural (such as earthquakes) and unnatural (such as China).Ian Cutress - Thursday, August 27, 2020 - link
That should be as simple as asking which Fabs at TSMC do N7+, N5, or are leading-edge R&D.Gondalf - Saturday, August 29, 2020 - link
In your article you mean "exposures" and not "layers"....i believe.The number of layers is not process related but a Foundry choice to address customers SOC complexity demand. Another matter are the exposures to have a good layer.
Modern DUV based silicon (7nm class) require between three and four exposures on critical layers.
The real problem is that a true 5nm a single patterning of EUV could be not enough on critical layers with NA = 0.33. Looking at TSMC 5nm we can see that it is pretty conservative and the density absolutely is not a record this time. Intel is much more aggressive with 7nm and sure they need of two EUV exposures on critical layers.
IMO this the reason of Intel delay on 7nm or this is why they will mix a less advanced TSMC/Samsung 5nm process with their leading edge (but expensive) 7nm.
Looking at Ponte Vecchio, Intel will utilize their 7nm for cache to have a strong sram footprint reduction, leaving dirty logic to Foundries.
Honestly these ASML machines are embarassing, they do not meet the foundries specifics, and i have suspect 5nm output will not be large as 7nm. 3nm looks a real disaster, 2nm a low output process for premium applications.
Any news about the lack of 24/7 availability of these EUV scanners?? Are already true the frequents stops of the scanners due lack of reliability in the long run? This could be a limiting factor for large volume or the reason why TSMC orders a so large number of scanners (backup machines).
Santoval - Saturday, August 29, 2020 - link
"Looking at TSMC 5nm we can see that it is pretty conservative and the density absolutely is not a record this time. Intel is much more aggressive with 7nm and sure they need of two EUV exposures on critical layers."Actually the projected transistor density of TSMC at 5nm and Intel at 7nm is not that different. Intel is expected to be more aggressive, sure, but not *much* more aggressive. They are targeting a doubling of density at 7nm versus 10nm So, for the highest density cell library of both nodes (which is used for uncore and I/O parts of the doe, *not* for logic) they will move from ~100 million transistors per mm² (MTr/mm²) to ~200 MTr/mm².
TSMC are targeting a transistor density of 173.1 MTr/mm² in the first (N5) iteration of their 5nm node (per SemiWiki anyway, see link below), but they will also release a second denser 5nm node iteration a few quarters later, as they always do, that will get even closer to Intel's 7nm node in density. While that might not be record setting compared to Intel's targets its release will definitely set a density record, by far, since Intel's 7nm node is not anywhere near ready and will rather compete with TSMC's 3nm node... which will be quite denser.
The company that is very conservative at 5nm is actually Samsung. Their 5LPE node will have a density of a mere 126.5 MTr/mm², which is barely denser than TSMC's (partly EUV using) 7nm+/7FFP node. That's because Samsung at 5nm are basically switching from DDB (double diffusion break) to SDB (single diffusion break) and that's it. That's the same change TSMC did with the second gen 7nm+ iteration of their 7nm node to increase density. So Samsung's 5nm node is basically going to be a slightly denser 7nm+ node. The above assume that the data of this article are valid :
https://semiwiki.com/semiconductor-manufacturers/s...
Santoval - Saturday, August 29, 2020 - link
edit : "which is used for uncore and I/O parts of the doe ---> *die*"dotjaz - Monday, August 31, 2020 - link
N5P is not denser. And while Intel claims to have better density, there's no chip in existence to verify that.dotjaz - Monday, August 31, 2020 - link
What a stupid rant. Intel's 7nm is the inferior process.flgt - Thursday, August 27, 2020 - link
Yeah, that’s a great question. I know that’s some bragging rights for their marketing department but it’s got to be raising some eyebrows around the world. Everyone is cheering on Intel’s downfall but we may not want all our eggs in the TSMC/ASML basket in 5 years.FunBunny2 - Thursday, August 27, 2020 - link
"all our eggs in the TSMC/ASML basket in 5 years"as the author says, ASML currently has a monopoly on these kind of machines, so questions:
1 - are there other vendors for current/DUV machines?
2 - are there other vendors for EUV machines?
IOW, the bottleneck isn't TSMC. if it is true that ASML is the sole source for EUV (and, perhaps, best DUV?), it makes little difference which foundry has the machines, from a customer/cost point of view. since, I'd wager, capital amoritization is the driving cost of wafers, ASML's 'tax' will be built in wherever the wafer comes from.
Tomatotech - Thursday, August 27, 2020 - link
These machines are insanely complex. They cost nearly $100 million each and are just one tool in a long chain of tools. As you saw in the article there are only a few humans in the world with the technical skills to set them up. Several machines are sitting unused waiting for this tiny group of humans to get round to setting them up.The tech is insane - these machines work by throwing a tiny droplet of molten tin in the air on an excessively precise trajectory then vaporising it with intense lasers, collecting the light from the plasma (which damages everything it touches) and focusing it to make circuits tinier than anything made before. There are several stages, each of which loses 95%-98% of the power, so from a 500,000w wall supply, only 200w of light is output, and only about 4w of light actually arrives at the wafer to do the masking / lithography work.
ASML is basically supported by a joint agreement between every large chipmaker on the planet. It's not possible to have a second company making these machines, the capacity just isn't there and the expense is too high. Maybe in a few years time when ASML has moved onto creating whatever comes after EUV.
mczak - Thursday, August 27, 2020 - link
As for 1), Nikon sells 193nm (ArF) immersion scanners suitable for 7nm process technology. At a glance they look comparable to me to what ASML is selling, same resolution etc., but ASML has 90% or so market share there.As for 2) Nope. It has to be said EUV lithography was in development for well over 20 years (and talked about for like 30 years) at various places, and Nikon was investing in it too, but seems to have abandoned those plans quite a while ago.
FWIW it's actually not just ASML alone which has a monopoly - key parts of these machines come from Zeiss (optics) and TRUMPF (laser) which aren't exactly typical off-the-shelf parts.
Santoval - Saturday, August 29, 2020 - link
It depends on how you define "vendors". ASML are the only company that sell complete EUV machines, i.e. the deliver the entire package, ready to roll. However they do not make the entire thing themselves. Arguably the most important elements of the scanner are the optics and the EUV light source. Both are made by subcontractors. The optics by Zeiss and the light source by Cymer.EUV masks are also made by plenty of vendors, including ASML.
Yes, there are other DUV vendors, and I mean for the complete package. I think the only surviving ones are Nikon and Canon. Before ASML even existed these two were the big boys of this market; they are the old guard who used to compete with each other during the good ol' days. Then the newcomer ASML arrived and gradually ate almost their entire market share and eventually nearly drove them out of this market. I am lazy to look for hard numbers right now but I doubt you can fab any wafer at a denser node than ~28nm (Intel's 22nm) with a Nikon/Canon scanner. They have long stopped competing with ASML and do not intend to ever make their own EUV machines.
Santoval - Saturday, August 29, 2020 - link
p.s. Cymer's light source could be replaced by that of another contractor - or they could dual source it. That's not where ASML's bottleneck lies though, so there is no need. The bottleneck that delays the delivery of their scanners, from what I've heard, is the optics. And no other company has the expertise and skilled experts to polish mirrors down to a precision of couple of nanometers *at scale* and within tight deadlines. This is why ASML have invested generously in Zeiss in the last decade or so.The smoothness of the optics is important because it places a limit on how fine the features you print can ultimately be. DUV has much laxer requirements, but EUV requires extremely high precision due to its 13.5nm light and due to the switch from lenses to mirrors. As should be obvious there is a finite speed to how fast a mirror can be polished and still meet the target specs.
So, in all the manufacturing steps of the scanner starting from its design and ending up in assembly and testing, mirror polishing is a step that's an inherent bottleneck. The only to way to speed it up is to do it "in parallel", i.e. hire more mirror polishers (if you can find sufficiently skilled ones), give them more polishing machines to work with and so on. My guess is that this is what Zeiss have been doing to fulfill the high demand.
dotjaz - Monday, August 31, 2020 - link
Who are you to doubt Nikon/Intel? Intel has Nikon scanner for 14/10nm.https://www.nikon.com/news/2014/02_nsr-s630d_01.ht...
RU482 - Thursday, August 27, 2020 - link
lol, was just going to say "gonna suck when China invades"Freeb!rd - Thursday, August 27, 2020 - link
Fab 15 & Fab 18 both in Taiwan. Fab 18 was built for 5nm, Fab 15 for 7nm/7nm+(EUV)https://www.tsmc.com/english/campaign/N7plus/index...
TSMC fab locations:
https://www.tsmc.com/english/contact_us.htm#TSMC_f...
shabby - Thursday, August 27, 2020 - link
Intel: oh yeah? Well we have 100% of 14nm capacity!MrCommunistGen - Thursday, August 27, 2020 - link
I realize your comment is meant entirely in jest, but GlobalFoundries and Samsung both have "14nm" nodes as well. Yeah, the 3 aren't equivalent but whatever.alphasquadron - Thursday, August 27, 2020 - link
Can someone give me some reasons why I should NOT invest in ASML stock? They seem to be the only provider of a technology that everyone needs.SirMaster - Thursday, August 27, 2020 - link
Everyone needs?Seems like only 2-3 companies at most need them and only for so many years before the industry moves on to whatever comes after EUV.
If the couple compiles who use their machines aren’t expanding their production capacity then they aren’t going to order more machines from ASML.
LAZRJOCK - Friday, August 28, 2020 - link
What comes after EUV you ask? molecular level. Asml has nothing in the pipe line for that. A higher N.A. isnt going to do the trick then.catavalon21 - Thursday, August 27, 2020 - link
A high P/E ratio?Yojimbo - Saturday, August 29, 2020 - link
High valuation is the only reason. You're a little late to the party. But that doesn't mean it isn't a good investment. Notice how the companies who design cutting-edge logic chips are stressing "it's the architecture that's important"? That's because it's getting more and more expensive to use the latest logic processes. They are sharing more and more of their revenue with the manufacturing services. And the manufacturing is capital intensive and takes a high degree of technical skill. So foundries and chip equipment makers will capture a greater percentage of the hardware pie. This is why it's important for chip companies to develop platforms to ensure profit margins. For a while now, server and PC makers have made hardly any profit, as all the profit goes to the makers of the chips that demand a lot of work to design, and because it's the chip makers that define the platform, not the server/PC makers. If that margin on chips gets siphoned off to foundries and chip equipment makers the chip makers will especially need vibrant platforms to maintain their margins, but the trend would be that chip equipment makers like ASML should benefit with secular growth and margin expansion.oak8292 - Thursday, August 27, 2020 - link
I have been curious about the availability of EUV equipment based on the reported back log of EUV machines. If AMD, Intel or somebody else wants additional N6 or N5 wafers can TSMC provide them. Here is the comment from the last ASML quarterly conference.'We are still planning at capacity of 45 to 50 systems next year. They just planned within our existing factory footprint by reducing cycle time in our factory to around 20 weeks by the end of this year, currently have a backlog of 54 systems with 28 system orders for 2021 delivery, covering over half of this capacity, and we expect orders to continue in the second half of the year in support of the 2021 demand.' (Sourced from SA Earnings Call Transcript.)
Based on the 28 machines scheduled for delivery in 2021 it looks like there are still 17-22 EUV machines that could be ordered for deliver in 2021. With a six month set up it could be 2022 before actual additional capacity is on line.
LAZRJOCK - Friday, August 28, 2020 - link
I worked for ASML for 9 years. install for another vendor now. installed and set up, integrated for customer. the wafer and reticle stages are under vacuum allowing them a cost saving by returning to the original interferometer om IMF. customer won't see that. Density wise intels 10 is better than tmsc's 7. I've been to fab 15. 18 wasn't built yet. I've been in Intel D1C,D,and X in building R4. Also fab42 which has capacity of 8 machines but only has 2. 8 are installed in Oregon D1X fab. EUV is all CO2 lasers. Trumph just pumps the signal through 5 separate amplifying cavities to acquire the need gain to reach 260W. But 4 watts at the wafer would burn at 10nm. so 4W using zernike indices they get the imaging down to mere Nanowatts actually being delivered to the photo resist. TSMC right now is smoke and mirrors. dont let the smaller figures fool you. Intel still has a much stronger architecture. With a consistent 99 percent yield TSMC still has some ground to make up.Spunjji - Friday, August 28, 2020 - link
Weird flexes at several points here:"Density wise intels 10 is better than tmsc's 7"
This is not borne out in practice for die size vs. transistor count on Ice Lake or Lakefield. Intel had a theoretical density advantage which they had to burn to get the process to yield. They're notably not talking density for 10++/SF.
"Intel still has a much stronger architecture. With a consistent 99 percent yield TSMC still has some ground to make up."
Eh? Intel's yields on 10nm are still dismal. 14nm yields are almost certainly better, but that's not much use when that process is significantly less dense.
Duncan Macdonald - Friday, August 28, 2020 - link
I wonder how long it will be before free electron lasers are able to replace the current tin plasma source. (Starting with a laser source should allow a reduction in the number of mirror stages and elimination of plasma damage.)LAZRJOCK - Friday, August 28, 2020 - link
the collectors in the projection optics box or the POB. thats in the immediate future. athe closer the wafer to the source the clearer the imaging and even closer overlay than 2nm Ioverlay is at now.
LAZRJOCK - Friday, August 28, 2020 - link
Plus they ate always looking at different coatings for the mirrors to help with that exact reason.Anymoore - Friday, August 28, 2020 - link
They've been running 1000-1500 wpd (at most ~60 wph effectively).ksec - Friday, August 28, 2020 - link
That was the reason why I speculate Intel's delay of 7nm has little to do with their own yield but installation of EUV. Not only are ASML no where near their target, the pandemic has stopped manufacturing of TwinScan for months. Which means there is no chance ASML will be able to catch up with those backlogs.Yojimbo - Saturday, August 29, 2020 - link
I speculate that it has to do with getting enough EUV for 7 nm plus an improvement in 10 nm. Intel made a major strategic error forgoing early use of EUV. They implied some years back that they had the option to go with it, i.e., they could have procured the needed machines, but they decided against it. It came along too late for their first attempt at 10 nm, but it looks like they even underestimated its importance for the 7 nm node, where they did plan to insert it from the beginning. Although ASML has been slightly slower than promised in turning out machines, they have been faster than promised in increasing the productivity of the machines. So it's not ASML delays that are to blame. It's Intel's decisions.I'm not sure why you say the pandemic has stopped manufacturing of TwinScan for months. Do you have any source for that? That would be major news that should plummet ASML's stock. How could ASML have reported strong Q2 sales and a solid Q3 forecast on July 15 if their major product line were shut down? Here is what the CEO said about the pandemic during the July 15 conference call: "Although, we experienced some challenges early in the quarter around supply delays and increased absenteeism, we did not encounter any new disruptions due to COVID-19. We continue to operate with special measures in place around isolation and contamination protocols to ensure the safety of our employees and to reduce risk of operational disruption. Even though this created some initial inefficiencies and production delays, operations capabilities are largely back to normal."