I'm not expecting it to bring costs down year on year but I am expecting it to allow significant effective layer scaling with less-than-linear cost scaling. ie we will see $10,000 chips for the datacenter with 4x as many transistors on 2x as many layers for the same cost as today's $10,000 chips.
I sorely doubt we'll see an i9 / Ryzen 9 product with 8 HBM stacks in 2021, at any price point.
Well CoWoS-S (silicon interposer) was costing $30 for sub-reticle interposers to over $100 for larger ones. Additionally, the chips to be mounted are mounted on the interposer wafer, so I guess there's some yield waste from poor assembly, poor interposers, and so on.
RDLs are organic assembled interposers, and are around $3 for the same size. The LSIs will be very simple cheap silicon bridges. The assembly of the LSIs and RDLs and 'filler with TSVs' and so on looks complex of course, hence it's taken some time to come to market.
Indeed - after a year or two I'd be hopeful of seeing an APU with console-level performance thanks to some on-package HBM acting as L4 / dedicated graphics RAM.
5nm Epyc isn't on the roadmap until 2023, which is the 4 chiplet + 12 HBM roadmap from TSMC. So we might see TR and EPYC Frequency-optimised products using this in 2023. The problem is that power scale savings from 7nm to 5nm is quite small, ie <18% so that's not going to very easily increase the core budget, but it should allow a modest frequency bump, and treating the HBM like an L4 cache should help with the poor SRAM scaling.
CoWoS-S doesn't really get described well. It might be a chip-sized RDL just to aid I/O placement+routing on the chip before it is attached to the substrate. RDLs are very thin because of the TSVs.
What we know as a standard interposer (logic+hbm typically): CoWoS-R (R=redistribution layer, with 6 layers of routing in the interposer). Multiple chips are attached to the interposer when it's on the wafer. The wafer is then thinned to expose TSVs and become quite thin, then it is cut and assembled to the substrate.
This article is about CoWoS-L - and besides the LSI bridges, it has *LOTS* of tiny thin RDLs hosted in a 'molding' which itself has through interposer vias. The LSI is mounted to the substrate using CoWoS-S, the TIVs and their small RDLs are also assembled, the molding is added, then the main logic dies on top. The LSI may contain active logic. LSI is thicker than RDL.
-S is what I wrote as -R with the thin Si interposer and chip-first assembly. -R is the version using an RDL, which is an organic interposer: https://semiengineering.com/return-of-the-organic-... (so calling it Chip *on Wafer* on Substrate is not really correct here. Should be CoRoS. Anyway, this is chip-last.
Thanks, yes I corrected myself above for the descriptions. One issue is that CoWoS-R is actually missing the "oW' part, it's 'oR' but I guess they didn't want to confuse branding any more than it is already confusing to outsiders. It sounds to me that RDLs will cut prices a lot for this type of packaging.
I meant to write but messed it up (tiredness) "mounted to the substrate in a compatible manner to CoWoS-S" as TSMC's website mentions - the compatibility will aid uptake I'm sure.
If the LSI die has TSVs (needed to uBump on the bottom), seems more like Intel's Foveros than EMIB. As far as I know, EMIB does not have TSVs. Plus EMIB is embedded in a substrate and not in epoxy. The TIVs are similar to Intel's Omni Directional Interconnect (ODI).
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jeremyshaw - Tuesday, August 25, 2020 - link
Finally, something like EMIB has been lacking from 3rd party foundries. Hopefully this can help bring the cost of HBM-type systems down.linuxgeex - Wednesday, August 26, 2020 - link
I'm not expecting it to bring costs down year on year but I am expecting it to allow significant effective layer scaling with less-than-linear cost scaling. ie we will see $10,000 chips for the datacenter with 4x as many transistors on 2x as many layers for the same cost as today's $10,000 chips.I sorely doubt we'll see an i9 / Ryzen 9 product with 8 HBM stacks in 2021, at any price point.
psychobriggsy - Wednesday, August 26, 2020 - link
Well CoWoS-S (silicon interposer) was costing $30 for sub-reticle interposers to over $100 for larger ones. Additionally, the chips to be mounted are mounted on the interposer wafer, so I guess there's some yield waste from poor assembly, poor interposers, and so on.RDLs are organic assembled interposers, and are around $3 for the same size. The LSIs will be very simple cheap silicon bridges. The assembly of the LSIs and RDLs and 'filler with TSVs' and so on looks complex of course, hence it's taken some time to come to market.
mdriftmeyer - Monday, August 31, 2020 - link
You'll be happily wrong. 2021 is Zen 4 and the first 2.5/3D process node design for them, thus there will be 8 HBM2e stacks in 2021.Spunjji - Wednesday, August 26, 2020 - link
Indeed - after a year or two I'd be hopeful of seeing an APU with console-level performance thanks to some on-package HBM acting as L4 / dedicated graphics RAM.TimSyd - Tuesday, August 25, 2020 - link
So how soon are we betting AMD will be discussing this for next gen EPYC? (Genoa etc):)
jeremyshaw - Tuesday, August 25, 2020 - link
Hopefully reducing the power penalty of Infinity Fabric?TimSyd - Tuesday, August 25, 2020 - link
Lower power & higher clocks ideally (for lower latency) :)linuxgeex - Wednesday, August 26, 2020 - link
5nm Epyc isn't on the roadmap until 2023, which is the 4 chiplet + 12 HBM roadmap from TSMC. So we might see TR and EPYC Frequency-optimised products using this in 2023. The problem is that power scale savings from 7nm to 5nm is quite small, ie <18% so that's not going to very easily increase the core budget, but it should allow a modest frequency bump, and treating the HBM like an L4 cache should help with the poor SRAM scaling.Spunjji - Wednesday, August 26, 2020 - link
Those would seem like the obvious benefits. Exciting stuff! :DValantar - Wednesday, August 26, 2020 - link
Hm, I thought EMIB embedded _into_ the substrate, not into a layer on top of the substrate. Have I misunderstood this all along?anonomouse - Sunday, August 30, 2020 - link
You're correct, this is different. Here the local silicon appears to be integrated with the RDL.psychobriggsy - Wednesday, August 26, 2020 - link
It's good that a smaller silicon interconnect option is becoming available at TSMC. The large silicon interposers never came down in price it seems.TSMC have a lot of information here, that still might not clear everything up:
https://3dfabric.tsmc.com/english/dedicatedFoundry...
CoWoS-S doesn't really get described well. It might be a chip-sized RDL just to aid I/O placement+routing on the chip before it is attached to the substrate. RDLs are very thin because of the TSVs.
What we know as a standard interposer (logic+hbm typically): CoWoS-R (R=redistribution layer, with 6 layers of routing in the interposer). Multiple chips are attached to the interposer when it's on the wafer. The wafer is then thinned to expose TSVs and become quite thin, then it is cut and assembled to the substrate.
This article is about CoWoS-L - and besides the LSI bridges, it has *LOTS* of tiny thin RDLs hosted in a 'molding' which itself has through interposer vias. The LSI is mounted to the substrate using CoWoS-S, the TIVs and their small RDLs are also assembled, the molding is added, then the main logic dies on top. The LSI may contain active logic. LSI is thicker than RDL.
psychobriggsy - Wednesday, August 26, 2020 - link
Ugh, need an edit function here.-S is what I wrote as -R with the thin Si interposer and chip-first assembly.
-R is the version using an RDL, which is an organic interposer: https://semiengineering.com/return-of-the-organic-... (so calling it Chip *on Wafer* on Substrate is not really correct here. Should be CoRoS. Anyway, this is chip-last.
Andrei Frumusanu - Wednesday, August 26, 2020 - link
CoWoS-S is just using a standard interposer and no RDL whatsoever;> What we know as a standard interposer (logic+hbm typically): CoWoS-R
No, incorrect. There's no interposer at all here. I'm not aware of talked about -R products that I could use as an example.
> The LSI is mounted to the substrate using CoWoS-S
That sentence makes no sense. -S describes the use of an interposer, which is not present in -L.
psychobriggsy - Wednesday, August 26, 2020 - link
Thanks, yes I corrected myself above for the descriptions. One issue is that CoWoS-R is actually missing the "oW' part, it's 'oR' but I guess they didn't want to confuse branding any more than it is already confusing to outsiders. It sounds to me that RDLs will cut prices a lot for this type of packaging.I meant to write but messed it up (tiredness) "mounted to the substrate in a compatible manner to CoWoS-S" as TSMC's website mentions - the compatibility will aid uptake I'm sure.
rchidambaram - Wednesday, August 26, 2020 - link
If the LSI die has TSVs (needed to uBump on the bottom), seems more like Intel's Foveros than EMIB. As far as I know, EMIB does not have TSVs. Plus EMIB is embedded in a substrate and not in epoxy. The TIVs are similar to Intel's Omni Directional Interconnect (ODI).