Looks like N5 is going to be a wonderful node for TSMC. Like you said Ian I'm sure removing quad patterning helped yields. Also switching to EUV the "lines" drawn are less fuzzy which will lead to better power and I have to assume higher frequencies at least higher frequencies on average. That last part is the killer for AMD right now as only 1-2 cores are able to hit rated frequencies and I'm pretty certain its due to quad patterning but do not know that for fact.
It'll be phenomenal for NVIDIA. They're currently at 12nm for RTX, where AMD is barely competitive at TSMC's 7nm. I've heard rumors that Ampere is going to 7nm, which is going to keep them ahead of AMD probably even at 5nm. I have no clue what NVIDIA is going to do with the extra die space at 5nm... other than more RTX cores I guess.
All the rumors suggest that nVidia went with Samsung, not TSMC.
The reason is, they tried to play hardball with TSMC, and wanted lower prices. They threatened to leave to Samsung if they didn't get their way.
Obviously, TSMC was smart enough to tell them to fuck right off, and by the time they realized Samsung's node was hot garbage compared to TSMC, it was too late... there was no capacity left.
Rumors also say, that they do have enough capacity in lockdown for 5nm...
So as big as an upgrade ampere is going to be (which would'be been at least 20% larger on TSMC) compared to Turing, it will be very short lived, since they can either to a 7nm refresh on TSMC, or better yet, a 5nm GPU sometime next year.
Things haven't been this interesting in at least a decade... 2020-2022 are going to be huge. Hopefully they can keep the momentum going for longer than that though.
The rumor is based on them having a contract with samsung in 2019. There's no rumor that TSMC has no capacity for nvidia's chips. A100 is already on 7nm from TSMC, so it's pretty much confirmed TSMC is working with nvidia on ampere. Only thing up in the air is whether some ampere chips from their gaming line will be produced by samsung instead.
"Only thing up in the air is whether some ampere chips from their gaming line will be produced by samsung instead."
That's not what is being said...
That was their plan, but trying to play hardball with TSMC backfired, and the rumor is that they just wouldn't be able to make enough gaming chips on TSMC.
The early rumor was that the low end graphics cards would be on Samsung, and all of the high end chips would be on TSMC. But apparently, that didn't work out, and they're going to have to make everything on Samsung's significantly inferior node.
There's a reason the cooler on the 3090 is a mammoth (which would be a good idea for ALL cards IMO, since it would help with noise control) and it's not just to keep the card quiet...
The card will require 3, 8 pin connectors. The node is bad, so they'll have to put a lot of power in to get to the performance target they want.
So all of the TSMC capacity will go to the highest paying customers (A100 buyers) and the rest of us are going to get second hand stuff.
Nvidia IS on TSMC, but they're obviously using all their allocation to produce A100s. They have at least six supercomputer projects contracted to use A100, and each of those will need thousands of chips.
Obviously they'll prioritize their big expensive HPC chip with huge margins over the consumer stuff which is why RTX3000 gets booted to Samsung 8nm. I'd expect a 3000 Super built on TSMC a year from now after demand for A100 is filled and Nvidia can use their allocation for something else.
Currently, the manufacturer is nothing more than rumors. The only available facts are: - GA100 is manufactured on TSMCs N7 - NV also hat 8LPP capacity ordered and e. g. it is known, that the Orin SoC is going to be manufactured in 8LPP - J.Huang stated in December, that most of the new GPUs will be manufactured at TSMC, Samsung will only handle the smaller part
"-- J.Huang stated in December, that most of the new GPUs will be manufactured at TSMC, Samsung will only handle the smaller part"
Yeah, that was the plan... but it din't work out for them, they got greedy, but probably won't get punished by consumers since it will still be a huge upgrade over the current linup.
I'm hoping that AMD does enough to punish them for us though, Big Navi should give the regular 3080 a run for it's money.
We'll see. Between gains from architectural changes and N7P, RDNA 2 should be in a better position to compete with Nvidia than RDNA was.
A lot depends on whether or not the rumours of Ampere being built on Samsung 8nm are true, though, along with how competitive that process actually is.
Also, AMD do build CPUs too... and APUs. Those are going to rock on 5nm with mature DDR5 speeds.
Looks like 7nm didn't really get any better than the 0.09 figure for a long time, the first graph shows an improvement starting at Q6 and getting below 0.09 by Q8, but the second graph doesn't go beyond that (but shows good figures for N7+/N6).
Also I thought TSMC were not going to use N7+ name any longer, yet there it is on that first graph.
The problem started when customers were using N7+ to mean 'beyond 7nm but still on DUV', which was then called N7P (or perhaps just enhanced versions of N7).
To be fair I think he isn't saying that N7+ isn't EUV but that it is not compatible with N7, while N6 provides an almost seamless upgrade from N7 with the same benefits as N7+. So it's more correct to say that N6 is the EUV version of N7.
It's not all about money. AMD are a dedicated TSMC-only customer right now, whereas Intel are a high risk of only being a fly-by customer until they sort their own issues out. That factors heavily into allocation decisions.
According to Bloomberg, Intel has ordered 180,000 wafers in N6 for 2021. To bring this in context, they also stated that AMD had a 7 nm volume of about 200,000 wafers in 2019 at TSMC.
I'm not sure that does necessarily bring things into context, though - we'd need to see AMD's 2021 numbers for 7nm and 5nm. They've done a fair bit of growing since 2019.
Nah. AMD has more wafer volume & spends more at TSMC that Apple - do the math on AMD's multiple hi-volume products per technology node (3-5 different APU's & counting, CPU chiplets, GPU's etc) vs Apples single/dual product per node (iPhone & iPad). Though of course Apple's aggressive SoC roadmaps help TSMC learn & pay for initial node ramps at each technology generation :)
Where did you get that information from? It’s very doubtful. Apple buys well over 200 million chips a year from TSMC. Additionally, TSMC receives equipment from Apple.
Apple's probably bigger, but between their multi-die CPUs, their GPUs, their APUs, their console chips, AMD's still making a ton of dies with TSMC. They did collaborate on a semi-custom node, after all.
There's some nuance to be had here though. Apple is likely still TSMC's biggest customer, and the one most willing to pay whatever is needed for first access, but AMD shouldn't be that far behind in terms of volume, at least in the immediate future. How? Apple's SoCs are generally below 100mm2 (often quite a lot below). AMD' s CCDs are small, but they also make GPUs and console SoCs - and the latter are going to need a lot of wafers in the next couple of years. 20 million console SoCs - a likely sales number at least for the first year or two - would likely require as many wafers as something like a quarter of Apple's phone and tablet SoCs. Then there's consumer and datacenter GPUs, the vast majority of which will also be on the large side, and the ever growing sales of Ryzen. In other words, there's reason to believe that AMD is getting close to Apple in terms of sheer wafer volume.
Every SoC Apple designs (iPhone, iPad, iPad Pro, AirPods, HomePod, Watch) is manufactured by TSMC. That's approximately 250 million devices per year. And AMD doesn't contract out to only TSMC. They also contract out to GlobalFoundries.
TSMC makes more for Apple than just SoCs. They make Apple’s video controller chips, the t2 for Macs, various other sensor and controller chips. Over all, the number is easily close to, if not more than 300 million. It’s not just number of wafers that determine value. That’s an oversimplification.
Not sure about volume for each company. But in terms of projected revenue for 2021, Apple is paying TSMC about $11 billion USD almost 1/3 of TSMC's total revenue. giving them 1st place by a long shot. 2nd place is AMD with projected revenue share of $4.6 billion USD. Then there are a bunch of $2 and 3billions customers, including Broadcom, Qualcomm, Nvidia ... etc.
Really unlikely to happen. TSMC & AMD work well together & TSMC isnt likely to shaft a major customer like that. Bad form, bad precedent for other customers & not the way they do business. Fastest way to encourage your customers to get serious abt spending money to help Samsung/UMC or GF get in the game is to shaft them publicly. It *will* mean TSMC can push AMD higher on wafer pricing because they can use the Itel wafer allocation as a bargaining chip in the next round of pricing contract. Now that is much more TSMC's style.
TSMC has already said that they see Intel as a short-term partner (a "rescuer", they said, where Intel would make some big orders and then drop them when their own fabs get back on track). Even if Intel offered more money for capacity, I really doubt they'd shortchange a long-term customer to satisfy a short-term one.
TSMC is already production constrained. Their existing customers will use up as much fab capacity as they can build. They're not desperate for more business.
Yes, Intel will spend billions on it's fabs and spend more money to secure wafers from TSMC. Ever thought of the impact on gross margins and profitability? I hope Intel gets back on track but come on, don't be such a shill.
The things people say... Like you literally should've thought about that before you decided to type that. Why would they care about Intel their main competitor and their chip woes to allow them to leapfrog a consistent customer in AMD who will be with them for the long run. Like someone said its not about money in this situation. Besides AMD already secured wafers for 7nm and 5nm as from what I heard TSMC is making AMD 5nm more specifically tuned to their architecture.
Intel isn’t really a competitor. Samsung is a competitor. Intel produces their own chips, and just does a small fab business, while Samsung has a much bigger fab business. TSMC is entirely a fab business.
Right? The wishfull thinking and their whole “logic” is annoying the living hell out of me. AMD this, TSMC that. It’s a bussiness and money, not AMD, has the last word.
It’s amazing that people only seem to get out of statements what they want to. Intel said that CPUs would not be fabled, but some other chips likely would be. Nobody knows what the future will hold, but we can only go by what we’re told. It would be good to keep that in mind.
Not really. Not without pissing off their shareholders. "Please tell us again why you spent billions on fabs and then paid hugely over the odds for 3rd party fab access?"
I dont understand why people are still saying this and especially with the 10nm comparison to 7nm. The reason Intel cant get their nodes right is because they were over-ambitious. Thus they've had to lower their ambitions and tone it down. For example their revised 10nm no longer appears to be similar to TSMC 7nm because they had to tone it down for it to actually yield anything worthwhile. So im very skeptical of their 7nm being similar to TSMC 5nm. Whose to say their 7nm wont be scaled down due to certain difficulties/delays.. I'm just really skeptical about Intel and their claims these days
Those people are just copy-pasting the same logic that used to apply to Intel's 32nm and 22nm nodes, whether it be through ignorance or a calculated appeal to the ignorance of others.
I'll be interested to see what density and performance looks like on TGL when it finally releases - I'm curious as to whether this "superfin" stuff they're bragging about came at the expense of density. That would rely on them being honest about transistor count, though...
Maybe this means the pricing on the N5 won't be insane. It'll be nice if its comparable to N7 but probably won't be for 5 yrs....nevertheless great work!
The article & graphs show a timeline more like 5qtrs not 5yrsd. Where on earth did you get that idea?
N5 *will* be expensive. Lots of EUV isn't cheap & throughput will be lower that they'd like. Both mean more $$ per wafer. I expect north of $15k/wafer easily though maybe volume/favoured customer discounts will pull that down below $12k/wafer mark.
This is absolutely fascinating; defect-density curves with numbers on them are I think actually unprecedented (iirc Intel once provided a handout with numbers on but all the reporting of it was very quickly taken down). And that a mature process sticks at 0.1 defect per square centimetre (IE about 40% fully functioning 800mm^2 chips) for a year surprises me a lot, but possibly TSMC has finitely many fab engineers and would prefer to use them on getting the defect densities for newer processes down to a level they consider liveable with.
Yeah, 47% perfect dies for a chip of that size is absolute gangbusters. At that rate you're not even getting a clear majority of second-tier usable chips from each wafer, which is an interesting problem to have.
Holy crap... these guys are on fire. Who ever made the choice at nVidia to go with Samsung instead of TSMC for Ampere should be fired, re-hired, and fired again.
Nvidia's architecture is so far ahead of the game that they just don't need the best fab process, they can use a lesser one and still kick AMD's and Intel's asses with ease.
Nvidia's technical prowess is really a testament to Jensen Huang leadership skills. When most companies dominate their respective markets, they get complacent. Nvidia has managed to keep innovating while dominating the competition. I wish I could say the same for Intel. Perhaps there is a cultural aspect that contributes to the high levels of innovation over at Nvidia.
Intel have to focus on both manufacturing and chip design, which probably doesn't help with how bloated their corporate structure has become. They also came of age with an effective monopoly and extended it through anti-competitive shenanigans and marketing, so there's been no real incentive for them to be any other way - they can always bully competitors out of their core markets whenever things get dicey for them.
Nvidia, on the other hand, had to compete in a much more competitive market for a longer time, and have always focused much more keenly on graphics processor design. When they've tried to diversify it hasn't been so great (Tegra), and they've had some hilarious missteps directly overseen by Huang (wood screws!), but they appear to have actually learned from that and refocused back on core competencies. Even so, they've had their own share of anti-competitive and anti-consumer practices, and I do worry that this has been worsening noticeably in the past few years.
That is one weird rationalisation for a stupid decision. "We could have had an even better product, but we're so awesome that we decided not to" 🤡
You're probably right about their architecture. We'll see what Ampere brings, but unless it fails to move the bar much from Turing, it should keep them well in the lead at the high-end.
Honestly, I'd accept that response if I could see figures to back it up, but we don't have access to them. Speaking theoretically, I'd be very surprised if manufacturing such massive power-hungry chips on a less-dense process weren't costing them significantly in terms of yields. It's already clear they've blown the power budget too, but for some reason nobody cares about that? All in all, I'm getting big Fermi vibes from this generation.
Whether or not AMD are able to repeat the feat ATi managed back then of introducing a more power-efficient and cost-effective design to counter Nvidia's juggernaut remains to be seen, though. I have hope but anticipate disappointment.
That's the wrong way to look at it. Defect density is defects per unit area. TSMC has shown a 45% reduction in area for N5 vs N7. That means the number of defects relative to the number of transistors is actually ~1/2 that compared to N7 at the same density. So it's more that ~0.1 is the floor for some other reason. It may simply be that TSMC actually have set 0.1 as their acceptable target and don't push hard on it after the fact, focusing more on power and area improvements to get meaningful gains in performance. You have to factor in the diminishing returns of pumping more money into R&D for only a small improvement in yields vs getting the next process out the door. Meanwhile, most customers are just happy to have double the transistor budget or double the yields per wafer, along-side the improvements in power and/or frequency, compared to the old node.
No. These plots look like classic diminishing returns. Even their prediction line for N5 doesn't show significant improvement in the future. It's far more likely that they have a very rigorous internal schedule with predictable process maturity. Once it gets to a certain point internally they begin ramping production. It probably takes about 9-12 months on average after that point to dial in the process to these kinds of defect densities, at which point they stop trying to make significant improvements and focus on higher wafer throughput instead. TSMC has maintained that they saw much better yields on N5 out of the gate than N7. This just means they were able to start ramping earlier than they expected (ie. starting their 3-4Q long process tuning). I don't think they actually hit any significant issues that stopped them improving, just that it's "good enough" for mass production and any further improvements are expensive to make and pull resources away from the next process node. It's more important that they get the current process churning out wafers and get the next process moving along than it is to keep chasing defect density. They realized a long time ago that smaller feature size more than makes up for not chasing higher yields. Like I said, N5 at the same defect density at N7 has a much lower defect rate for the same transistor budget.
They are consistent. The first plot starts at -2Q, the second starts at -3Q. They added N10 in the second plot which had much higher defect density. This changes the linear scale limits (mainly maximum) for the Y-axis.
The second graph is literally just a zoomed-in segment of the first with a trend line and y-axis labelling added in.
When you say "approaching convergence", that's just a guess - there's no way to know from the information they have provided whether the lines will converge or remain separate. They're predicting the latter, but then they would. So 🤷♂️
That wiki chip link mentions that tsmc focused on hpc for the first 5nm iteration rather than their usual LP. That may account for the difference in defect rates between 7 & 5.
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FreckledTrout - Tuesday, August 25, 2020 - link
Looks like N5 is going to be a wonderful node for TSMC. Like you said Ian I'm sure removing quad patterning helped yields. Also switching to EUV the "lines" drawn are less fuzzy which will lead to better power and I have to assume higher frequencies at least higher frequencies on average. That last part is the killer for AMD right now as only 1-2 cores are able to hit rated frequencies and I'm pretty certain its due to quad patterning but do not know that for fact.psychobriggsy - Tuesday, August 25, 2020 - link
Marvell claim that TSMC N5 improves power by 40% at iso-performance even, from their work on multiple design ports from N7.https://semiaccurate.com/2020/08/25/marvell-talks-...
FreckledTrout - Tuesday, August 25, 2020 - link
Interesting read. The N5 node is going to do wonders for AMD.michael2k - Tuesday, August 25, 2020 - link
It'll be phenomenal for NVIDIA. They're currently at 12nm for RTX, where AMD is barely competitive at TSMC's 7nm. I've heard rumors that Ampere is going to 7nm, which is going to keep them ahead of AMD probably even at 5nm. I have no clue what NVIDIA is going to do with the extra die space at 5nm... other than more RTX cores I guess.Kamus - Tuesday, August 25, 2020 - link
All the rumors suggest that nVidia went with Samsung, not TSMC.The reason is, they tried to play hardball with TSMC, and wanted lower prices. They threatened to leave to Samsung if they didn't get their way.
Obviously, TSMC was smart enough to tell them to fuck right off, and by the time they realized Samsung's node was hot garbage compared to TSMC, it was too late... there was no capacity left.
Rumors also say, that they do have enough capacity in lockdown for 5nm...
So as big as an upgrade ampere is going to be (which would'be been at least 20% larger on TSMC) compared to Turing, it will be very short lived, since they can either to a 7nm refresh on TSMC, or better yet, a 5nm GPU sometime next year.
Things haven't been this interesting in at least a decade... 2020-2022 are going to be huge. Hopefully they can keep the momentum going for longer than that though.
whatthe123 - Tuesday, August 25, 2020 - link
The rumor is based on them having a contract with samsung in 2019. There's no rumor that TSMC has no capacity for nvidia's chips. A100 is already on 7nm from TSMC, so it's pretty much confirmed TSMC is working with nvidia on ampere. Only thing up in the air is whether some ampere chips from their gaming line will be produced by samsung instead.Kamus - Thursday, August 27, 2020 - link
"Only thing up in the air is whether some ampere chips from their gaming line will be produced by samsung instead."That's not what is being said...
That was their plan, but trying to play hardball with TSMC backfired, and the rumor is that they just wouldn't be able to make enough gaming chips on TSMC.
The early rumor was that the low end graphics cards would be on Samsung, and all of the high end chips would be on TSMC. But apparently, that didn't work out, and they're going to have to make everything on Samsung's significantly inferior node.
There's a reason the cooler on the 3090 is a mammoth (which would be a good idea for ALL cards IMO, since it would help with noise control) and it's not just to keep the card quiet...
The card will require 3, 8 pin connectors. The node is bad, so they'll have to put a lot of power in to get to the performance target they want.
So all of the TSMC capacity will go to the highest paying customers (A100 buyers) and the rest of us are going to get second hand stuff.
JlHADJOE - Wednesday, August 26, 2020 - link
Nvidia IS on TSMC, but they're obviously using all their allocation to produce A100s. They have at least six supercomputer projects contracted to use A100, and each of those will need thousands of chips.https://www.hpcwire.com/2020/08/19/microsoft-azure...
Obviously they'll prioritize their big expensive HPC chip with huge margins over the consumer stuff which is why RTX3000 gets booted to Samsung 8nm. I'd expect a 3000 Super built on TSMC a year from now after demand for A100 is filled and Nvidia can use their allocation for something else.
https://videocardz.com/newz/nvidia-a100-ampere-ben...
AnGe85 - Wednesday, August 26, 2020 - link
Currently, the manufacturer is nothing more than rumors. The only available facts are:- GA100 is manufactured on TSMCs N7
- NV also hat 8LPP capacity ordered and e. g. it is known, that the Orin SoC is going to be manufactured in 8LPP
- J.Huang stated in December, that most of the new GPUs will be manufactured at TSMC, Samsung will only handle the smaller part
Kamus - Thursday, August 27, 2020 - link
"-- J.Huang stated in December, that most of the new GPUs will be manufactured at TSMC, Samsung will only handle the smaller part"Yeah, that was the plan... but it din't work out for them, they got greedy, but probably won't get punished by consumers since it will still be a huge upgrade over the current linup.
I'm hoping that AMD does enough to punish them for us though, Big Navi should give the regular 3080 a run for it's money.
Spunjji - Wednesday, August 26, 2020 - link
We'll see. Between gains from architectural changes and N7P, RDNA 2 should be in a better position to compete with Nvidia than RDNA was.A lot depends on whether or not the rumours of Ampere being built on Samsung 8nm are true, though, along with how competitive that process actually is.
Also, AMD do build CPUs too... and APUs. Those are going to rock on 5nm with mature DDR5 speeds.
TristanSDX - Wednesday, August 26, 2020 - link
do not this so. Defect rate may only increase profits, and TSMC will eat it completely (good yield -> higher price / wafer for AMD)WaltC - Tuesday, August 25, 2020 - link
You're only talking about single-core boost frequencies--by design.Anymoore - Wednesday, August 26, 2020 - link
EUV has more stochastic fuzziness actually.plopke - Tuesday, August 25, 2020 - link
..., so my replacing 4 steps of DUV for 1 step of EUV, ... tiny typo :)?RobertMontefore - Tuesday, August 25, 2020 - link
No one proofreads these days; the role of an editor has been relegated to a spell checker.bji - Tuesday, August 25, 2020 - link
Actually, it's been delegated to the readers.shabby - Tuesday, August 25, 2020 - link
Intel: oh yeah? Well we have better yield on 14nm than on 10nm... higher is better!RobertMontefore - Tuesday, August 25, 2020 - link
Intel is trying (er, WAS trying) to stay "in house" on their fabrication; didn't work out as they plannedpsychobriggsy - Tuesday, August 25, 2020 - link
Looks like 7nm didn't really get any better than the 0.09 figure for a long time, the first graph shows an improvement starting at Q6 and getting below 0.09 by Q8, but the second graph doesn't go beyond that (but shows good figures for N7+/N6).Also I thought TSMC were not going to use N7+ name any longer, yet there it is on that first graph.
Ian Cutress - Tuesday, August 25, 2020 - link
The problem started when customers were using N7+ to mean 'beyond 7nm but still on DUV', which was then called N7P (or perhaps just enhanced versions of N7).N7+ is very specifically the EUV version of N7.
smalM - Wednesday, August 26, 2020 - link
Au contraire, N7+ is very specifically not the EUV version of N7 (that's N6).You are Ian Cutress so you have to weigh your words ;-)
Grayson Carlyle - Wednesday, August 26, 2020 - link
Did you even attempt to look anything up before you stated something wrong?Spunjji - Thursday, August 27, 2020 - link
It baffles me how some people will talk nonsense with such confidenceWilco1 - Thursday, August 27, 2020 - link
To be fair I think he isn't saying that N7+ isn't EUV but that it is not compatible with N7, while N6 provides an almost seamless upgrade from N7 with the same benefits as N7+. So it's more correct to say that N6 is the EUV version of N7.smalM - Saturday, August 29, 2020 - link
It baffles me, that people don't read the exact words in a post about using words exactly.willgart - Tuesday, August 25, 2020 - link
at the same time at Intel:yes! we are on track ... we are 6months late for our 7nm process!
FreckledTrout - Tuesday, August 25, 2020 - link
Which lands Intel over 1 year after TSMC's 5nm which likely will be very similar to Intel's 7nm node.FreckledTrout - Tuesday, August 25, 2020 - link
(I should have noted TSMC's 5nm high performance used for AMD chips not he Initial low power 5nm for say Apple SoC's.)edzieba - Tuesday, August 25, 2020 - link
For comparison: TSMC announced 7nm in 2015, announced production start in April 2017, and the Ryzen 3xxx series arrived July 2019.RSAUser - Tuesday, August 25, 2020 - link
TSMC announced it in 2016, Risk production was 2017, high volume was started in April 2018, not sure where you're getting your dates from.JayNor - Tuesday, August 25, 2020 - link
Intel should be able to outbid AMD for TSMC wafer starts. In fact, Xe-HPG is already in the lab.psychobriggsy - Tuesday, August 25, 2020 - link
It's not all about money. AMD are a dedicated TSMC-only customer right now, whereas Intel are a high risk of only being a fly-by customer until they sort their own issues out. That factors heavily into allocation decisions.AnGe85 - Wednesday, August 26, 2020 - link
According to Bloomberg, Intel has ordered 180,000 wafers in N6 for 2021. To bring this in context, they also stated that AMD had a 7 nm volume of about 200,000 wafers in 2019 at TSMC.Spunjji - Wednesday, August 26, 2020 - link
I'm not sure that does necessarily bring things into context, though - we'd need to see AMD's 2021 numbers for 7nm and 5nm. They've done a fair bit of growing since 2019.Eneq - Saturday, August 29, 2020 - link
Also remember that Intel die size is a lot larger so the volume per wafer is less.hululu - Tuesday, August 25, 2020 - link
TSMC would not kill its golden goose.canukstorm - Tuesday, August 25, 2020 - link
TSMC's golden goose is Apple, not AMDTimSyd - Tuesday, August 25, 2020 - link
Nah. AMD has more wafer volume & spends more at TSMC that Apple - do the math on AMD's multiple hi-volume products per technology node (3-5 different APU's & counting, CPU chiplets, GPU's etc) vs Apples single/dual product per node (iPhone & iPad).Though of course Apple's aggressive SoC roadmaps help TSMC learn & pay for initial node ramps at each technology generation :)
melgross - Tuesday, August 25, 2020 - link
Where did you get that information from? It’s very doubtful. Apple buys well over 200 million chips a year from TSMC. Additionally, TSMC receives equipment from Apple.Guspaz - Tuesday, August 25, 2020 - link
Apple's probably bigger, but between their multi-die CPUs, their GPUs, their APUs, their console chips, AMD's still making a ton of dies with TSMC. They did collaborate on a semi-custom node, after all.melgross - Tuesday, August 25, 2020 - link
Whatever AMD does, Apple is still TSMC’ s largest customer, by some margin. It’s possible that Qualcomm is number two, or close to it.Valantar - Tuesday, August 25, 2020 - link
There's some nuance to be had here though. Apple is likely still TSMC's biggest customer, and the one most willing to pay whatever is needed for first access, but AMD shouldn't be that far behind in terms of volume, at least in the immediate future. How? Apple's SoCs are generally below 100mm2 (often quite a lot below). AMD' s CCDs are small, but they also make GPUs and console SoCs - and the latter are going to need a lot of wafers in the next couple of years. 20 million console SoCs - a likely sales number at least for the first year or two - would likely require as many wafers as something like a quarter of Apple's phone and tablet SoCs. Then there's consumer and datacenter GPUs, the vast majority of which will also be on the large side, and the ever growing sales of Ryzen. In other words, there's reason to believe that AMD is getting close to Apple in terms of sheer wafer volume.canukstorm - Tuesday, August 25, 2020 - link
Every SoC Apple designs (iPhone, iPad, iPad Pro, AirPods, HomePod, Watch) is manufactured by TSMC. That's approximately 250 million devices per year. And AMD doesn't contract out to only TSMC. They also contract out to GlobalFoundries.melgross - Tuesday, August 25, 2020 - link
TSMC makes more for Apple than just SoCs. They make Apple’s video controller chips, the t2 for Macs, various other sensor and controller chips. Over all, the number is easily close to, if not more than 300 million. It’s not just number of wafers that determine value. That’s an oversimplification.Wilco1 - Wednesday, August 26, 2020 - link
250 million 100mm^2 mobile SoCs would be close to 500000 7nm wafers per year.astroboy888 - Wednesday, August 26, 2020 - link
Not sure about volume for each company. But in terms of projected revenue for 2021, Apple is paying TSMC about $11 billion USD almost 1/3 of TSMC's total revenue. giving them 1st place by a long shot. 2nd place is AMD with projected revenue share of $4.6 billion USD. Then there are a bunch of $2 and 3billions customers, including Broadcom, Qualcomm, Nvidia ... etc.Spunjji - Wednesday, August 26, 2020 - link
@melgross here counting chips because they know Apple build smaller chips than AMD and therefore it makes their numbers look bigger. 😏melgross - Wednesday, August 26, 2020 - link
No. As was just pointed out, Apple is one third of TSMC’ s revenue. Nobody else comes close.smalM - Saturday, August 29, 2020 - link
Apple is TSMC's biggest customer at $8.0Bn 2019, $7.4Bn 2018, and $7.4Bn 2017.This is directly from their financial report for 2019.
RobertMontefore - Tuesday, August 25, 2020 - link
Unless AMD has this weird piece of paper called a "contract."vladx - Tuesday, August 25, 2020 - link
Fab contracts last only 2 years at most, after which AMD needs to renegotiate at which point Intel can just pay more.TimSyd - Tuesday, August 25, 2020 - link
Really unlikely to happen. TSMC & AMD work well together & TSMC isnt likely to shaft a major customer like that. Bad form, bad precedent for other customers & not the way they do business.Fastest way to encourage your customers to get serious abt spending money to help Samsung/UMC or GF get in the game is to shaft them publicly.
It *will* mean TSMC can push AMD higher on wafer pricing because they can use the Itel wafer allocation as a bargaining chip in the next round of pricing contract. Now that is much more TSMC's style.
Guspaz - Tuesday, August 25, 2020 - link
TSMC has already said that they see Intel as a short-term partner (a "rescuer", they said, where Intel would make some big orders and then drop them when their own fabs get back on track). Even if Intel offered more money for capacity, I really doubt they'd shortchange a long-term customer to satisfy a short-term one.TSMC is already production constrained. Their existing customers will use up as much fab capacity as they can build. They're not desperate for more business.
Spunjji - Wednesday, August 26, 2020 - link
Today in the Intel shill fantasies: every company works exactly the way they think a company should work in theory.Teckk - Wednesday, August 26, 2020 - link
Yes, Intel will spend billions on it's fabs and spend more money to secure wafers from TSMC. Ever thought of the impact on gross margins and profitability?I hope Intel gets back on track but come on, don't be such a shill.
TheReason8286 - Tuesday, August 25, 2020 - link
The things people say... Like you literally should've thought about that before you decided to type that. Why would they care about Intel their main competitor and their chip woes to allow them to leapfrog a consistent customer in AMD who will be with them for the long run. Like someone said its not about money in this situation. Besides AMD already secured wafers for 7nm and 5nm as from what I heard TSMC is making AMD 5nm more specifically tuned to their architecture.melgross - Tuesday, August 25, 2020 - link
Intel isn’t really a competitor. Samsung is a competitor. Intel produces their own chips, and just does a small fab business, while Samsung has a much bigger fab business. TSMC is entirely a fab business.vladx - Tuesday, August 25, 2020 - link
Exactly, Intel fabs were never TSMC competitors since Intel doesn't make ani 3rd party products at their fabs.Gigaplex - Tuesday, August 25, 2020 - link
If customers buy Intel chips fabbed by Intel vs buying AMD chips fabbed by TSMC, then yes, Intel is effectively a competitor.vladx - Tuesday, August 25, 2020 - link
Jeezus you AMD fanbois are nutsliquid_c - Wednesday, August 26, 2020 - link
Right? The wishfull thinking and their whole “logic” is annoying the living hell out of me. AMD this, TSMC that. It’s a bussiness and money, not AMD, has the last word.Spunjji - Wednesday, August 26, 2020 - link
@liquid_c - it's not *just* about money. Money is a huge factor, yes, but it's not the only one.It's abundantly clear that most Intel shills (yeah, nice "AMD fanboi" projection from you and vladx) would be shit at running a business.
melgross - Tuesday, August 25, 2020 - link
No, they’re not. They’re AMD’s competitor. TSMC is really just a jobber.melgross - Wednesday, August 26, 2020 - link
It’s amazing that people only seem to get out of statements what they want to. Intel said that CPUs would not be fabled, but some other chips likely would be. Nobody knows what the future will hold, but we can only go by what we’re told. It would be good to keep that in mind.Spunjji - Wednesday, August 26, 2020 - link
Not really. Not without pissing off their shareholders."Please tell us again why you spent billions on fabs and then paid hugely over the odds for 3rd party fab access?"
TheReason8286 - Tuesday, August 25, 2020 - link
I dont understand why people are still saying this and especially with the 10nm comparison to 7nm. The reason Intel cant get their nodes right is because they were over-ambitious. Thus they've had to lower their ambitions and tone it down. For example their revised 10nm no longer appears to be similar to TSMC 7nm because they had to tone it down for it to actually yield anything worthwhile. So im very skeptical of their 7nm being similar to TSMC 5nm. Whose to say their 7nm wont be scaled down due to certain difficulties/delays.. I'm just really skeptical about Intel and their claims these daysWaltC - Tuesday, August 25, 2020 - link
Yes, until Intel can put its products where its mouth is there is little point in listening to them at all, imo.Spunjji - Wednesday, August 26, 2020 - link
Those people are just copy-pasting the same logic that used to apply to Intel's 32nm and 22nm nodes, whether it be through ignorance or a calculated appeal to the ignorance of others.I'll be interested to see what density and performance looks like on TGL when it finally releases - I'm curious as to whether this "superfin" stuff they're bragging about came at the expense of density. That would rely on them being honest about transistor count, though...
RobertMontefore - Tuesday, August 25, 2020 - link
And now Intel is looking for someone else (TSMC?) to fabricate their chips.melgross - Tuesday, August 25, 2020 - link
Not CPUs.lmcd - Tuesday, August 25, 2020 - link
Gonna be honest I did not expect this. Intel is actually screwed :-/webdoctors - Tuesday, August 25, 2020 - link
Maybe this means the pricing on the N5 won't be insane. It'll be nice if its comparable to N7 but probably won't be for 5 yrs....nevertheless great work!vladx - Tuesday, August 25, 2020 - link
Wafer capacity is sold in Dutch auction style so the price is set by the clients.TimSyd - Tuesday, August 25, 2020 - link
The article & graphs show a timeline more like 5qtrs not 5yrsd. Where on earth did you get that idea?N5 *will* be expensive. Lots of EUV isn't cheap & throughput will be lower that they'd like. Both mean more $$ per wafer. I expect north of $15k/wafer easily though maybe volume/favoured customer discounts will pull that down below $12k/wafer mark.
TomWomack - Tuesday, August 25, 2020 - link
This is absolutely fascinating; defect-density curves with numbers on them are I think actually unprecedented (iirc Intel once provided a handout with numbers on but all the reporting of it was very quickly taken down). And that a mature process sticks at 0.1 defect per square centimetre (IE about 40% fully functioning 800mm^2 chips) for a year surprises me a lot, but possibly TSMC has finitely many fab engineers and would prefer to use them on getting the defect densities for newer processes down to a level they consider liveable with.Wilco1 - Wednesday, August 26, 2020 - link
According to https://caly-technologies.com/die-yield-calculator... it's actually 47% for 800mm^2! And many of the failed dies may be salvageable since large dies have a lot of redundancy.Spunjji - Thursday, August 27, 2020 - link
Yeah, 47% perfect dies for a chip of that size is absolute gangbusters. At that rate you're not even getting a clear majority of second-tier usable chips from each wafer, which is an interesting problem to have.Kamus - Tuesday, August 25, 2020 - link
Holy crap... these guys are on fire. Who ever made the choice at nVidia to go with Samsung instead of TSMC for Ampere should be fired, re-hired, and fired again.vladx - Tuesday, August 25, 2020 - link
Nvidia's architecture is so far ahead of the game that they just don't need the best fab process, they can use a lesser one and still kick AMD's and Intel's asses with ease.Morawka - Wednesday, August 26, 2020 - link
Nvidia's technical prowess is really a testament to Jensen Huang leadership skills. When most companies dominate their respective markets, they get complacent. Nvidia has managed to keep innovating while dominating the competition. I wish I could say the same for Intel. Perhaps there is a cultural aspect that contributes to the high levels of innovation over at Nvidia.Spunjji - Thursday, August 27, 2020 - link
Intel have to focus on both manufacturing and chip design, which probably doesn't help with how bloated their corporate structure has become. They also came of age with an effective monopoly and extended it through anti-competitive shenanigans and marketing, so there's been no real incentive for them to be any other way - they can always bully competitors out of their core markets whenever things get dicey for them.Nvidia, on the other hand, had to compete in a much more competitive market for a longer time, and have always focused much more keenly on graphics processor design. When they've tried to diversify it hasn't been so great (Tegra), and they've had some hilarious missteps directly overseen by Huang (wood screws!), but they appear to have actually learned from that and refocused back on core competencies. Even so, they've had their own share of anti-competitive and anti-consumer practices, and I do worry that this has been worsening noticeably in the past few years.
Spunjji - Wednesday, August 26, 2020 - link
That is one weird rationalisation for a stupid decision."We could have had an even better product, but we're so awesome that we decided not to" 🤡
You're probably right about their architecture. We'll see what Ampere brings, but unless it fails to move the bar much from Turing, it should keep them well in the lead at the high-end.
vladx - Wednesday, August 26, 2020 - link
"That is one weird rationalisation for a stupid decision."It's stupid in your view as a customer, meanwhile as a company would rather have higher profits than unnecessary gains at this time.
Spunjji - Thursday, August 27, 2020 - link
Honestly, I'd accept that response if I could see figures to back it up, but we don't have access to them. Speaking theoretically, I'd be very surprised if manufacturing such massive power-hungry chips on a less-dense process weren't costing them significantly in terms of yields. It's already clear they've blown the power budget too, but for some reason nobody cares about that? All in all, I'm getting big Fermi vibes from this generation.Whether or not AMD are able to repeat the feat ATi managed back then of introducing a more power-efficient and cost-effective design to counter Nvidia's juggernaut remains to be seen, though. I have hope but anticipate disappointment.
vladx - Friday, August 28, 2020 - link
Must really suck being an AMD fanboi always expecting to be disappointed.Kishoreshack - Tuesday, August 25, 2020 - link
Unfortunately no 5nm cpu or GPU launches for another year & a halfVitor - Wednesday, August 26, 2020 - link
Unless you are Apple.Anymoore - Wednesday, August 26, 2020 - link
It's doubtful fewer masks improved yield, it didn't do anything for N7+ or N6.Wilco1 - Wednesday, August 26, 2020 - link
Both N7+ and N6 are the lowest in the graphs. So all EUV processes, including N5, show a much faster yield improvement than N7.Anymoore - Wednesday, August 26, 2020 - link
They leveraged the N7 status, so if it's the same D0 they offer no improvement with lower mask count.Anymoore - Wednesday, August 26, 2020 - link
N5 starts off much better than N7, but is approaching the same level of defectivity. It suggests new issues came up.SaberKOG91 - Wednesday, August 26, 2020 - link
That's the wrong way to look at it. Defect density is defects per unit area. TSMC has shown a 45% reduction in area for N5 vs N7. That means the number of defects relative to the number of transistors is actually ~1/2 that compared to N7 at the same density. So it's more that ~0.1 is the floor for some other reason. It may simply be that TSMC actually have set 0.1 as their acceptable target and don't push hard on it after the fact, focusing more on power and area improvements to get meaningful gains in performance. You have to factor in the diminishing returns of pumping more money into R&D for only a small improvement in yields vs getting the next process out the door. Meanwhile, most customers are just happy to have double the transistor budget or double the yields per wafer, along-side the improvements in power and/or frequency, compared to the old node.Anymoore - Wednesday, August 26, 2020 - link
Defect density of N7 got to the same level of defect density in 3Q, N5 is at about the same level in same time. It's the same issue?SaberKOG91 - Wednesday, August 26, 2020 - link
No. These plots look like classic diminishing returns. Even their prediction line for N5 doesn't show significant improvement in the future. It's far more likely that they have a very rigorous internal schedule with predictable process maturity. Once it gets to a certain point internally they begin ramping production. It probably takes about 9-12 months on average after that point to dial in the process to these kinds of defect densities, at which point they stop trying to make significant improvements and focus on higher wafer throughput instead. TSMC has maintained that they saw much better yields on N5 out of the gate than N7. This just means they were able to start ramping earlier than they expected (ie. starting their 3-4Q long process tuning). I don't think they actually hit any significant issues that stopped them improving, just that it's "good enough" for mass production and any further improvements are expensive to make and pull resources away from the next process node. It's more important that they get the current process churning out wafers and get the next process moving along than it is to keep chasing defect density. They realized a long time ago that smaller feature size more than makes up for not chasing higher yields. Like I said, N5 at the same defect density at N7 has a much lower defect rate for the same transistor budget.Anymoore - Wednesday, August 26, 2020 - link
The two plots are obviously inconsistent, what is TSMC pulling. Linear vs log is not the explanation.SaberKOG91 - Wednesday, August 26, 2020 - link
They are consistent. The first plot starts at -2Q, the second starts at -3Q. They added N10 in the second plot which had much higher defect density. This changes the linear scale limits (mainly maximum) for the Y-axis.Anymoore - Thursday, August 27, 2020 - link
The upper graph shows N5 curving upward toward N7, approaching convergence, while the lower graph shows it maintaining ~80%.Spunjji - Thursday, August 27, 2020 - link
The second graph is literally just a zoomed-in segment of the first with a trend line and y-axis labelling added in.When you say "approaching convergence", that's just a guess - there's no way to know from the information they have provided whether the lines will converge or remain separate. They're predicting the latter, but then they would. So 🤷♂️
phdthesiswrite - Thursday, August 27, 2020 - link
Amazing one!thanks for sharingtuxRoller - Friday, August 28, 2020 - link
That wiki chip link mentions that tsmc focused on hpc for the first 5nm iteration rather than their usual LP. That may account for the difference in defect rates between 7 & 5.martixy - Sunday, August 30, 2020 - link
So... good things are coming in 2021, is what I'm reading here.