BTW - I hate to think how much power these things guzzle. Doing *anything* at 112G/224G on Si is an enormous challenge and throwing power at it is pretty much the only way to move signals around on chip. 1 simple nand/inverter gate delay can be 4-6ps in 10nm FinFET & here we're talking just 8ps bit times!
Much kudos to the Serdes engineers who made this happen.
seems things are getting towards extremely fast analog to digital conversion, means DDR5 to DDR6 will need higher power envelope on top bandwidth speeds?
The Tofino 2 presentation states it has 260 lanes of 56Gb PAM4. Looks like the serdes are on a separate die than the core in their presentation diagrams.
This article says Intel was previously using TSMC 58G serdes chiplets with their FPGAs. I see the 112G and 224G transceivers are being built with an Intel 10nm process now. I wonder if it is the same 10nm process as used on the cpu, or if this requires separate chiplets.
This article doesn't say what form factor the transceiver is. Is it SFP or QSFP? 200-gigabit QSFP56 transceivers are already available. But a 200-gigabit SFP transceiver would be big news.
It's just the logic -- there is no "connector" -- just pins on the die. You could put whatever connector you wanted, or perhaps it's just being used on a single board for chip to chip communication.
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JayNor - Friday, August 21, 2020 - link
Do PAM4 drivers go on the CPU chips when PCIE6 comes along?PixyMisa - Friday, August 21, 2020 - link
Yep. GDDR6X is also PAM4, so GPUs will be getting it as well. I wonder if DDR6 will also be PAM4.And with 224G transceivers on the way, the path is set for PCIe 8.0 and 112GB/s M.2 drives.
rpg1966 - Friday, August 21, 2020 - link
"This module is set to support both 224G in a PAM4 mode (4-bits)..."PAM4 is 2 bits (4 levels), not 4 bits?
TimSyd - Saturday, August 22, 2020 - link
Correct - PAM4 is 2 bits per symbol.BTW - I hate to think how much power these things guzzle.
Doing *anything* at 112G/224G on Si is an enormous challenge and throwing power at it is pretty much the only way to move signals around on chip. 1 simple nand/inverter gate delay can be 4-6ps in 10nm FinFET & here we're talking just 8ps bit times!
Much kudos to the Serdes engineers who made this happen.
back2future - Saturday, August 22, 2020 - link
seems things are getting towards extremely fast analog to digital conversion, means DDR5 to DDR6 will need higher power envelope on top bandwidth speeds?JayNor - Saturday, August 22, 2020 - link
The Tofino 2 presentation states it has 260 lanes of 56Gb PAM4. Looks like the serdes are on a separate die than the core in their presentation diagrams.https://www.anandtech.com/show/16003/hot-chips-202...
JayNor - Saturday, August 22, 2020 - link
This article says Intel was previously using TSMC 58G serdes chiplets with their FPGAs. I see the 112G and 224G transceivers are being built with an Intel 10nm process now. I wonder if it is the same 10nm process as used on the cpu, or if this requires separate chiplets.https://www.eejournal.com/article/intel-fpga-hits-...
https://www.intel.com/content/www/us/en/products/p...
richmaxw - Sunday, August 23, 2020 - link
This article doesn't say what form factor the transceiver is. Is it SFP or QSFP? 200-gigabit QSFP56 transceivers are already available. But a 200-gigabit SFP transceiver would be big news.extide - Tuesday, August 25, 2020 - link
It's just the logic -- there is no "connector" -- just pins on the die. You could put whatever connector you wanted, or perhaps it's just being used on a single board for chip to chip communication.richmaxw - Tuesday, August 25, 2020 - link
I see. I am a networking guy. Hence the confusion. So, would it be fair to say that this is a single lane?back2future - Wednesday, August 26, 2020 - link
for example Agilex I-Series IP shows for F-Tile"Transceiver channel count :- 4 channels at 116 Gbps (PAM4) / 58 Gbps (NRZ)- 16 channels at 32 Gbps (NRZ) /12 channels at 58 Gbps (PAM4) - RS & KP FEC"
(probably one channel is two differential signal lanes, full duplex?)