Nothing new in any of those talks, it appears. Nvidia is going over their A100 material again, Intel Xe, you can get similar if not nearly all relevant information from Anandtech already, and Xbox Arch covers nothing new.
Only thing interesting to me is how little IBM talked about their partners this time around. Looks like they really did burn some bridges at the end of POWER9.
I took some notes back in May. 2nd-gen Cerebras Wafer Scale Engine, Alibaba RISC-V and NPU, 3rd-gen Google TPUs, 4096-core RISC-V Manticore, Marvell ThunderX3, and ARM Cortex-M55 look interesting. Maybe some of those have already been detailed, I didn't check.
I think this is "doubled" in the sense that they're at the same level as Skylake-SP (which has 256-bit SIMD units on ports 0 and 1 and a 512-bit unit on port 5); getting substantially lower performance from an i9-11940X than from an i9-7940X would otherwise be embarrassing.
I’m new here. That being said, any speculation as to why Ice lake Xeon is using sunny cove and not willow cove? I thought from the tiger lake stuff that willow cove is a much better core design?? Just curious on if anyone has any thoughts...
Ice Lake SP is just like Ice Lake U/Y in that they're both Sunny Cove. The cadence for Intel architectures is that consumer gets it first, then it's adapted for Xeon a year later. We get Tiger Lake on Willow Cove for now and then Sapphire Rapids on Willow Cove a year from now.
but Sapphire Rapids has AMX instructions and Willow Cove does not, based on arch manual, as someone has already pointed out. Also, server cores had avx512 before moving to consumer cores.
Specific features can debut on server versions of a specific generation of a core instead of on the consumer version (or vice versa); that doesn't change that due to more extensive pre-release validation that the base server cores lag about a year behind the base consumer ones.
Considering that Willow Cove is basically more or less the same as Sunny Cove, I kinda doubt Sapphire Rapids would bother to "upgrade" to Willow Cove. It'd be more likely that it's a bit later, but with Golden Cove.
Willow Cove is basically Sunny Cove adapted to higher frequencies (SuperFin / 10nm+). Considering Ice Lake SP is already on 10nm+, I don't see any reason to use Willow Cove.
I don't recall seeing in any presentation a mention that Ice Lake Server has been updated to SuperFin. I think they would have been explicit, if this were so.
Willow Cove has 1.25MB L2 (and a non-inclusive L3), like this server Sunny Cove (and the server Skylake). This server Sunny Cove also has an extra FMA unit. So microarchitecturally Willow Cove is between client and server Sunny Cove, as far as I gather from the reporting. I guess there are improvements in Willow Cove at lower levels that were ot ready in time for server Sunny Cove (server parts have longer lead times); or maybe the server team is not as keen as others to have a separate name for the core.
One interesting development is that the OoO Window size is given as 384, while I had that number as 352 earlier (but don't remember from where).
They said it's more or less the same core microarchitecturally, so there's not really a big difference. At that point, it's probably more to do with just with what fabrication technology they are able to use in "volume".
Disappointed that Intel didn't release any SKU's yet, I hope we get some soon because this talk about improvements with no actual SKU's is very worrying.
I'm genuinely interested to see whether this ends up being one of their "shipped for revenue" releases that they stop talking about once a successor rolls around, or whether it actually gets out there in volume.
tomshardware picked up on this tidbit on IF type features added in Ice Lake Server's fabric:
"Intel redesigned the chip to support two new sideband fabrics, one controlling power management and the other used for general-purpose management traffic. These provide telemetry data and control to the various IP blocks, like execution cores, memory controllers, PCIe/UPI controllers, and the like. This is akin to AMD's Infinity Fabric, which also features a sideband telemetry/control mechanism for SoC structures."
there was also this tidbit in the toms article ... 3x fabric bandwidth seems signifcant:
"The die includes a separate peer-to-peer (P2P) fabric to improve bandwidth between cores, and the I/O subsystem was also virtualized, which Intel says offers up to three times the fabric bandwidth compared to Cascade Lake."
Silly question, but how wide are the FP registers into which the unit is renaming? Are they full 256-bit SIMD with other instructions using a power-gated bottom quarter, or are SIMD instructions renaming into multiple registers?
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SirDragonClaw - Monday, August 17, 2020 - link
I am pumped for the Intel GPU, Nvidia GPU and Xbox Arch talks!jeremyshaw - Monday, August 17, 2020 - link
Nothing new in any of those talks, it appears. Nvidia is going over their A100 material again, Intel Xe, you can get similar if not nearly all relevant information from Anandtech already, and Xbox Arch covers nothing new.Only thing interesting to me is how little IBM talked about their partners this time around. Looks like they really did burn some bridges at the end of POWER9.
nandnandnand - Monday, August 17, 2020 - link
I took some notes back in May. 2nd-gen Cerebras Wafer Scale Engine, Alibaba RISC-V and NPU, 3rd-gen Google TPUs, 4096-core RISC-V Manticore, Marvell ThunderX3, and ARM Cortex-M55 look interesting. Maybe some of those have already been detailed, I didn't check.Samsung could also be sharing some more info about the "X-Cube" 3D TSV SRAM. Ref: https://www.theregister.com/2020/08/13/samsung_tou...
JayNor - Monday, August 17, 2020 - link
would be interesting to know how many avx512 units they put in the server cores.also would be interesting to know if MKTME has any software behind it.
also would be interesting to know if they have some pcie4 peripherals for demo ... Habana NNP, Optane SSD, perhaps a Xe SG1.
JayNor - Tuesday, August 18, 2020 - link
Dr. Cutress answered this on his twitter acct. Intel effectively doubled the avx512 units per Sunny Cove core on the server chip.https://twitter.com/IanCutress/status/129546338432...
TomWomack - Tuesday, August 25, 2020 - link
I think this is "doubled" in the sense that they're at the same level as Skylake-SP (which has 256-bit SIMD units on ports 0 and 1 and a 512-bit unit on port 5); getting substantially lower performance from an i9-11940X than from an i9-7940X would otherwise be embarrassing.Dehjomz - Monday, August 17, 2020 - link
I’m new here.That being said, any speculation as to why Ice lake Xeon is using sunny cove and not willow cove? I thought from the tiger lake stuff that willow cove is a much better core design?? Just curious on if anyone has any thoughts...
Eulytaur - Monday, August 17, 2020 - link
Ice Lake SP is just like Ice Lake U/Y in that they're both Sunny Cove. The cadence for Intel architectures is that consumer gets it first, then it's adapted for Xeon a year later. We get Tiger Lake on Willow Cove for now and then Sapphire Rapids on Willow Cove a year from now.JayNor - Monday, August 17, 2020 - link
but Sapphire Rapids has AMX instructions and Willow Cove does not, based on arch manual, as someone has already pointed out. Also, server cores had avx512 before moving to consumer cores.DanNeely - Monday, August 17, 2020 - link
Specific features can debut on server versions of a specific generation of a core instead of on the consumer version (or vice versa); that doesn't change that due to more extensive pre-release validation that the base server cores lag about a year behind the base consumer ones.Spunjji - Tuesday, August 18, 2020 - link
It's pretty similar to how AMD do Desktop/Server first, then Mobile with tweaks - only in reverse!anonomouse - Monday, August 17, 2020 - link
Considering that Willow Cove is basically more or less the same as Sunny Cove, I kinda doubt Sapphire Rapids would bother to "upgrade" to Willow Cove. It'd be more likely that it's a bit later, but with Golden Cove.Rudde - Saturday, August 22, 2020 - link
Willow Cove is basically Sunny Cove adapted to higher frequencies (SuperFin / 10nm+). Considering Ice Lake SP is already on 10nm+, I don't see any reason to use Willow Cove.JayNor - Saturday, September 12, 2020 - link
I don't recall seeing in any presentation a mention that Ice Lake Server has been updated to SuperFin. I think they would have been explicit, if this were so.AntonErtl - Monday, August 17, 2020 - link
Willow Cove has 1.25MB L2 (and a non-inclusive L3), like this server Sunny Cove (and the server Skylake). This server Sunny Cove also has an extra FMA unit. So microarchitecturally Willow Cove is between client and server Sunny Cove, as far as I gather from the reporting. I guess there are improvements in Willow Cove at lower levels that were ot ready in time for server Sunny Cove (server parts have longer lead times); or maybe the server team is not as keen as others to have a separate name for the core.One interesting development is that the OoO Window size is given as 384, while I had that number as 352 earlier (but don't remember from where).
Ian Cutress - Monday, August 17, 2020 - link
Development cycle. The Xeon chip takes longer to optimize and bring to market than a mobile chip. That and the process delays ofcanonomouse - Monday, August 17, 2020 - link
They said it's more or less the same core microarchitecturally, so there's not really a big difference. At that point, it's probably more to do with just with what fabrication technology they are able to use in "volume".DigitalFreak - Monday, August 17, 2020 - link
Intel has some literal "hot chips" to talk about this year.Eulytaur - Monday, August 17, 2020 - link
Disappointed that Intel didn't release any SKU's yet, I hope we get some soon because this talk about improvements with no actual SKU's is very worrying.Ian Cutress - Monday, August 17, 2020 - link
Full launch later this year. General Availability, who knows.Spunjji - Tuesday, August 18, 2020 - link
I'm genuinely interested to see whether this ends up being one of their "shipped for revenue" releases that they stop talking about once a successor rolls around, or whether it actually gets out there in volume.JayNor - Tuesday, August 18, 2020 - link
tomshardware picked up on this tidbit on IF type features added in Ice Lake Server's fabric:"Intel redesigned the chip to support two new sideband fabrics, one controlling power management and the other used for general-purpose management traffic. These provide telemetry data and control to the various IP blocks, like execution cores, memory controllers, PCIe/UPI controllers, and the like. This is akin to AMD's Infinity Fabric, which also features a sideband telemetry/control mechanism for SoC structures."
https://www.tomshardware.com/news/intel-10nm-xeon-...
JayNor - Tuesday, August 18, 2020 - link
there was also this tidbit in the toms article ... 3x fabric bandwidth seems signifcant:"The die includes a separate peer-to-peer (P2P) fabric to improve bandwidth between cores, and the I/O subsystem was also virtualized, which Intel says offers up to three times the fabric bandwidth compared to Cascade Lake."
TomWomack - Tuesday, August 25, 2020 - link
Silly question, but how wide are the FP registers into which the unit is renaming? Are they full 256-bit SIMD with other instructions using a power-gated bottom quarter, or are SIMD instructions renaming into multiple registers?