Tigerlake is launching in September for notebooks. They can afford to make desktop parts that will compete with cheap AMD parts and sell for peanuts on their new 10nm process since it is not as high yielding as needed and the capacity from what I understand is not sufficient. So they focus on laptops and servers with 10nm and 14nm will have to make do for desktops this year.
TL is launching for ultrabooks which of course has overlap for notebooks. But in reality the H series mobile chip isn't going TL until 2021 and while it's thought to be Q1 frankly we could be at this same time a year from now still wondering where Tiger Lake H chips are. And by this time next year AMD will have cleaned Tiger Lake's clock (so to speak).
Tiger Lake will be released up to an -H series (i.e. middle TDPs of 35 - 45W), maxing at 8 cores. I have no idea if Intel mean -H for desktop or for heavy duty laptops though. It might, and should, be both. -S series and HEDT series will be covered by Rocket Lake, which will also almost certainly be released for -H, -U and -Y series as well because Intel's still problematic 10nm+ node cannot fully cover the market demand due to inadequate yields.
However while in the previous generation roughly 4 Comet Lake-U/Ys were fabbed for each Ice Lake-U/Y Intel plan to significantly increase the production of Tiger Lake-U/Y/Hs so that the split between them and the equivalent Rocket Lakes is somewhere between 2 Rocket Lakes for each Tiger Lake and (optimistically) an even split of both. Alder Lake, fabbed at 10nm++, is planned to be Intel's first top to bottom single release 10nm part, in other words Intel plans (or... hopes) to finally ditch their 14nm+++++ node next year..
Tiger Lake-U/Y/H is expected to have a faster iGPU than AMD's APU 4000 series due to AMD insisting on employing a 2017 iGPU μarch in their APUs - and even worse, they plan on using the same iGPUs in their Zen 3 sporting 5000 APU series next year. As insane as that sounds AMD plan to deliver the APU / laptop market back to Intel before they even took an appreciable slice from it, which is bizarre and disappointing. Tiger Lake might also have faster CPUs (if Intel can deliver high clocks), while the -H 8-core version might beat AMD's fastest -H APUs in all metrics : single core, multi core *and* GPU performance.
Intel's Xe (iGPUs) are expected to decimate Vega iGPUs and so surpass AMD in iGPU performance for the first time since... ever? Well, if Intel's brand new 2020 GPU tech couldn't even surpass AMD's 2017 iGPU tech Intel would be in big trouble..
Renoir is meant to be paired with a discrete mobile GPU, although even that is a problem since it can't support the most powerful ones. On the other hand, the most expensive and powerful laptops sell less units.
It looks like they will put the good graphics (RDNA/RDNA2) in Van Gogh, and make modest iGPU improvements in Cezanne, but probably fix the PCIe bandwidth issue at that time.
"even that is a problem since it can't support the most powerful ones" Yes it can. It has 8 PCIe 3.0 lanes dedicated to graphics which is more than sufficient to support the highest-end laptop GPUs.
This bizarre rationalization needs to die. It *can support the best graphics chips*, it's just that *no OEM will pair them up*. Nobody knows why for sure, but it's not down to the PCIe lanes.
Just more Spunjii nonsense, some games already started to show difference between PCIe 3.0 x8 and x16, this will become more and more apparent in the future.
I'm interested to see 10nm SuperFin Tiger Lake H with 8 Willow Cove Cores, Xe-LP, LPDDR5, PCIe 4.0 (dGPU+NVME SSD) and Thunderbolt 4|USB4 USB-C. I don't see Tiger Lake bringing any form factor design changes. More the laptop performance playing catch up with the desktop. Alder Lake on the other hand could help usher longer battery life and even lighter devices. I say this considering the performance of Lakefield which only has 1 Sunny Cove and the 4 Tre Mont Cores do most of the lifting. Alder Lake will be on an advanced SuperFin (whatever that means) will have upto 8 Golden Cove cores (improved Willow Cove) and upto 8 Grace Mont cores. Not only will it be improving on the 8 Big cores found in Tiger Lake H but will be adding 8 small Cores which as we have seen with Lakefield can be very efficient. The improved scheduler will help future laptops ran cooler, quieter and longer since most of the day to day tasks will ran on the small cores. In fact I don't think we will see many laptop designs with 8 Big Cores, it will be more common to see gaming ultra portables with 6 big cores + 8 Little Cores + GT2 (iGPU) + dGPU. The bigLittle design prefers the Little cores and calls upon the big cores to boost performance or short bursts of performance.The little cores will handle typical tasks like Web browsing, Word processing well. I really hope Intel can get Alder Lake out and swe see healthy competition between x86 x64 vs ARM, and between Intel, AMD, Nvidia, Qualcomm and Apple chip designs.
"...which as we have seen with Lakefield can be very efficient..." Why are so many people talking like this is a product that has already released and been tested? Can anyone buy it yet? The only info I've seen was that early leak from Notebookcheck.
I'm glad that people finally care about iGPU performance now that Intel are about to get better than AMD at it. 😏
I do find their choices in that area inexplicable. Renoir having Vega makes some sense; Cezanne on the other hand...
If Tiger launches on time, in volume and hits its performance metrics then it should be a force to be reckoned with. I very much doubt we'll ever see it on desktop, though, and my understanding is that the 8-core parts will be arriving significantly later than the 4-core ones.
Yep the "confirmed" or "scheduled for date xxx" statements from Intel have been useless for several years. Sooner or later the newsworthy world will just start ignoring their official statements entirely as baseless rumor. They simply cannot deliver anything when they think they will 6 months ahead of time let alone a year or more. They are even less accurate than weather forecasters.
I'm still confused by why Intel chose to beta-test several new technologies simultaneously (mixed cores, chiplets, stacking) on what's effectively a low-end chip. I gather they're relying on marketing to keep the prices high, but we won't know until we actually see it, and now they're talking about it like it's a thing that already happened...
Can we have an edit button already please? I re-wrote the comment a few times. At first I wanted to write "IINM Alder lake is going to have a much higher IPC".
It's not too bad. Most games and applications won't use more than 8 cores, so there's a nice cluster of 8 Golden Cove performance cores in Alder Lake. The Gracemont cores are supposed to be near Ivy Bridge's IPC, although I guess they won't hit the same clocks.
It would have been nice to see more small cores. Like 8+16 or 8+32 instead of 8+8. Oh well.
"The smaller footprint on Lakefield enabled smaller, thinner, and lighter mobile designs by shrinking the size of the chip package with 3D stacking, but Intel doesn't have the same footprint concerns on the desktop. As such, Intel wouldn't necessarily have to use the cost-increasing Foveros 3D packaging technique to bring the processors to market. Instead, the chipmaker could use a single monolithic die with two kinds of cores, a chiplet-based architecture composed of separate compute chiplets for each type of core, or stick with 3D Foveros packaging. Only time will tell."
What would be the use case of having 32 or 16 Ivy Bridge type of Cores with 8 Golden Cove cores? On a desktop I would rather have 16 or 32 Golden Cove core instead of a Hybrid. On a Laptop you are constrained by the battery and thermals of the chasis. Seems like 4 Little core are 1 big core, that is what I think Intel was hoping with Lakefield. Once you go past 8 little cores it better to exchange a set of 4 little cores with 1 big core, for example instead of 6+12 it is better to exchange little cores and end up with 8+4. The big core are high performance Cores so once you need more performance they will always be better, if you need efficiency then what you need is not more Cores but how to do more with less. This is the philosophy being the bigLITTLE architecture. Once the performamce demand increases by due to multi tasking or high performance tasks it is no longer efficient to use the LITTLE core. Even with ARM SOCs we have performance increased by adding a better big core, for example Snapdragon 865 plus adds a prime core on top of the big Cores to get an edge on performance over the snapdragon 865. I could be very wrong in my analysis. So we will see how things pan out. I believe without the problems with 7nm and 10nm Intel would have used a chip let design for their desktop and a hybrid design for mobile. Intel struggled to get their chip let designs working even on the Xe-HP GPUs. AMD is really nailing it with their Infinity fabric and architecture.
It's a cheap way to get lots of multi-threaded performance. Less die area, less cost.
The big core cluster can get loaded up with the tasks that need high single-threaded performance. Anything that is embarrassingly parallel could use dozens if not hundreds of small cores.
A hypothetical 8+32 configuration would have 8 big cores which could handle the most demanding threads, and would match the next-gen console core count by itself, meaning most gaming is covered for several years. Then the small cores can handle any background tasks and any software capable of using as many cores as you throw at it.
My understanding is that 1 big core is around the same die area as 4 small cores, but the small cores have more than 25% the performance of a big core. Maybe 50%? So 8+32 would have more total multi-threaded performance than 16 big cores, at around the same die area. 8+32 can credibly compete with AMD's 16-core, 8+8... not so much.
Consider the performance of 8+32 vs 12+16 vs 16+0 (big+LITTLE), how will they rank? If we look at what is happening with smartphone SOCs which have more thermal constraints than laptops and desktops, for example the Snapdragon 600 series vs Snapdragon 700 series vs the 800 series vs Snapdragon 8cx performance is scaled up generation on generation by increasing and improving the big cores. The little cores have remained the same (Cortex A55) for several generations.
I remember seeing some disappointment over there being no Cortex-A55 successor, but has anybody provided an official explanation why that is?
Intel has continued to improve its Atom line. Goldmont Plus (e.g. J4115) is being dumped into x86 single board computers right now, Tremont is in Lakefield, and Gracemont will be in Alder Lake.
A53 was a very long-lived design; I don't expect A55 to be very different. The RoI to develop further increases in efficiency in the power and thermal budgets the "efficiency" cores live in probably isn't judged to be worth frequent updates
I do wonder about this one. In theory it could do very well - but memory contention already starts to bite pretty hard on the 3950X, so wouldn't that problem be multiplied by having 40 cores (regardless of size) on the same chip?
Well, the 40-core ain't happening, it's just hypothetical, but maybe DDR5 could improve the situation? Alder Lake may even be using DDR5, if not, probably everything launched afterwards will.
AMD's Mark Papermaster has said the company will increase core counts on mainstream Ryzen CPUs, so we will probably see the 3950X-tier flagship go to 24 or 32 cores by Zen 4/5.
It's not clear to me what Intel's HEDT plans are post-Cascade Lake (presumably they'll have something based on Ice Lake SP or its successor eventually).
If it Intel puts more than 8 'big' cores on a non-HEDT chip, it's for marketing, not because there's any real use case for it (which is why the 10-core non-HEDT i9s exist). Which is why AMD did it, too.
While I like many cores CPUs like 3950x, I think having a 8 big cpu cores that are much faster than AMD cores and 8 smaller cores work together would be better in the end for both pure performance and efficiency. While having the same type of cores is nice, in the end there are benefits to having different cores for different purposes like mobile chips have already for quite a long time.
And what exactly is that ? Mobile trash always does it because to save that pathetic battery technology. This doesn't belong in desktops where the Clockspeed matters a lot and that adjusts your efficiency with Turbo Boost you already have it.. Why do you need a small trash core doing the work with reduced performance ? You are not going to save anything except making the work finished in longer period.
This bullshit Intel approach is because to keep their SMT performance, they cannot scale with Ring bus it's game over for Intel after this SKL, which was max at 10C, that's why RKL is not 10C at-least from rumors, it's not an SKL uArch part so it's having this uneven SMT distribution too, 8C/12T & Mesh is trash as it gobbles up power like anything too inefficient is the reason.
This is a joke from Intel which is getting nasty with each of their moves after 10nm debacle.
Statements like "best performance-per-watt" and mentions of notebooks in the same breath as desktops make me wonder if this is really what half of us are expecting. This might be a high performance CPU for constrained form factors rather than some kind of balls-out desktop successor to the 11700K.
And why wouldn't it be? That's what normal, non-enthusiast people are willing to pay more for, and there are a lot more of those people.
If it was a pure performance part, why would it be using low power cores?
"but in the Q2 2020 financial disclosures, it was said to be positioned for mobile and desktops."
Yes, I believe the Alder Lake use for mobile was mentioned somewhere in the architecture day presentations also. It makes a lot of sense to me, assuming the small core performance is a cut above hyper-thread performance.
I'd also be surprised if there isn't a Lakefield successor.
Alder Lake is the Lakefield successor. While the desktop variant Alder Lake S goes upto 8 Big Cores, the mobile variant Alder Lake P maxs out at 6 Big Cores. According to leaks there are 3 skus with 2 Big Cores and a combination of 8, 4 or 0 little cores (2+8, 2+4, 2+0) and one with 4 Big Cores paired with 8 little cores. Lakefield only had one big core which was not competitive so the lowest next gen hybrid CPUs from Intel will have 2 Big Cores. The desktop variants has one sku with 4 Big Cores paired and another with 2 Big Cores in the lower end, both with no little cores. The desktop Alder Lake P comes with GT1 rated iGPU while the mobile variants have GT2, this are probably the upgrade to Gen 12 Xe-LP. All these are according to leaks and with Intel one can't be confident predicting what will actually happen.
Lakefield is not very competitive just because it is made on a shitty process...Unfortunately it is not made on this new SuperFin 10nm process, so the power/performance characteristics are similar to the 1065G7 which is pretty bad TBH. I would expect that Lakefield made on 7nm TSMC would be much much more competitive, allowing the Sunny Cove core to boost to ~3Ghz and the little ones to a similar frequency.
I quite like the sound of those 2+8 chips - they could make for a really nice low-power experience. If they really have gone all the way down to 2+0 at the low end then that will be a shame - I can't imagine they'd have any yield reasons to do that as the small cores are so tiny, so it would entirely be about segmentation.
I wonder if they'll start using Gracemont in big socket Xeons. Cloud providers would *love* to stuff 4 cores in the place of one big one in many scenarios, even if each core is a little (30%?) slower.
One of the issues with Hybrid right now is that you have to limit the support instructions to the lowest common denominator. So in a server, if you start adding Atom cores, you'll lose all the AVX512 stuff, which is just a waste of silicon. You can't just add different cores for free, it's always a bit of give and take.
You could, technically, allow a hypervisor to build VMs of only one core type. But then you're just putting two different class of VMs onto the same CPU. Beyond that you can run into troubles regarding shared cache for one type of core, or how the LLC works, etc.
Thats not a problem if every core is a Gracemont core.
But in future hybrid scenarios, I wonder if Intel will homogenize the ISA across the big and little cores. So a little core could, for example, accept an AVX 512 instruction, but it would break it down into a series of smaller ops that it can handle.
Makes sense, and I presume it won't be there in the Xeon lineup. I think many are not able to understand how does translate to performance. I hope AMD doesn't do this hybrid drama and rekts them straight with their Zen designs.
This is why AVX512 is a dead end in the first place. Intel's Xe GPUs should be accelerating those instructions with the on-die Xe GPU accelerating if there's no dGPU. Intel doesn't hardly sell CPUs without GPUs anyway. Then that takes advantage of Intel's pricing for GPU virtualization as well, and eventually the possibility for GPU slices to be assigned out of a shared pool between the iGPU and dGPU.
SIMD instructions and offloading to a GPU are very different. One can be done right inside a stream of branchy CPU instructions, or nice high level CPU code. With the other you have to start up a whole kernel and manually shuffle the data to and from the GPU, or let some library do it for you.
Executing GPU instructions directly on data in system RAM, with a minimal latency hit, would be pretty awesome.
Oh No. I can already see the marketing from Intel and laptop vendors going like "mega-ultra-high-performance TWELVE CORE CPU ..." (4 big+8 little) When in reality it is slower than an AMD (or Intel) 8 core CPU. And I can see people falling for that kind of marketing as well ...
The problem's pretty similar (counting total cores without specifying resources per core), if indeed you believe that's is a problem in the first place. You do, so you'd have to do better on rationalising why one's okay and one's not.
That lawsuit was an absolute nonsense. In a technical sense it was without merit, and from a performance point of view you had to be a really specific kind of ignoramus to think you needed 8 cores but somehow failed to notice the reviews pointing out that the per-core performance was not up to Intel's standards.
Honestly most highly-threaded workloads on a laptop don't need every thread to be crazy powerful anyway. A modern Atom core is actually up to snuff for most workloads as long as it isn't allocated the bottleneck thread. If you think about boost clocks and such, an Atom core would allow for nearby cores to have higher boost clocks. For the die space, each one would disproportionately benefit threaded workloads.
Unlike Bulldozer, assigning to nearby cores shouldn't be a problem, so scheduling around these mixed cores should be relatively easy.
Your comments here are amusing. Scheduling for Lakefield is already known to be *more difficult* than scheduling for Bulldozer was, because the cores don't have equal execution resources.
If it were so easy they'd let you use the big and little cores at the same time; but they don't.
4 big+8 little might be able to match the multi-threaded performance of a normal 8-core. Same with 8 big+8 little vs. a normal 12-core.
Cancel out the big cores and it comes down to: can 8 "Gracemont" Atom cores perform as well as 4 big cores? Maybe, if all of them are being used, the clock speeds aren't very low, and other conditions are right.
Exactly. All they do is talk now. Rubbish Xe and this joke of a tech in Desktops, it's only made for that SMT loss against Ryzen, we already know how Zen absolutely kills SKL and all its successors in HT/SMT performance. With unified 8C CCDs in Zen 3 it's going to break havoc on Intel for sure.
It's like they want to get that SMT performance, I beleive that's the only reason to add those in Desktop, adding a small x86 Atom cores will net some performance in the loss of more cores and SMT. Zen 3 is going big with 8C CCDs and unified Cache. It's going to be crazy fast with the 3300X as proof of that.
Intel really cannot do more than 10C on SKL, so RKL is 8C tops from the rumors and this is also looking same, past 8C no more ring bus, and perhaps on this +2 cores will result in high power consumption, if they axe ring bus they will lose gaming performance and SMT. Only way is to cram more x86 cores for that SMT/Physical cores loss.
I'm quite keen on adding small cores to desktops. Most desktops spend most of their time doing nothing, so it makes sense to have a few small cores to take care of checking email, tidying up the SSD, running backups and other background operations. Good for the environment and reducing power bills. It will mean much of the low power code can be removed from the big cores, freeing up space on them for the high-power circuits.
These Atom cores should be about 25% the die area, but what, 50-70% the performance?
Beyond an initial 8 or so big cores, adding many small Atom cores makes sense. They could put 40 cores (8+32) in a die area similar to a normal 16-core.
Given how low Intel Core cores can clock down and how much silicon they can simply shut down, with power draws dropping <1W, power-savings from including Mont cores will be effectively invisible.
Alder Lake will not compete against Zen 3 based parts but against Zen 4 ones. The Zen 3 generation will bring no core increases but the Zen 4 one will, along with the introduction of AVX-512, DDR5 and probably PCIe 5.0 and CXL as well. Alder Lake should support DDR5 -and probably PCIe 5.0- as well, since Tiger Lake-U will already support LPDDR5.
AMD should retain the chiplet scheme with their Zen 4 launch, I don't think that is going away. Zen 3 will unify the L3 cache, thus the two 4-core CCXs will be merged, so each 8-core chiplet will be monolithic, not split in 2 CCXs. Perhaps with Zen 4 they are going to re-introduce CCXs but with a 6-core CCX as a base (for 12-core chiplets)? I don't know, wouldn't that be a step backwards? Perhaps it would be best to make monolithic 12-core chiplets and use 6 cores as a base for their Zen 4 APUs, up to maybe 12 cores. It's also unclear whether AMD will introduce a big-little scheme or not. From an energy efficiency point of view it would make sense. From a performance one it might not. It is still unclear if the Golden Cove cores of Alder Lake will need to be handicapped in order to match the features of the Gracemont cores or not.
I don't think they need to respond to big/small right now. If Intel was pitting a 40-core (8+32) against AMD's 16-core, that would be crazy and could deserve a response. But the leaks say it tops out at 8+8, which might be comparable to AMD's 12-core.
I think they might stick to the 8-core chiplet, and just use three of them for up to 24 cores, maybe four for 32 cores in a later generation. Games will mostly be using 8 cores due to XSX/PS5. Let games hog a full 8-core chiplet for the best performance, and use the defective chiplets with cores disabled for background tasks.
The most interesting feature could be L4 cache stacked on the I/O die. If they pull it off, certain games and workloads will benefit big time.
Does Gracemont support the same SIMD instruction set that Golden Cove does? I'm wondering if they plan to use the low power cores for heavily multithreaded and efficiency on the desktop parts. I'm otherwise unsure where the plan is other than Intel not caring about the desktop. I guess you could turn off the fan on the heatsink if it's only using 2W or something.
Intel is also using Gracemont in the 24 core Grand Ridge, which appears to be a successor to the P5900 Snow Ridge family chips... also no hyper-threading.
Thanks Ian! Question: any statement by Intel whether the big cores in Alder Lake will have AVX2 and AVX512? Asking as one of the issues in Lakefield that kept AVX out of Lakefield's big core were (reportedly) concerns about problems with handovers from big to little cores, as Monts don't have AVX. Will the new scheduler address that?
Seems really weird to be including Mont in a desktop chip. The power draw for light tasks just isn't that different between a Cove core and a Mont core.
...unless the idea is to remove non-experience-critical tasks from the big cores, allowing them to concentrate on tasks which will make the system feel faster to the user.
Anybody else notice how that slide shows Lakefield as a 2019 part... but it's still not available now?
I'm getting leery of this habit Intel have of simply pretending they did things they didn't really do (Lakefield) / pretending they never tried to do things they weren't able to do (Cannon Lake).
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Alistair - Friday, August 14, 2020 - link
I don't even have that big of a problem with Intel chips. But they aren't even available, it is all empty marketing.Give me a 4 core Tiger Lake chip, unlocked, with Xe graphics, on my desktop. Thanks. Not for sale? Then it is meaningless.
Flunk - Friday, August 14, 2020 - link
Good luck, they're still planning get ANOTHER Sky Lake refresh for desktop (Rocket Lake).eddman - Friday, August 14, 2020 - link
All the rumors are claiming it's based on a Willow Cove derived arch but at 14nm, Cypress Cove.SarahKerrigan - Friday, August 14, 2020 - link
Rocket isn't a Skylake refresh.yeeeeman - Saturday, August 15, 2020 - link
Rocket Lake is a backport of a 10nm CPU to 14nm. It has a new core (willow cove) and it will bring some IPC improvements.Santoval - Saturday, August 15, 2020 - link
Rocket Lake is not a Skylake refresh, it is a 14nm node "refresh".FXi - Sunday, August 16, 2020 - link
Rocket isn't even here yet. And how many times has some future roadmap changed? Yeah...Meteor2 - Monday, August 17, 2020 - link
RL is still nothing but rumour. Using the word "will" in the same sentence as RL is ridiculous. Try "might", "maybe".yeeeeman - Saturday, August 15, 2020 - link
Tigerlake is launching in September for notebooks.They can afford to make desktop parts that will compete with cheap AMD parts and sell for peanuts on their new 10nm process since it is not as high yielding as needed and the capacity from what I understand is not sufficient. So they focus on laptops and servers with 10nm and 14nm will have to make do for desktops this year.
Santoval - Saturday, August 15, 2020 - link
"They can afford.."You rather meant "they *cannot* afford", right?
FXi - Sunday, August 16, 2020 - link
TL is launching for ultrabooks which of course has overlap for notebooks. But in reality the H series mobile chip isn't going TL until 2021 and while it's thought to be Q1 frankly we could be at this same time a year from now still wondering where Tiger Lake H chips are. And by this time next year AMD will have cleaned Tiger Lake's clock (so to speak).Santoval - Saturday, August 15, 2020 - link
Tiger Lake will be released up to an -H series (i.e. middle TDPs of 35 - 45W), maxing at 8 cores. I have no idea if Intel mean -H for desktop or for heavy duty laptops though. It might, and should, be both. -S series and HEDT series will be covered by Rocket Lake, which will also almost certainly be released for -H, -U and -Y series as well because Intel's still problematic 10nm+ node cannot fully cover the market demand due to inadequate yields.However while in the previous generation roughly 4 Comet Lake-U/Ys were fabbed for each Ice Lake-U/Y Intel plan to significantly increase the production of Tiger Lake-U/Y/Hs so that the split between them and the equivalent Rocket Lakes is somewhere between 2 Rocket Lakes for each Tiger Lake and (optimistically) an even split of both. Alder Lake, fabbed at 10nm++, is planned to be Intel's first top to bottom single release 10nm part, in other words Intel plans (or... hopes) to finally ditch their 14nm+++++ node next year..
Tiger Lake-U/Y/H is expected to have a faster iGPU than AMD's APU 4000 series due to AMD insisting on employing a 2017 iGPU μarch in their APUs - and even worse, they plan on using the same iGPUs in their Zen 3 sporting 5000 APU series next year. As insane as that sounds AMD plan to deliver the APU / laptop market back to Intel before they even took an appreciable slice from it, which is bizarre and disappointing. Tiger Lake might also have faster CPUs (if Intel can deliver high clocks), while the -H 8-core version might beat AMD's fastest -H APUs in all metrics : single core, multi core *and* GPU performance.
Intel's Xe (iGPUs) are expected to decimate Vega iGPUs and so surpass AMD in iGPU performance for the first time since... ever? Well, if Intel's brand new 2020 GPU tech couldn't even surpass AMD's 2017 iGPU tech Intel would be in big trouble..
nandnandnand - Saturday, August 15, 2020 - link
Renoir is meant to be paired with a discrete mobile GPU, although even that is a problem since it can't support the most powerful ones. On the other hand, the most expensive and powerful laptops sell less units.It looks like they will put the good graphics (RDNA/RDNA2) in Van Gogh, and make modest iGPU improvements in Cezanne, but probably fix the PCIe bandwidth issue at that time.
Spunjji - Monday, August 17, 2020 - link
"even that is a problem since it can't support the most powerful ones"Yes it can. It has 8 PCIe 3.0 lanes dedicated to graphics which is more than sufficient to support the highest-end laptop GPUs.
This bizarre rationalization needs to die. It *can support the best graphics chips*, it's just that *no OEM will pair them up*. Nobody knows why for sure, but it's not down to the PCIe lanes.
nandnandnand - Monday, August 17, 2020 - link
You sure?https://www.igorslab.de/en/manufacturers-when-gami...
vladx - Thursday, August 20, 2020 - link
Just more Spunjii nonsense, some games already started to show difference between PCIe 3.0 x8 and x16, this will become more and more apparent in the future.KimGitz - Sunday, August 16, 2020 - link
I'm interested to see 10nm SuperFin Tiger Lake H with 8 Willow Cove Cores, Xe-LP, LPDDR5, PCIe 4.0 (dGPU+NVME SSD) and Thunderbolt 4|USB4 USB-C.I don't see Tiger Lake bringing any form factor design changes. More the laptop performance playing catch up with the desktop.
Alder Lake on the other hand could help usher longer battery life and even lighter devices. I say this considering the performance of Lakefield which only has 1 Sunny Cove and the 4 Tre Mont Cores do most of the lifting. Alder Lake will be on an advanced SuperFin (whatever that means) will have upto 8 Golden Cove cores (improved Willow Cove) and upto 8 Grace Mont cores. Not only will it be improving on the 8 Big cores found in Tiger Lake H but will be adding 8 small Cores which as we have seen with Lakefield can be very efficient. The improved scheduler will help future laptops ran cooler, quieter and longer since most of the day to day tasks will ran on the small cores. In fact I don't think we will see many laptop designs with 8 Big Cores, it will be more common to see gaming ultra portables with 6 big cores + 8 Little Cores + GT2 (iGPU) + dGPU. The bigLittle design prefers the Little cores and calls upon the big cores to boost performance or short bursts of performance.The little cores will handle typical tasks like Web browsing, Word processing well.
I really hope Intel can get Alder Lake out and swe see healthy competition between x86 x64 vs ARM, and between Intel, AMD, Nvidia, Qualcomm and Apple chip designs.
Spunjji - Monday, August 17, 2020 - link
"...which as we have seen with Lakefield can be very efficient..."Why are so many people talking like this is a product that has already released and been tested? Can anyone buy it yet? The only info I've seen was that early leak from Notebookcheck.
Valantar - Tuesday, August 18, 2020 - link
... because it has? There's at least a Samsung laptop available with Lakefield, and it's been reviewed extensively.vladx - Thursday, August 20, 2020 - link
Lmao @Spunjii busted again.Meteor2 - Monday, August 17, 2020 - link
Nonsense.Spunjji - Monday, August 17, 2020 - link
I'm glad that people finally care about iGPU performance now that Intel are about to get better than AMD at it. 😏I do find their choices in that area inexplicable. Renoir having Vega makes some sense; Cezanne on the other hand...
If Tiger launches on time, in volume and hits its performance metrics then it should be a force to be reckoned with. I very much doubt we'll ever see it on desktop, though, and my understanding is that the 8-core parts will be arriving significantly later than the 4-core ones.
FXi - Sunday, August 16, 2020 - link
Yep the "confirmed" or "scheduled for date xxx" statements from Intel have been useless for several years. Sooner or later the newsworthy world will just start ignoring their official statements entirely as baseless rumor. They simply cannot deliver anything when they think they will 6 months ahead of time let alone a year or more. They are even less accurate than weather forecasters.Meteor2 - Monday, August 17, 2020 - link
Well given the way people hang onto every last word of rumour, I don't see them ignoring official Intel statements any time soon.YB1064 - Monday, August 17, 2020 - link
AT should stop publishing these vaporware slide decks.liujustin604 - Thursday, September 24, 2020 - link
Oh wait, Tiger Lake is Laptop.tipoo - Friday, August 14, 2020 - link
Hmm, does the hardware scheduler alleviate concerns over Windows not handling this well?nandnandnand - Friday, August 14, 2020 - link
Lakefield was the "beta test" of x86 big/small, hopefully. Or it just wasn't capable of much because of power constraints.Santoval - Saturday, August 15, 2020 - link
It's both actually.Spunjji - Monday, August 17, 2020 - link
Precisely that.I'm still confused by why Intel chose to beta-test several new technologies simultaneously (mixed cores, chiplets, stacking) on what's effectively a low-end chip. I gather they're relying on marketing to keep the prices high, but we won't know until we actually see it, and now they're talking about it like it's a thing that already happened...
Meteor2 - Tuesday, August 18, 2020 - link
It's not low-end for its power and thermal envelopeseddman - Friday, August 14, 2020 - link
No 12 and 16 big core configs? Is this the only replacement for rocket lake, or they will have a non-hybrid line too?IINM Alder lake will be based on the golden cove arch, which allegedly is going to have a much higher IPC compared to skylake arch.
If so, does this mean intel is planning to counter AMD's core count with their big-little setup? I don't know what to think of this.
eddman - Friday, August 14, 2020 - link
Can we have an edit button already please? I re-wrote the comment a few times. At first I wanted to write "IINM Alder lake is going to have a much higher IPC".nandnandnand - Friday, August 14, 2020 - link
It's not too bad. Most games and applications won't use more than 8 cores, so there's a nice cluster of 8 Golden Cove performance cores in Alder Lake. The Gracemont cores are supposed to be near Ivy Bridge's IPC, although I guess they won't hit the same clocks.It would have been nice to see more small cores. Like 8+16 or 8+32 instead of 8+8. Oh well.
yeeeeman - Saturday, August 15, 2020 - link
I am guessing 10nm process is the limit here...nandnandnand - Saturday, August 15, 2020 - link
Is it going to be monolithic or chiplets though?https://www.tomshardware.com/news/intel-alder-lake...
"The smaller footprint on Lakefield enabled smaller, thinner, and lighter mobile designs by shrinking the size of the chip package with 3D stacking, but Intel doesn't have the same footprint concerns on the desktop. As such, Intel wouldn't necessarily have to use the cost-increasing Foveros 3D packaging technique to bring the processors to market. Instead, the chipmaker could use a single monolithic die with two kinds of cores, a chiplet-based architecture composed of separate compute chiplets for each type of core, or stick with 3D Foveros packaging. Only time will tell."
KimGitz - Sunday, August 16, 2020 - link
What would be the use case of having 32 or 16 Ivy Bridge type of Cores with 8 Golden Cove cores? On a desktop I would rather have 16 or 32 Golden Cove core instead of a Hybrid. On a Laptop you are constrained by the battery and thermals of the chasis. Seems like 4 Little core are 1 big core, that is what I think Intel was hoping with Lakefield. Once you go past 8 little cores it better to exchange a set of 4 little cores with 1 big core, for example instead of 6+12 it is better to exchange little cores and end up with 8+4. The big core are high performance Cores so once you need more performance they will always be better, if you need efficiency then what you need is not more Cores but how to do more with less. This is the philosophy being the bigLITTLE architecture. Once the performamce demand increases by due to multi tasking or high performance tasks it is no longer efficient to use the LITTLE core. Even with ARM SOCs we have performance increased by adding a better big core, for example Snapdragon 865 plus adds a prime core on top of the big Cores to get an edge on performance over the snapdragon 865. I could be very wrong in my analysis. So we will see how things pan out. I believe without the problems with 7nm and 10nm Intel would have used a chip let design for their desktop and a hybrid design for mobile. Intel struggled to get their chip let designs working even on the Xe-HP GPUs. AMD is really nailing it with their Infinity fabric and architecture.nandnandnand - Sunday, August 16, 2020 - link
It's a cheap way to get lots of multi-threaded performance. Less die area, less cost.The big core cluster can get loaded up with the tasks that need high single-threaded performance. Anything that is embarrassingly parallel could use dozens if not hundreds of small cores.
A hypothetical 8+32 configuration would have 8 big cores which could handle the most demanding threads, and would match the next-gen console core count by itself, meaning most gaming is covered for several years. Then the small cores can handle any background tasks and any software capable of using as many cores as you throw at it.
My understanding is that 1 big core is around the same die area as 4 small cores, but the small cores have more than 25% the performance of a big core. Maybe 50%? So 8+32 would have more total multi-threaded performance than 16 big cores, at around the same die area. 8+32 can credibly compete with AMD's 16-core, 8+8... not so much.
KimGitz - Monday, August 17, 2020 - link
Consider the performance of 8+32 vs 12+16 vs 16+0 (big+LITTLE), how will they rank?If we look at what is happening with smartphone SOCs which have more thermal constraints than laptops and desktops, for example the Snapdragon 600 series vs Snapdragon 700 series vs the 800 series vs Snapdragon 8cx performance is scaled up generation on generation by increasing and improving the big cores. The little cores have remained the same (Cortex A55) for several generations.
nandnandnand - Monday, August 17, 2020 - link
I remember seeing some disappointment over there being no Cortex-A55 successor, but has anybody provided an official explanation why that is?Intel has continued to improve its Atom line. Goldmont Plus (e.g. J4115) is being dumped into x86 single board computers right now, Tremont is in Lakefield, and Gracemont will be in Alder Lake.
Meteor2 - Tuesday, August 18, 2020 - link
A53 was a very long-lived design; I don't expect A55 to be very different. The RoI to develop further increases in efficiency in the power and thermal budgets the "efficiency" cores live in probably isn't judged to be worth frequent updatesSpunjji - Monday, August 17, 2020 - link
"8+32 can credibly compete with AMD's 16-core"I do wonder about this one. In theory it could do very well - but memory contention already starts to bite pretty hard on the 3950X, so wouldn't that problem be multiplied by having 40 cores (regardless of size) on the same chip?
nandnandnand - Monday, August 17, 2020 - link
Well, the 40-core ain't happening, it's just hypothetical, but maybe DDR5 could improve the situation? Alder Lake may even be using DDR5, if not, probably everything launched afterwards will.AMD's Mark Papermaster has said the company will increase core counts on mainstream Ryzen CPUs, so we will probably see the 3950X-tier flagship go to 24 or 32 cores by Zen 4/5.
drothgery - Friday, August 14, 2020 - link
It's not clear to me what Intel's HEDT plans are post-Cascade Lake (presumably they'll have something based on Ice Lake SP or its successor eventually).If it Intel puts more than 8 'big' cores on a non-HEDT chip, it's for marketing, not because there's any real use case for it (which is why the 10-core non-HEDT i9s exist). Which is why AMD did it, too.
yeeeeman - Saturday, August 15, 2020 - link
While I like many cores CPUs like 3950x, I think having a 8 big cpu cores that are much faster than AMD cores and 8 smaller cores work together would be better in the end for both pure performance and efficiency. While having the same type of cores is nice, in the end there are benefits to having different cores for different purposes like mobile chips have already for quite a long time.Quantumz0d - Saturday, August 15, 2020 - link
And what exactly is that ? Mobile trash always does it because to save that pathetic battery technology. This doesn't belong in desktops where the Clockspeed matters a lot and that adjusts your efficiency with Turbo Boost you already have it.. Why do you need a small trash core doing the work with reduced performance ? You are not going to save anything except making the work finished in longer period.This bullshit Intel approach is because to keep their SMT performance, they cannot scale with Ring bus it's game over for Intel after this SKL, which was max at 10C, that's why RKL is not 10C at-least from rumors, it's not an SKL uArch part so it's having this uneven SMT distribution too, 8C/12T & Mesh is trash as it gobbles up power like anything too inefficient is the reason.
This is a joke from Intel which is getting nasty with each of their moves after 10nm debacle.
nandnandnand - Sunday, August 16, 2020 - link
If 4 Atom cores is about the same die area as 1 big core, but with better multi-threaded performance, that is a benefit.mattbg - Monday, August 17, 2020 - link
Statements like "best performance-per-watt" and mentions of notebooks in the same breath as desktops make me wonder if this is really what half of us are expecting. This might be a high performance CPU for constrained form factors rather than some kind of balls-out desktop successor to the 11700K.And why wouldn't it be? That's what normal, non-enthusiast people are willing to pay more for, and there are a lot more of those people.
If it was a pure performance part, why would it be using low power cores?
JayNor - Friday, August 14, 2020 - link
"but in the Q2 2020 financial disclosures, it was said to be positioned for mobile and desktops."Yes, I believe the Alder Lake use for mobile was mentioned somewhere in the architecture day presentations also. It makes a lot of sense to me, assuming the small core performance is a cut above hyper-thread performance.
I'd also be surprised if there isn't a Lakefield successor.
KimGitz - Friday, August 14, 2020 - link
Alder Lake is the Lakefield successor. While the desktop variant Alder Lake S goes upto 8 Big Cores, the mobile variant Alder Lake P maxs out at 6 Big Cores. According to leaks there are 3 skus with 2 Big Cores and a combination of 8, 4 or 0 little cores (2+8, 2+4, 2+0) and one with 4 Big Cores paired with 8 little cores. Lakefield only had one big core which was not competitive so the lowest next gen hybrid CPUs from Intel will have 2 Big Cores. The desktop variants has one sku with 4 Big Cores paired and another with 2 Big Cores in the lower end, both with no little cores. The desktop Alder Lake P comes with GT1 rated iGPU while the mobile variants have GT2, this are probably the upgrade to Gen 12 Xe-LP. All these are according to leaks and with Intel one can't be confident predicting what will actually happen.yeeeeman - Saturday, August 15, 2020 - link
Lakefield is not very competitive just because it is made on a shitty process...Unfortunately it is not made on this new SuperFin 10nm process, so the power/performance characteristics are similar to the 1065G7 which is pretty bad TBH.I would expect that Lakefield made on 7nm TSMC would be much much more competitive, allowing the Sunny Cove core to boost to ~3Ghz and the little ones to a similar frequency.
JayNor - Sunday, August 16, 2020 - link
22FFL base chiplet process of Lakefield offers ultra low leakage, which was required by MSFT's application.Spunjji - Monday, August 17, 2020 - link
I quite like the sound of those 2+8 chips - they could make for a really nice low-power experience. If they really have gone all the way down to 2+0 at the low end then that will be a shame - I can't imagine they'd have any yield reasons to do that as the small cores are so tiny, so it would entirely be about segmentation.brucethemoose - Friday, August 14, 2020 - link
I wonder if they'll start using Gracemont in big socket Xeons. Cloud providers would *love* to stuff 4 cores in the place of one big one in many scenarios, even if each core is a little (30%?) slower.Ian Cutress - Friday, August 14, 2020 - link
One of the issues with Hybrid right now is that you have to limit the support instructions to the lowest common denominator. So in a server, if you start adding Atom cores, you'll lose all the AVX512 stuff, which is just a waste of silicon. You can't just add different cores for free, it's always a bit of give and take.You could, technically, allow a hypervisor to build VMs of only one core type. But then you're just putting two different class of VMs onto the same CPU. Beyond that you can run into troubles regarding shared cache for one type of core, or how the LLC works, etc.
brucethemoose - Friday, August 14, 2020 - link
Thats not a problem if every core is a Gracemont core.But in future hybrid scenarios, I wonder if Intel will homogenize the ISA across the big and little cores. So a little core could, for example, accept an AVX 512 instruction, but it would break it down into a series of smaller ops that it can handle.
nandnandnand - Friday, August 14, 2020 - link
They should just use chiplets totaling 64 to 256+ Atom cores. Like Xeon Phi but with no AVX-512.Quantumz0d - Friday, August 14, 2020 - link
Makes sense, and I presume it won't be there in the Xeon lineup. I think many are not able to understand how does translate to performance. I hope AMD doesn't do this hybrid drama and rekts them straight with their Zen designs.lmcd - Friday, August 14, 2020 - link
This is why AVX512 is a dead end in the first place. Intel's Xe GPUs should be accelerating those instructions with the on-die Xe GPU accelerating if there's no dGPU. Intel doesn't hardly sell CPUs without GPUs anyway. Then that takes advantage of Intel's pricing for GPU virtualization as well, and eventually the possibility for GPU slices to be assigned out of a shared pool between the iGPU and dGPU.brucethemoose - Friday, August 14, 2020 - link
SIMD instructions and offloading to a GPU are very different. One can be done right inside a stream of branchy CPU instructions, or nice high level CPU code. With the other you have to start up a whole kernel and manually shuffle the data to and from the GPU, or let some library do it for you.Executing GPU instructions directly on data in system RAM, with a minimal latency hit, would be pretty awesome.
Spunjji - Monday, August 17, 2020 - link
Wasn't that the goal of HSA? I haven't heard about that in so long I've gone and presumed the concept is dead now.Meteor2 - Tuesday, August 18, 2020 - link
Too hard to programMark242 - Friday, August 14, 2020 - link
Oh No.I can already see the marketing from Intel and laptop vendors going like
"mega-ultra-high-performance TWELVE CORE CPU ..." (4 big+8 little)
When in reality it is slower than an AMD (or Intel) 8 core CPU. And I can see people falling for that kind of marketing as well ...
lmcd - Friday, August 14, 2020 - link
That was called Bulldozer.brucethemoose - Friday, August 14, 2020 - link
There was a lawsuit over that marketing scheme IIRC.lmcd - Friday, August 14, 2020 - link
Yes. I'm just saying I don't see the problem with this considering that each core has a separate fetch/decode/int/fp etc pipeline.Spunjji - Monday, August 17, 2020 - link
The problem's pretty similar (counting total cores without specifying resources per core), if indeed you believe that's is a problem in the first place. You do, so you'd have to do better on rationalising why one's okay and one's not.Spunjji - Monday, August 17, 2020 - link
That lawsuit was an absolute nonsense. In a technical sense it was without merit, and from a performance point of view you had to be a really specific kind of ignoramus to think you needed 8 cores but somehow failed to notice the reviews pointing out that the per-core performance was not up to Intel's standards.lmcd - Friday, August 14, 2020 - link
Honestly most highly-threaded workloads on a laptop don't need every thread to be crazy powerful anyway. A modern Atom core is actually up to snuff for most workloads as long as it isn't allocated the bottleneck thread. If you think about boost clocks and such, an Atom core would allow for nearby cores to have higher boost clocks. For the die space, each one would disproportionately benefit threaded workloads.Unlike Bulldozer, assigning to nearby cores shouldn't be a problem, so scheduling around these mixed cores should be relatively easy.
Spunjji - Monday, August 17, 2020 - link
Your comments here are amusing. Scheduling for Lakefield is already known to be *more difficult* than scheduling for Bulldozer was, because the cores don't have equal execution resources.If it were so easy they'd let you use the big and little cores at the same time; but they don't.
nandnandnand - Saturday, August 15, 2020 - link
4 big+8 little might be able to match the multi-threaded performance of a normal 8-core. Same with 8 big+8 little vs. a normal 12-core.Cancel out the big cores and it comes down to: can 8 "Gracemont" Atom cores perform as well as 4 big cores? Maybe, if all of them are being used, the clock speeds aren't very low, and other conditions are right.
ksec - Saturday, August 15, 2020 - link
Lots of talk. It reads to me Intel is trying to do damage control, hyping up some of their future product roadmap.We need to see how well Tigerlake execute and its volume. No use if you cant actually deliver anything.
Quantumz0d - Saturday, August 15, 2020 - link
Exactly. All they do is talk now. Rubbish Xe and this joke of a tech in Desktops, it's only made for that SMT loss against Ryzen, we already know how Zen absolutely kills SKL and all its successors in HT/SMT performance. With unified 8C CCDs in Zen 3 it's going to break havoc on Intel for sure.It's like they want to get that SMT performance, I beleive that's the only reason to add those in Desktop, adding a small x86 Atom cores will net some performance in the loss of more cores and SMT. Zen 3 is going big with 8C CCDs and unified Cache. It's going to be crazy fast with the 3300X as proof of that.
Intel really cannot do more than 10C on SKL, so RKL is 8C tops from the rumors and this is also looking same, past 8C no more ring bus, and perhaps on this +2 cores will result in high power consumption, if they axe ring bus they will lose gaming performance and SMT. Only way is to cram more x86 cores for that SMT/Physical cores loss.
Tomatotech - Saturday, August 15, 2020 - link
I'm quite keen on adding small cores to desktops. Most desktops spend most of their time doing nothing, so it makes sense to have a few small cores to take care of checking email, tidying up the SSD, running backups and other background operations. Good for the environment and reducing power bills. It will mean much of the low power code can be removed from the big cores, freeing up space on them for the high-power circuits.nandnandnand - Saturday, August 15, 2020 - link
These Atom cores should be about 25% the die area, but what, 50-70% the performance?Beyond an initial 8 or so big cores, adding many small Atom cores makes sense. They could put 40 cores (8+32) in a die area similar to a normal 16-core.
JayNor - Sunday, August 16, 2020 - link
\Perhaps the real competition is Gracemont + Golden Cove vs AMD SMT pair.Meteor2 - Monday, August 17, 2020 - link
Given how low Intel Core cores can clock down and how much silicon they can simply shut down, with power draws dropping <1W, power-savings from including Mont cores will be effectively invisible.JayNor - Sunday, August 16, 2020 - link
Perhaps they will do the dual ring bus on Rocket Lake, as on Tiger Lake.Santoval - Saturday, August 15, 2020 - link
Alder Lake will not compete against Zen 3 based parts but against Zen 4 ones. The Zen 3 generation will bring no core increases but the Zen 4 one will, along with the introduction of AVX-512, DDR5 and probably PCIe 5.0 and CXL as well. Alder Lake should support DDR5 -and probably PCIe 5.0- as well, since Tiger Lake-U will already support LPDDR5.AMD should retain the chiplet scheme with their Zen 4 launch, I don't think that is going away. Zen 3 will unify the L3 cache, thus the two 4-core CCXs will be merged, so each 8-core chiplet will be monolithic, not split in 2 CCXs. Perhaps with Zen 4 they are going to re-introduce CCXs but with a 6-core CCX as a base (for 12-core chiplets)? I don't know, wouldn't that be a step backwards? Perhaps it would be best to make monolithic 12-core chiplets and use 6 cores as a base for their Zen 4 APUs, up to maybe 12 cores.
It's also unclear whether AMD will introduce a big-little scheme or not. From an energy efficiency point of view it would make sense. From a performance one it might not. It is still unclear if the Golden Cove cores of Alder Lake will need to be handicapped in order to match the features of the Gracemont cores or not.
nandnandnand - Saturday, August 15, 2020 - link
I don't think they need to respond to big/small right now. If Intel was pitting a 40-core (8+32) against AMD's 16-core, that would be crazy and could deserve a response. But the leaks say it tops out at 8+8, which might be comparable to AMD's 12-core.I think they might stick to the 8-core chiplet, and just use three of them for up to 24 cores, maybe four for 32 cores in a later generation. Games will mostly be using 8 cores due to XSX/PS5. Let games hog a full 8-core chiplet for the best performance, and use the defective chiplets with cores disabled for background tasks.
The most interesting feature could be L4 cache stacked on the I/O die. If they pull it off, certain games and workloads will benefit big time.
evilpaul666 - Sunday, August 16, 2020 - link
Does Gracemont support the same SIMD instruction set that Golden Cove does? I'm wondering if they plan to use the low power cores for heavily multithreaded and efficiency on the desktop parts. I'm otherwise unsure where the plan is other than Intel not caring about the desktop. I guess you could turn off the fan on the heatsink if it's only using 2W or something.JayNor - Sunday, August 16, 2020 - link
The Alder Lake info says no hyper-threading.Intel is also using Gracemont in the 24 core Grand Ridge, which appears to be a successor to the P5900 Snow Ridge family chips... also no hyper-threading.
Meteor2 - Monday, August 17, 2020 - link
SIMD is not SMT.JayNor - Sunday, August 16, 2020 - link
The Tiger Lake presentation stated that Intel doubled the bandwidth by using a dual ring bus. See slide 65.eastcoast_pete - Sunday, August 16, 2020 - link
Thanks Ian! Question: any statement by Intel whether the big cores in Alder Lake will have AVX2 and AVX512? Asking as one of the issues in Lakefield that kept AVX out of Lakefield's big core were (reportedly) concerns about problems with handovers from big to little cores, as Monts don't have AVX. Will the new scheduler address that?Meteor2 - Monday, August 17, 2020 - link
Seems really weird to be including Mont in a desktop chip. The power draw for light tasks just isn't that different between a Cove core and a Mont core.Meteor2 - Monday, August 17, 2020 - link
...unless the idea is to remove non-experience-critical tasks from the big cores, allowing them to concentrate on tasks which will make the system feel faster to the user.Spunjji - Monday, August 17, 2020 - link
Anybody else notice how that slide shows Lakefield as a 2019 part... but it's still not available now?I'm getting leery of this habit Intel have of simply pretending they did things they didn't really do (Lakefield) / pretending they never tried to do things they weren't able to do (Cannon Lake).
nandnandnand - Monday, August 17, 2020 - link
It seems to exist in the hands of real, non-Intel people: https://www.notebookcheck.net/Exclusive-First-benc...If availability is nearly zero, I wouldn't notice because I already checked out when I saw the "premium" prices.