Based on core count, no mention of multithreading, and cache sizes... I think these may actually be based on the original ThunderX2 developed by Cavium, not the Vulcan design acquired from Marvell.
-66+41K L1 lines up better with the original 64+40K announced for Cavium-TX2 than with Vulcan's 32+32 caches.
-Vulcan goes to 32 cores @ 2.2GHz in 180W, so 36 cores @ 120ish with a bunch of extra peripherals seems unlikely unless there's a shrink. Cavium's inhouse TX2 design targeted higher core counts than Vulcan.
-No multithreading is mentioned. This is something of a headline feature for Vulcan.
I think we're looking at a microarchitecture that was widely assumed dead.
And, one more addition: Cavium TX2 (the original design, not Vulcan) was supposed to have a 32MB LLC for 54 cores. That scales exactly with what we're seeing for Octeon TX2 - 21MB LLC at 36 cores.
At this point I think I'd put money on this being based on Cavium's original TX2 microarchitecture rather than Vulcan.
> However, Intel didn’t talk in detail about availability of its new Snow Ridge platform, while Marvell’s chips are in mass production and being deployed right now.
Marvell website says:
> Marvell’s OCTEON TX2 CN9130, CN92xx and CN96xx are available now with reference designs and development kits. Marvell’s CN98xx will begin sampling in the second quarter of 2020.
Clearly they won't be in mass production until 2021 timeframe at the earliest.
Any chance you’ll be able to reach out to Marvell and get some more details on the uarch of the cores used? As SarahKerrigan points out it seems likely to be a derivative of the original ThunderX uarch, which would be interesting as with all of the other Arm vendors seemingly going to all stock core IP Marvell is in the unusual position of fielding two different lines of custom uarch.
And I’m guessing based on their reticence to talk about node that it’s not 7nm, probably Samsung 14nm or TSMC 16/12.
I have a question related to the architectural deployment of the Octeon Fusion. 1. Small cell w/ Split 6 Does Octeon Fusion support nFAPI termination, so it could interwork with any (ie non Octeon TX2) vendor's L2+ solution ?
2. Macro cell w/ Split 7.2 In this case, the Octeon Fusion + Octeon TX2 (any alternate) would be co-located, in the O-RAN defined O-DU. In this case, what is the connection btwtween the Fusion and TX2 - Is it Ethernet, OR, does it support any alternate, like a FAPI-over-PCIE (as in competing products) ?
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SarahKerrigan - Monday, March 2, 2020 - link
Based on core count, no mention of multithreading, and cache sizes... I think these may actually be based on the original ThunderX2 developed by Cavium, not the Vulcan design acquired from Marvell.-66+41K L1 lines up better with the original 64+40K announced for Cavium-TX2 than with Vulcan's 32+32 caches.
-Vulcan goes to 32 cores @ 2.2GHz in 180W, so 36 cores @ 120ish with a bunch of extra peripherals seems unlikely unless there's a shrink. Cavium's inhouse TX2 design targeted higher core counts than Vulcan.
-No multithreading is mentioned. This is something of a headline feature for Vulcan.
I think we're looking at a microarchitecture that was widely assumed dead.
SarahKerrigan - Monday, March 2, 2020 - link
And, one more addition: Cavium TX2 (the original design, not Vulcan) was supposed to have a 32MB LLC for 54 cores. That scales exactly with what we're seeing for Octeon TX2 - 21MB LLC at 36 cores.At this point I think I'd put money on this being based on Cavium's original TX2 microarchitecture rather than Vulcan.
SarahKerrigan - Monday, March 2, 2020 - link
Ugh, "Acquired from Broadcom", not Marvell. An edit button would be nice!dotjaz - Thursday, March 5, 2020 - link
That's pretty much confirmed. Based on GCC commit not the specs. Cavium is explicitly mentioned./* Cavium ('C') cores. */
AARCH64_CORE("octeontx2", octeontx2, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_CRYPTO | AARCH64_FL_PROFILE, cortexa57, 0x43, 0x0b0, -1)
https://github.com/gcc-mirror/gcc/blob/master/gcc/...
RallJ - Monday, March 2, 2020 - link
> However, Intel didn’t talk in detail about availability of its new Snow Ridge platform, while Marvell’s chips are in mass production and being deployed right now.Marvell website says:
> Marvell’s OCTEON TX2 CN9130, CN92xx and CN96xx are available now with reference designs and development kits. Marvell’s CN98xx will begin sampling in the second quarter of 2020.
Clearly they won't be in mass production until 2021 timeframe at the earliest.
anonomouse - Tuesday, March 3, 2020 - link
Any chance you’ll be able to reach out to Marvell and get some more details on the uarch of the cores used? As SarahKerrigan points out it seems likely to be a derivative of the original ThunderX uarch, which would be interesting as with all of the other Arm vendors seemingly going to all stock core IP Marvell is in the unusual position of fielding two different lines of custom uarch.And I’m guessing based on their reticence to talk about node that it’s not 7nm, probably Samsung 14nm or TSMC 16/12.
songhai.wang - Thursday, March 12, 2020 - link
How about the capability of the CNF95xx of supporting MassiveMIMO as the major product in 5G?saju_n - Wednesday, June 15, 2022 - link
I have a question related to the architectural deployment of the Octeon Fusion.1. Small cell w/ Split 6
Does Octeon Fusion support nFAPI termination, so it could interwork with any (ie non Octeon TX2) vendor's L2+ solution ?
2. Macro cell w/ Split 7.2
In this case, the Octeon Fusion + Octeon TX2 (any alternate) would be co-located, in the O-RAN defined O-DU. In this case, what is the connection btwtween the Fusion and TX2 - Is it Ethernet, OR, does it support any alternate, like a FAPI-over-PCIE (as in competing products) ?