It is tech news for techies. Honestly if you don't know what SOI is google it :) Kind of like asking to explain what a hard drive is, most people on this site know what SOI was used for prior.
No, but if he is going to, do it the FIRST time. As Jordan pointed out, it is good journalism, hell good writing, to define an acronym the first time you use it, at least if you are going to bother doing it at all.
It is bad writing to define it later one. Because defining it means that the author is assuming some of the audience will not understand what it means. So by doing it well in to an article after it has been used multiple times means that the author is assuming the audience does not know what SOI means, but btw, doesn't mind letting them wonder for most of the article.
It either should have been defined the first time it was used, or not at all.
You are correct in principle but I don't see a problem here. The first paragraph is telling the reader what is happening; Global Foundries is making stuff (chips), the specifics are not needed to convey that. The second paragraph gets into what exactly they are making and SOI is defined at this point which makes sense to me.
And only once - a publication for my other hobby has a tendency to, in the course of say a 2 page article, covering 3-4 columns, depending on how many pictures there are (magazine format), define common hobby acronyms 4-5 times. As in every other or every third usage. No, I did not forget from two paragraphs above, thank you.
Except it really isn't "acronym". In Tech you dont define everything up front like FDD, TDD, CDMA, SQL, DRAM, CPU, M-MIMO, FPGA, GAA, FinFET, etc.. Depending on your reader's understanding, unless they are very rare and not used much, you are expected to know them. And in the case Anandtech is one of the rare site that focuses on the relatively higher end. SOI isn't something brand new, and if you dont know, you are expected to look it up. No one will spell out Dynamic Random Access Memory in PC publishing or Massive Multi-input Multi-output Antenna in 4G / 5G publishing.
Yeah, you don't use an abbreviation multiple times before you give the definition. Anyone who has written a 12th grade essay knows that much. I also highly doubt that the majority of readers on this site know that particular abbreviation off the top of their heads.
I wonder if this is a move to secure wafers long term if the fabs who are currently on leading edge processes do end up adopting SOI down the road. Much of the technology currently in use on bulk leading edge can be made to work with SOI though it is currently not adopted due to an imbalance in cost/benefit. As transistors continue to get smaller that could change.
450 mm wafer plans have been canned, due to their dubious ROI (either the same or less than that of 300 mm wafers) and the much higher difficulty and cost of handling and processing them. While with 450 mm wafers you can have many more dies per wafer, if the wafers cost 4 times more than 300 mm wafers (as is currently estimated) the high numbers of dies per wafer does not really matter.
Nobody cares about 450mm. There is a very small improvement in utilization of wafer until you get to very large dies, and those aren't really viable due to yield. Additionally, you get troubles in every single step on the way - people making ingots have it harder, all tools need to be redesigned and made bigger, and people carrying those hot lots around also complain because of twice the weight.
Silicon ingots for 450 mm wafers are not just twice as heavy as those for 300 mm wafers. They are *three* times heavier, at roughly one ton each. Furthermore, a FOUP (a special plastic enclosure for holding and carrying wafers) with 25 450 mm wafers weighs a whopping 45 kg, while a FOUP with 25 300 mm wafers weighs only 7.5 kg. Everything (from ingots to step-and-scan systems) needs to be bigger, much heavier, quite costlier and more time consuming to make the transition to 450 mm wafers a reality.
Are these 300 mm wafers to be used for GloFo's 12 nm FDSOI (fully-depleted silicon on insulator)? The article (apparently from a press release) omits any details on that. At least one of the Fabs named was retrofitted for 12 nm FDSOI, which is supposed to be especially power efficient. Some information on that power efficiency would be great, too!
ROFL...I can only "assume" most folks who come to sites such as this absolutely KNOW what SOI is, as others have pointed out, maybe some "not known" other abbreviations it would be helpful, but SOI has been a VERY long time in use decade+ is anything but a "new term"..I myself do not get the "undies in a bunch" commentary, upset because? did not spell out what SOI stands for till a few sentences in..
does it REALLY MATTER?
Ii would be picking more upon when product announcement is given (to them, from the makers) but does not include things such as battery size, if there is 3.5mm jack, type of power connectors, P/E cycles and such things.
but not IMHO for such a silly thing as SOI..that is my .02c
FWIW, I'm a computer geek, not a silicon geek. I would've guessed silicon-on-interposer, not insulator, because interposers are talked about frequently with relation to silicon chip substrates.
People are getting up in arms about things that would normally be covered by an sub-editor, and they are not seeing them here - such inconsistencies suggests that normal phase is missing.
SOI was all the rage for most of the 2000's. People following tech news during those years should know it well but after that it's pretty understandable that people don't necessarily know what it is.
What an ignorant comment! You can't assume people in their 20s would know SOI. The last time SOI making waves it was mid-2000s, by the time 45nm SOI hit the market, we already know there won't be a 28nm and smaller node for the decade to come. People get into technology world in the 2010s won't necessarily know what it is from bits and pieces reported about 28FDS 22FDX 14HP 12FDX.
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waterdog - Thursday, February 27, 2020 - link
Waiting until the second paragraph and seventh use to define the abbreviation SOI is not good.AshlayW - Friday, February 28, 2020 - link
Stop complaining.Papaspud - Friday, February 28, 2020 - link
I kept wondering too.FreckledTrout - Friday, February 28, 2020 - link
It is tech news for techies. Honestly if you don't know what SOI is google it :) Kind of like asking to explain what a hard drive is, most people on this site know what SOI was used for prior.NICOXIS - Friday, February 28, 2020 - link
Since SOI has been around since 90nm, I'd think most people on this website would be familiar with the term...jordanclock - Friday, February 28, 2020 - link
It's just good journalism to define abbreviations the first time you use them, if you're going to define them at all.NICOXIS - Friday, February 28, 2020 - link
so he should also define SoC, MCU and IoT as well?azazel1024 - Friday, February 28, 2020 - link
No, but if he is going to, do it the FIRST time. As Jordan pointed out, it is good journalism, hell good writing, to define an acronym the first time you use it, at least if you are going to bother doing it at all.It is bad writing to define it later one. Because defining it means that the author is assuming some of the audience will not understand what it means. So by doing it well in to an article after it has been used multiple times means that the author is assuming the audience does not know what SOI means, but btw, doesn't mind letting them wonder for most of the article.
It either should have been defined the first time it was used, or not at all.
Operandi - Friday, February 28, 2020 - link
You are correct in principle but I don't see a problem here. The first paragraph is telling the reader what is happening; Global Foundries is making stuff (chips), the specifics are not needed to convey that. The second paragraph gets into what exactly they are making and SOI is defined at this point which makes sense to me.rrinker - Friday, February 28, 2020 - link
And only once - a publication for my other hobby has a tendency to, in the course of say a 2 page article, covering 3-4 columns, depending on how many pictures there are (magazine format), define common hobby acronyms 4-5 times. As in every other or every third usage. No, I did not forget from two paragraphs above, thank you.ksec - Friday, February 28, 2020 - link
Except it really isn't "acronym". In Tech you dont define everything up front like FDD, TDD, CDMA, SQL, DRAM, CPU, M-MIMO, FPGA, GAA, FinFET, etc.. Depending on your reader's understanding, unless they are very rare and not used much, you are expected to know them. And in the case Anandtech is one of the rare site that focuses on the relatively higher end. SOI isn't something brand new, and if you dont know, you are expected to look it up. No one will spell out Dynamic Random Access Memory in PC publishing or Massive Multi-input Multi-output Antenna in 4G / 5G publishing.prisonerX - Friday, February 28, 2020 - link
YSAK, right?Dizoja86 - Friday, February 28, 2020 - link
Yeah, you don't use an abbreviation multiple times before you give the definition. Anyone who has written a 12th grade essay knows that much. I also highly doubt that the majority of readers on this site know that particular abbreviation off the top of their heads.Holliday75 - Friday, February 28, 2020 - link
I am guilty. I have seen it used over the years, but could not remember.Kevin G - Thursday, February 27, 2020 - link
I wonder if this is a move to secure wafers long term if the fabs who are currently on leading edge processes do end up adopting SOI down the road. Much of the technology currently in use on bulk leading edge can be made to work with SOI though it is currently not adopted due to an imbalance in cost/benefit. As transistors continue to get smaller that could change.FunBunny2 - Thursday, February 27, 2020 - link
so sad... still no 450mm wafers. progress is so slow.Santoval - Friday, February 28, 2020 - link
450 mm wafer plans have been canned, due to their dubious ROI (either the same or less than that of 300 mm wafers) and the much higher difficulty and cost of handling and processing them. While with 450 mm wafers you can have many more dies per wafer, if the wafers cost 4 times more than 300 mm wafers (as is currently estimated) the high numbers of dies per wafer does not really matter.Zizy - Friday, February 28, 2020 - link
Nobody cares about 450mm. There is a very small improvement in utilization of wafer until you get to very large dies, and those aren't really viable due to yield.Additionally, you get troubles in every single step on the way - people making ingots have it harder, all tools need to be redesigned and made bigger, and people carrying those hot lots around also complain because of twice the weight.
Santoval - Friday, February 28, 2020 - link
Silicon ingots for 450 mm wafers are not just twice as heavy as those for 300 mm wafers. They are *three* times heavier, at roughly one ton each. Furthermore, a FOUP (a special plastic enclosure for holding and carrying wafers) with 25 450 mm wafers weighs a whopping 45 kg, while a FOUP with 25 300 mm wafers weighs only 7.5 kg. Everything (from ingots to step-and-scan systems) needs to be bigger, much heavier, quite costlier and more time consuming to make the transition to 450 mm wafers a reality.dotjaz - Friday, February 28, 2020 - link
Why would you need 450mm wafers? What progress does it represent beyond one number?eastcoast_pete - Friday, February 28, 2020 - link
Are these 300 mm wafers to be used for GloFo's 12 nm FDSOI (fully-depleted silicon on insulator)? The article (apparently from a press release) omits any details on that. At least one of the Fabs named was retrofitted for 12 nm FDSOI, which is supposed to be especially power efficient. Some information on that power efficiency would be great, too!Dragonstongue - Friday, February 28, 2020 - link
ROFL...I can only "assume" most folks who come to sites such as this absolutely KNOW what SOI is, as others have pointed out, maybe some "not known" other abbreviations it would be helpful, but SOI has been a VERY long time in use decade+ is anything but a "new term"..I myself do not get the "undies in a bunch" commentary, upset because? did not spell out what SOI stands for till a few sentences in..does it REALLY MATTER?
Ii would be picking more upon when product announcement is given (to them, from the makers) but does not include things such as battery size, if there is 3.5mm jack, type of power connectors, P/E cycles and such things.
but not IMHO for such a silly thing as SOI..that is my .02c
GreenReaper - Friday, February 28, 2020 - link
FWIW, I'm a computer geek, not a silicon geek. I would've guessed silicon-on-interposer, not insulator, because interposers are talked about frequently with relation to silicon chip substrates.People are getting up in arms about things that would normally be covered by an sub-editor, and they are not seeing them here - such inconsistencies suggests that normal phase is missing.
andrewaggb - Friday, February 28, 2020 - link
SOI was all the rage for most of the 2000's. People following tech news during those years should know it well but after that it's pretty understandable that people don't necessarily know what it is.dotjaz - Friday, February 28, 2020 - link
What an ignorant comment! You can't assume people in their 20s would know SOI. The last time SOI making waves it was mid-2000s, by the time 45nm SOI hit the market, we already know there won't be a 28nm and smaller node for the decade to come. People get into technology world in the 2010s won't necessarily know what it is from bits and pieces reported about 28FDS 22FDX 14HP 12FDX.haukionkannel - Friday, February 28, 2020 - link
Most likely next gen Zen3 cpus have these in IO chip part and clobal foundaries Expect to be selling those a lot!