The reason is (obviously) the very tight integration between iOS and hardware. That is not possible with Android due to the many phone and mobile SoC manufacturers.
No, it's because for Android it's a marketing gimmick. My phone does fine with 4GB, would probably still be fine with 2/3GB for most users. Haven't suffered from windows reloading unless it's e.g. browser if it's been a couple of hours.
Android doesn't cache near as much as iOS on the NAND flash / SSD or compress RAM. So it needs more RAM. I don't understand what is with the amount of RAM. If you pay 1000€ for an iPhone and works great with 4 GB RAM but high duration SSD, fantastic; if I pay 1000€ for my S20 Ultra with 12 GB RAM and it works also fine, why would I Care?! Same price, same end result.
I thought i already mentioned better power efficiency, but you dont seem to know whats going on here. signaling across the PCB is never more efficient than signaling that doesnt leave silicon. HBM is vastly more efficient than LPDDR5 in terms energy per bit. now if you are comparing 500GB/s to 50GB/s thats a different story. but you can always down clock HBM.
I suspect the only reason we dont yet see HBM phones is cost and yield and lack of sufficient supply. not yet but should be soon.
Isn't HBM is an expensive, high power offering not built for mobile at all?
Samsung developed more that one generation of "Wide I/O" which they more or less pitched as mobile HBM, but I'm not aware of any products that ever used it.
So looking into it more, Wide I/O was last talked about in 2016, and papers on similar standards have tapered off as well. IDK what happened, but I'd guess they hit some kind of roadblock.
HBM is not high power its high bandwidth. if its more efficient with energy use per bit than its better than something thats less efficient. who are you to say "its not developed for mobile at all"
now that doesnt mean you put 4 HBM stacks for 1TB/s bandwidth in a smart phone. it probably would have to have other changes as well, like slower refresh and others. the point i was making was that. i rather have 2.5D stacking in a phone than just increase capacity from 12GB to 16GB
You are mistaken. HBM uses 128-bit wide channels, while standard DDR uses 64-bit channels. The whole point, and the main mechanism, behind LPDDR, as used in phones, is to use narrower channels, 16 or 32 bits wide, to save power.
The shorter signal lines HBM usually has going for it also do not apply - phones almost exclusively use package-on-package configurations for LPDDR, where lines are even shorter than in HBM setups.
Thus HBM is not more efficient per bit, it's about the same, or slightly worse. But HBM is _much_ worse when the high bandwidth is not required, as is the case most of the time for phones. That's where LPDDR has massive savings, and is - by far - the more efficient technology.
HBM in phones is absolutely pointless, when the huge bandwidth is not required (which it isn't).
yea you are probably right. i shouldnt have said HBM. I should have said, i prefer 3D stacking over more memory. It has to be a new technology to incorporate elements from HBM and LPDDR5
Yeah im playing with you, semantics. Not saying samsung wont develop a "LP-HBM", but HBM2 isnt what you would want in your phone. Ultimatley all DRAM will likley end up over silicon at some point, for mobiles probably "via"d in through the top or bottom of the SOC. Probably sooner than later too with the speed of mobile SOC dev.
yup. at least not ONLY HBM as phones are considered good with INSTANT responses not when they crunch 70 apps in background. And that is domain of DDR not HBM.
>I thought i already mentioned better power efficiency, but you dont seem to know whats going on here. signaling across the PCB is never more efficient than signaling that doesnt leave silicon.
Smartphones stack the DRAM on top of the SOC, so signaling doesn't go across the PCB, which neutralizes some of the advantage of HBM.
Smartphones stack the DRAM on top of the SOC, so signaling doesn't go across the PCB, which neutralizes some of the advantage of HBM.
well if thata the case then i dont seem to know whats going on lol. but joking aside, i dont think its like u describe either. they dont use interposers or 3d stacking yet. and many phones do put it across the PCB.
just to add: it looks like LPDDR5 is a form of "package on package" and it will use way more power per bit than HBM/2.5D/3D stacking/ or other ways of connecting TSVs together directly.
@azfacea : Well I wish as well to see smartphones with Non Volatile Memory (NVM) High Bandwith Memory (HBM) DRAM with at least 64GB of NVM HBM made for example of MRAM (SOT-MRAM), or Nantero Carbon Nanotubes RAM (NRAM).
It would make a pool of low latency memory with the full Operating System (OS) in it, and would greatly improve the user experience like replacing an HDD by a SSD make feel a laptop computer much more snappy.
Unfortunately, such dream is unlikely to happen before at least 2025 as DRAM manufacturers and smartphone manufacturers don’t yet have much incentive to invest in such disrupting technologies (too costly, and therefore not profitable enough)
"HBM is vastly more efficient than LPDDR5 in terms energy per bit." I strongly doubt that's the case. I think you are confusing LPDDR4/5 with DDR4/5 and GDDR5/6. Even against those though HBM is nowhere close to being "vastly" more energy efficient. For HBM to be so much more efficient than LPDDR5 or even more efficient at all, an LP version of HBM would need to be developed. That has not yet happened, and as far as I know there are no plans for that to happen. Merely downclocking HBM would not be a solution. If it was LPDDR would not exist, only downclocked DDR.
i think its time for quad channel memory in desktop. memory bandwidth gains have been pretty poor compared to CPU core count and APU growth. just going to ddr5 is not going to do it. we need quad channel ddr5. also putting 2 dimms on a single channel can never be a good thing for latency and latency sensitive gaming.
there is a small chance AMD will grant my wish with AM5, there is 0.00 % chance with shintel
4-channel memory on desktop is most useful for CPUs with embedded graphics, neither TR no Core XE have that, and too expensive to have that anyway. 4 channels of DDR5 are fast enough to have embedded graphics of the performance similar to Radeon 5500 or Geforce 1650. And in homogeneous configuration would enable extensibility of iGPU by add-in GPU instead of replacing it completely.
Hum... by which logic can an increase in the number of memory channels translate in better latency? In fact, in practice, that's the opposite of what we see on HEDT platforms. They have significantly worse memory latency than the mainstream ones.
It is not about memory channels, it is about slots being on the CPU package physically reducing the length of connectors. And yes, at present speeds it does play a big role in memory latency (speed of light in metal is not c if you are willing to make some calculations).
Standard config for most snapdragon devices is RAM on top of SoC. I have never understood how that doesn't cause a hot zone, but that is why I'm not an electrical engineer.
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nandnandnand - Tuesday, February 25, 2020 - link
"I've been looking forward to this."I didn't expect a mix of 12 Gb and 8 Gb chips, that is weird.
So what's next? 20 GB or straight on to 24 GB (such as 12x 16Gb)?
TeXWiller - Tuesday, February 25, 2020 - link
The DDR5 DIMMs will have two independent channels per DIMM, apparently.azfacea - Tuesday, February 25, 2020 - link
would i rather have 8GB of hbm2 in a flagship phone or 16GB LPDDR5? i mean better power, way more bandwidth .... its not like 8GB is not enough.The Chill Blueberry - Tuesday, February 25, 2020 - link
Phones are soon going to have more memory than storageyeeeeman - Wednesday, February 26, 2020 - link
Not really. Storage is already at 1tb and increasing. I don't see how ram could reach and overtake that figure in the next year or two.Santoval - Wednesday, February 26, 2020 - link
I believe Blueberry was jesting.29a - Wednesday, February 26, 2020 - link
For some reason Apple doesn't seem to have that problem. The XS gets by on 4 GB of RAM.Santoval - Wednesday, February 26, 2020 - link
The reason is (obviously) the very tight integration between iOS and hardware. That is not possible with Android due to the many phone and mobile SoC manufacturers.RSAUser - Sunday, March 1, 2020 - link
No, it's because for Android it's a marketing gimmick.My phone does fine with 4GB, would probably still be fine with 2/3GB for most users. Haven't suffered from windows reloading unless it's e.g. browser if it's been a couple of hours.
rmcrys - Wednesday, July 21, 2021 - link
Android doesn't cache near as much as iOS on the NAND flash / SSD or compress RAM. So it needs more RAM. I don't understand what is with the amount of RAM. If you pay 1000€ for an iPhone and works great with 4 GB RAM but high duration SSD, fantastic; if I pay 1000€ for my S20 Ultra with 12 GB RAM and it works also fine, why would I Care?! Same price, same end result.danielfranklin - Tuesday, February 25, 2020 - link
And only half the battery life!azfacea - Tuesday, February 25, 2020 - link
I thought i already mentioned better power efficiency, but you dont seem to know whats going on here. signaling across the PCB is never more efficient than signaling that doesnt leave silicon. HBM is vastly more efficient than LPDDR5 in terms energy per bit. now if you are comparing 500GB/s to 50GB/s thats a different story. but you can always down clock HBM.I suspect the only reason we dont yet see HBM phones is cost and yield and lack of sufficient supply. not yet but should be soon.
brucethemoose - Tuesday, February 25, 2020 - link
Isn't HBM is an expensive, high power offering not built for mobile at all?Samsung developed more that one generation of "Wide I/O" which they more or less pitched as mobile HBM, but I'm not aware of any products that ever used it.
brucethemoose - Wednesday, February 26, 2020 - link
So looking into it more, Wide I/O was last talked about in 2016, and papers on similar standards have tapered off as well. IDK what happened, but I'd guess they hit some kind of roadblock.azfacea - Wednesday, February 26, 2020 - link
HBM is not high power its high bandwidth. if its more efficient with energy use per bit than its better than something thats less efficient. who are you to say "its not developed for mobile at all"now that doesnt mean you put 4 HBM stacks for 1TB/s bandwidth in a smart phone. it probably would have to have other changes as well, like slower refresh and others. the point i was making was that. i rather have 2.5D stacking in a phone than just increase capacity from 12GB to 16GB
thomasg - Wednesday, February 26, 2020 - link
You are mistaken.HBM uses 128-bit wide channels, while standard DDR uses 64-bit channels.
The whole point, and the main mechanism, behind LPDDR, as used in phones, is to use narrower channels, 16 or 32 bits wide, to save power.
The shorter signal lines HBM usually has going for it also do not apply - phones almost exclusively use package-on-package configurations for LPDDR, where lines are even shorter than in HBM setups.
Thus HBM is not more efficient per bit, it's about the same, or slightly worse. But HBM is _much_ worse when the high bandwidth is not required, as is the case most of the time for phones. That's where LPDDR has massive savings, and is - by far - the more efficient technology.
HBM in phones is absolutely pointless, when the huge bandwidth is not required (which it isn't).
azfacea - Friday, February 28, 2020 - link
yea you are probably right. i shouldnt have said HBM. I should have said, i prefer 3D stacking over more memory. It has to be a new technology to incorporate elements from HBM and LPDDR5danielfranklin - Tuesday, February 25, 2020 - link
Yeah im playing with you, semantics. Not saying samsung wont develop a "LP-HBM", but HBM2 isnt what you would want in your phone.Ultimatley all DRAM will likley end up over silicon at some point, for mobiles probably "via"d in through the top or bottom of the SOC.
Probably sooner than later too with the speed of mobile SOC dev.
azfacea - Wednesday, February 26, 2020 - link
yes definitely, sillicon stacking is coming to phones.deil - Wednesday, February 26, 2020 - link
yup. at least not ONLY HBM as phones are considered good with INSTANT responses not when they crunch 70 apps in background. And that is domain of DDR not HBM.saratoga4 - Wednesday, February 26, 2020 - link
>I thought i already mentioned better power efficiency, but you dont seem to know whats going on here. signaling across the PCB is never more efficient than signaling that doesnt leave silicon.Smartphones stack the DRAM on top of the SOC, so signaling doesn't go across the PCB, which neutralizes some of the advantage of HBM.
azfacea - Wednesday, February 26, 2020 - link
Smartphones stack the DRAM on top of the SOC, so signaling doesn't go across the PCB, which neutralizes some of the advantage of HBM.well if thata the case then i dont seem to know whats going on lol.
but joking aside, i dont think its like u describe either. they dont use interposers or 3d stacking yet. and many phones do put it across the PCB.
azfacea - Wednesday, February 26, 2020 - link
just to add: it looks like LPDDR5 is a form of "package on package" and it will use way more power per bit than HBM/2.5D/3D stacking/ or other ways of connecting TSVs together directly.so it looks i did know what was going on.
levizx - Wednesday, February 26, 2020 - link
Name that "many phones"? I know for certain Snapdragon 6/7/8 series come with packaged LPDDR for years, same with Kirin and Apple A.Diogene7 - Wednesday, February 26, 2020 - link
@azfacea : Well I wish as well to see smartphones with Non Volatile Memory (NVM) High Bandwith Memory (HBM) DRAM with at least 64GB of NVM HBM made for example of MRAM (SOT-MRAM), or Nantero Carbon Nanotubes RAM (NRAM).It would make a pool of low latency memory with the full Operating System (OS) in it, and would greatly improve the user experience like replacing an HDD by a SSD make feel a laptop computer much more snappy.
Unfortunately, such dream is unlikely to happen before at least 2025 as DRAM manufacturers and smartphone manufacturers don’t yet have much incentive to invest in such disrupting technologies (too costly, and therefore not profitable enough)
Santoval - Wednesday, February 26, 2020 - link
"HBM is vastly more efficient than LPDDR5 in terms energy per bit."I strongly doubt that's the case. I think you are confusing LPDDR4/5 with DDR4/5 and GDDR5/6. Even against those though HBM is nowhere close to being "vastly" more energy efficient. For HBM to be so much more efficient than LPDDR5 or even more efficient at all, an LP version of HBM would need to be developed.
That has not yet happened, and as far as I know there are no plans for that to happen. Merely downclocking HBM would not be a solution. If it was LPDDR would not exist, only downclocked DDR.
peevee - Tuesday, February 25, 2020 - link
Put those on SODIMMs, plug 4 of those into 4 sides of a next-gen desktop CPU with 4 memory channels for low latency and simple MB, and I will buy.azfacea - Tuesday, February 25, 2020 - link
i think its time for quad channel memory in desktop. memory bandwidth gains have been pretty poor compared to CPU core count and APU growth. just going to ddr5 is not going to do it. we need quad channel ddr5.also putting 2 dimms on a single channel can never be a good thing for latency and latency sensitive gaming.
there is a small chance AMD will grant my wish with AM5, there is 0.00 % chance with shintel
bug77 - Wednesday, February 26, 2020 - link
You have quad-channel memory on desktop, you just need to buy a Threadripper or a Core XE.peevee - Thursday, February 27, 2020 - link
4-channel memory on desktop is most useful for CPUs with embedded graphics, neither TR no Core XE have that, and too expensive to have that anyway.4 channels of DDR5 are fast enough to have embedded graphics of the performance similar to Radeon 5500 or Geforce 1650. And in homogeneous configuration would enable extensibility of iGPU by add-in GPU instead of replacing it completely.
ZoZo - Wednesday, February 26, 2020 - link
Hum... by which logic can an increase in the number of memory channels translate in better latency? In fact, in practice, that's the opposite of what we see on HEDT platforms. They have significantly worse memory latency than the mainstream ones.peevee - Thursday, February 27, 2020 - link
It is not about memory channels, it is about slots being on the CPU package physically reducing the length of connectors. And yes, at present speeds it does play a big role in memory latency (speed of light in metal is not c if you are willing to make some calculations).James5mith - Wednesday, February 26, 2020 - link
Many modern smartphone SoC's use PoP: https://en.wikipedia.org/wiki/Package_on_packageStandard config for most snapdragon devices is RAM on top of SoC. I have never understood how that doesn't cause a hot zone, but that is why I'm not an electrical engineer.