Samsung Foundry doesn't really have a history to deliver on time, quality, and volume. They are surely working hard and investing a lot, ( especially from their NAND and DRAM branches ), but it remains to be seen whether they can really compete with TSMC.
I remmber when Apple fabed both with Samsung and TSMC, after reports came that chips fabed at Samsung draw more power than TSMC, they switched completely to TSMC year or couple of years later. If I'm not mistaken it was with Samsung 14nm vs TSMC 16nm. So no Samsung manufacturing process are not the lead nor their 14nm process. Other than dry facts of sizes there more details that may set one manufacturer process from another. Matter of fact their leading Logic fabs have fallen behind TSMC. Now they are in the game of catching up with competition and that why they decided to invest tens of billions USD each year for the next 10 years.
It's because 14LPE 9T has lesser cell size than TSMC's 7.5T One. So Die size of Sammy's A9 is much smaller. And In low clock, 14LPE comsumes power much lesser than 16FF.
In CPU Stress test. S.LSI's 14LPE consumes more power. But In General use, S.LSI's APL0898 has mare battery life perfomance. I'm using my phone for general use. Not an benchmarking machine that driving Geekbench 24/7. Talking 14LPE is inferior node than 16FF in CPU Stress test is very bad joke.
In your logic, TSMC 7FF is inferior than 14++ or 14+++ because they can reach more clock speed.
I could be wrong, but I'm pretty sure they have a prototype. Also, the pdk v0.1 is also available to begin designing on it. So they have finalized the requirements of what is legal in the designs.
Table at the bottom has an error: S1 line is shown as 200mm, but it should be 200mm. Only 6 line is 200mm The global map below is correct, but does not match table
Its time to sell Intel their security flaw getting to the point of too easy for hacker. Now intel lag in both advanced technology amd architueture. Tc in mass production mode and using new material. Amd will be golden winner unless intel bribe harder
Samsung mentioned they did not change pitch going from 7LPP to 5LPE, so density improvements are from diffusion breaks, gate over contact, etc. Since their current output is a third of what it could be, it must be quite low production volume right now. The overall EUV output rate per tool worldwide in 2019 was estimated less than 500 wpd, less than 1000-1500 Samsung targeted for HVM production.
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Vitor - Thursday, February 20, 2020 - link
Intel: Wait, isn't that illegal?nandnandnand - Friday, February 21, 2020 - link
Samsung/TSMC: I will make it legal.ksec - Thursday, February 20, 2020 - link
Samsung Foundry doesn't really have a history to deliver on time, quality, and volume. They are surely working hard and investing a lot, ( especially from their NAND and DRAM branches ), but it remains to be seen whether they can really compete with TSMC.drexnx - Thursday, February 20, 2020 - link
huh? Apple fabbed there for yearsksec - Friday, February 21, 2020 - link
They were not leading edge.mercucu1111 - Friday, February 21, 2020 - link
Samsung leads in 14nm. And TSMC didn't have counterpart of 14LPE in 2015Q1. 16FF has same cell size, CPP, M2P of 20SoC.Samsung leads HKMG, 14nm, 10nm and EUV Process. Why do you think that sammy isn't cutting edge? It is very bad joke.
Eliadbu - Saturday, February 22, 2020 - link
I remmber when Apple fabed both with Samsung and TSMC, after reports came that chips fabed at Samsung draw more power than TSMC, they switched completely to TSMC year or couple of years later. If I'm not mistaken it was with Samsung 14nm vs TSMC 16nm. So no Samsung manufacturing process are not the lead nor their 14nm process. Other than dry facts of sizes there more details that may set one manufacturer process from another. Matter of fact their leading Logic fabs have fallen behind TSMC. Now they are in the game of catching up with competition and that why they decided to invest tens of billions USD each year for the next 10 years.mercucu1111 - Saturday, February 22, 2020 - link
https://pc.watch.impress.co.jp/img/pcw/docs/1209/9...https://pc.watch.impress.co.jp/img/pcw/docs/1209/9...
It's because 14LPE 9T has lesser cell size than TSMC's 7.5T One. So Die size of Sammy's A9 is much smaller. And In low clock, 14LPE comsumes power much lesser than 16FF.
http://drmola.com/files/attach/images/56517/226/04...
On the other hand, 16FF has advantage in high clock. So TSMC's A9 has advantage in CPU Stress test.
mercucu1111 - Saturday, February 22, 2020 - link
https://www.tomshardware.com/news/iphone-6s-a9-sam...In CPU Stress test. S.LSI's 14LPE consumes more power. But In General use, S.LSI's APL0898 has mare battery life perfomance. I'm using my phone for general use. Not an benchmarking machine that driving Geekbench 24/7. Talking 14LPE is inferior node than 16FF in CPU Stress test is very bad joke.
In your logic, TSMC 7FF is inferior than 14++ or 14+++ because they can reach more clock speed.
MASSAMKULABOX - Monday, February 24, 2020 - link
Wasnt their a similar thing with Qualcom Phone Socs? some drew a lot more power than others , especially made for the USA market?levizx - Monday, February 24, 2020 - link
You are comparing 16FF+, TSMC's 2nd gen FinFET, to Samsung's 1st gen (14LPE) which had no competitor after TSMC scrapped their 1st gen (16FF).16FF+ should be compared to 14LPP, which Apple did NOT use.
Curiousland - Thursday, February 20, 2020 - link
Where is the proven technology and prototypes of 4nm and 3nm? Check before using title like that.rpg1966 - Thursday, February 20, 2020 - link
You don't need proven prototypes, to have built the fab with the expectation that it'll produce those designs.Fataliity - Thursday, February 20, 2020 - link
I could be wrong, but I'm pretty sure they have a prototype. Also, the pdk v0.1 is also available to begin designing on it. So they have finalized the requirements of what is legal in the designs.smilingcrow - Thursday, February 20, 2020 - link
5LPE v 7LPPArea Reduction <20%
Is that a mistake as not very impressive.
JKflipflop98 - Thursday, February 20, 2020 - link
Considering their "7nm" process is more like ~16nm or so. . .s.yu - Friday, February 21, 2020 - link
Samsung counts 7LPP-3LPE as a full node, which also shows in the numbers...just more marketing BS.s.yu - Friday, February 21, 2020 - link
GAE...edit, Anandtech, edit.mercucu1111 - Friday, February 21, 2020 - link
7LPP : 100MTr/mm^25LPE : 130MTr/mm^2
4LPE : 140MTr/mm^2
https://news.samsung.com/kr/카드-뉴스-5나노의-벽을-넘은-삼성전자-...
And They said that Area reduction is 25%. Not lesser than 20%.
Samsung's 5/4nm are half nodes. It is 5.5nm node in TSMC.
FullmetalTitan - Thursday, February 20, 2020 - link
Table at the bottom has an error:S1 line is shown as 200mm, but it should be 200mm. Only 6 line is 200mm
The global map below is correct, but does not match table
FullmetalTitan - Thursday, February 20, 2020 - link
Lack of edit strikes again.Should be 300mm* instead of 200mm
boozed - Thursday, February 20, 2020 - link
That's not very logarithmicazfacea - Thursday, February 20, 2020 - link
meanwhile intel is trying to decide whether to grow 14nm capacity by 0.00002 % or to bring back 45nm chipsetsteamet - Thursday, February 20, 2020 - link
Processes has always been defined with two significant figures, why are we all the sudden down to one figure?I mean, if we are talking about eg 20% reduction as significant, the the difference between 7.4 and 6.6 most also be significant!
Krayzieka - Friday, February 21, 2020 - link
Its time to sell Intel their security flaw getting to the point of too easy for hacker. Now intel lag in both advanced technology amd architueture. Tc in mass production mode and using new material. Amd will be golden winner unless intel bribe hardermercucu1111 - Friday, February 21, 2020 - link
They said Area Reduction of 5nm node is 25%. And 3GAE is 45%, 3GAP has progression of BEOL.https://news.samsung.com/kr/카드-뉴스-5나노의-벽을-넘은-삼성전자-...
levizx - Monday, February 24, 2020 - link
"Samsung is collaborating with customers on 6nm, a customized EUV-based process node"There's no need to speculate. 6LPP is for specific customer(s).
mercucu1111 - Wednesday, February 26, 2020 - link
Hua###Anymoore - Wednesday, March 4, 2020 - link
Samsung mentioned they did not change pitch going from 7LPP to 5LPE, so density improvements are from diffusion breaks, gate over contact, etc. Since their current output is a third of what it could be, it must be quite low production volume right now. The overall EUV output rate per tool worldwide in 2019 was estimated less than 500 wpd, less than 1000-1500 Samsung targeted for HVM production.