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  • DanNeely - Tuesday, January 7, 2020 - link

    I'd love to see BW vs Core count graphs for non-server platforms (HEDT, mainstream desktop, laptop, mobile) too.
  • Chaitanya - Tuesday, January 7, 2020 - link

    Isnt DDR5 offering capacity bump rather than speed?
  • Yojimbo - Tuesday, January 7, 2020 - link

    That would really suck. As compute increases it needs more bandwidth.
  • DanNeely - Tuesday, January 7, 2020 - link

    Sort of.

    On the PC a DDR5 dimm will offer 2 independent 32 bit channels instead of 1x64bit, but because the channel speed is nominally doubled each will be as fast as a DDR4 dimm. The reason it's being split into two independent channels is because more independent channels plays nicer with high core count systems.

    So while it won't help naively designed sequential access memory bound single threaded code much if at all overall multi-threaded performance should go up in memory bound cases.
  • TomWomack - Tuesday, January 7, 2020 - link

    I didn't realise there were server platforms with DDR5 even on the drawing board; I suppose it's not a huge leap for AMD to make with their separate memory controller, and AMD were happy to be first to PCIe4.

    Ah, there are leaks suggesting this is Intel Sapphire Rapids (the second 10nm Xeon)
  • DanNeely - Tuesday, January 7, 2020 - link

    It could be for ASIC/FPGA platforms not mainstream systems.
  • jonathanlevitt - Tuesday, June 16, 2020 - link

    That's awesome! Micron states that the move from DDR4 to DDR5 is more than a generational improvement. The new technology comes with new and enhanced features that center around performance and reliability according to https://redbytesite.com/. Some of these features include doubled burst lengths, bank groups, and banks alongside improved refresh granularity.

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