This is exactly the kind of result that makes RISC-V so interesting. I can only imagine what other processors people will come up with based on existing designs. I think in certain areas we'll see a big jump in application specific performance because people don't have to reinvent the wheel and can put resources into specialised features.
We're not talking 10baseT here (though you could). Modern 100 Gbps to 400 Gbps ethernet is seeing round trip times through a switch of around 500 ns (over short distances, obviously), which is comparable to DRAM access times.
Without some kind of lossless ethernet I'd think it'd be a hard protocol to deal with. I guess for NVMeOF you have that, and if this controller is already on that link...
OmniXtend packs TileLink cache coherence messages on top of Ethernet L2 frames, but is its own protocol. Check spec and details on https://github.com/chipsalliance/omnixtend. We get about 1.2 us latency...
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prisonerX - Friday, December 13, 2019 - link
This is exactly the kind of result that makes RISC-V so interesting. I can only imagine what other processors people will come up with based on existing designs. I think in certain areas we'll see a big jump in application specific performance because people don't have to reinvent the wheel and can put resources into specialised features.DanNeely - Friday, December 13, 2019 - link
Cache coherence over ethernet? I'm having trouble seeing how that could work well due to how high ethernet latency is.brucehoult - Saturday, December 14, 2019 - link
We're not talking 10baseT here (though you could). Modern 100 Gbps to 400 Gbps ethernet is seeing round trip times through a switch of around 500 ns (over short distances, obviously), which is comparable to DRAM access times.nimisht - Saturday, December 14, 2019 - link
Without some kind of lossless ethernet I'd think it'd be a hard protocol to deal with. I guess for NVMeOF you have that, and if this controller is already on that link...B_Zvonimir - Saturday, December 14, 2019 - link
OmniXtend packs TileLink cache coherence messages on top of Ethernet L2 frames, but is its own protocol. Check spec and details on https://github.com/chipsalliance/omnixtend. We get about 1.2 us latency...rahvin - Monday, December 16, 2019 - link
0.023mm^2 is crazy small. Thats like a dot on a piece of paper small.nivedita123 - Tuesday, December 24, 2019 - link
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jonnyhawk - Monday, October 26, 2020 - link
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coolmath - Friday, July 23, 2021 - link
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