Depending on how you define that, the Xeon Phi did that with its MCM. It didn't save on latency much it had much higher bandwidth than the six channel DDR4 bus it was socketed in. It would have been interesting to have had a third generation of Xeon Phi with larger HBM2 stacks. Shame Intel's 10 nm troubles killed off the part early on.
Check the time line. It was killed for lack of 10 nm availability. It was to be Intel's first big die on 10 nm with a release date of . Intel formally killed off Knight's Hill in 2017 which was the same year it was initially due. That wasn't supposed to be the first 10 nm chip either. Cannon Lake was originally due in late 2015/early 2016. With 10 nm slipping, Intel had nothing to compete with nVidia in the HPC space during this time. It made no sense to bring a relatively low volume product to market that would not be able to compete.
Intel's Xe line up is indeed replacing Xeon Phi but that was only set in stone after they already had killed off Knight's Hill.
According to one of the project managers at Intel during that time frame, that line of processors was already on precarious ground. Its continuance was predicated on a smooth 10nm development, which clearly didn't happen. Technically speaking, 10nm failures killed the product line, but more accurately phrased, 10nm failings just kicked out the last supporting post for the project.
All-core boost on these parts must be close to their maximum turbo speeds. 64 Zen2 cores churning along at 3.2-3.3 GHz~ that is truly scary (for Intel). These parts are likely what the Archer SC will use
Servethehome was seeing 3.2Ghz actual all-core boost in integer loads on the 225W parts so I would imagine that you'd see the full 3.3 in integer and pretty close to that in FP & AVX loads. So, yeah, it's going to be a slaughtering, especially when you factor in price...
That seems hard to believe: An integer workload basically means single cycle instructions, leaving the pipeline empty and most of the register file idle. Actually I can think of few integer-only workloads that have enough locality to not just strain the RAM channels with e.g. in-memory databases. Even at top clocks, the chip might not pull more than half its TDP, lots of it in cache operations.
AVX and FP workloads on the other hand would fill the pipeline and the register file to the hilt and keep a maximum number of ALUs churning through the various stages in the pipelines: That's where you'd get base clock speeds, because pretty much every transistor on the chip lights up and turns electricity into heat. If that stuff would run at turbo speed any length of time, turbo would become the new base.
Depends....that 3.3Ghz turbo is really crap, not suited for a large numbers of server applications. AMD choses the very low power process from TSMC and now Epyc is in a niche leaving a lot of server market to Intel. On a standard 7nm 64 cores are not even thinkable today, in fact desktop parts turbo much higher with a strong single thread performance. Anyway.....better a single digit market share than nothing.
Not sure what loads you are talking about but to me it sounds amazing. Most servers are VMs and have been for a long time. 64 cores/ 128 threads in one chip sounds amazing for a VM host. That degree of scale up, plus the extra PCIe lanes is just something Intel can't match. Before Epyc you had to cluster boxes to get those numbers and live with the incurred penalty. Now you don't.
Gandolf. " Epyc is in a niche leaving a lot of server market to Intel. " how so ?? more like intel will loose alot of the server market to amd. " On a standard 7nm 64 cores are not even thinkable today " source for this, or you just speculating, and this is just your own thoughts?? " in fact desktop parts turbo much higher with a strong single thread performance " and this is for server, NOT desktop, point is ? come gondalf, grasping at straws trying to make intel look better when with epyc, beats intel practically on every fronts ?
I would like to see AMD partner up with an OEM on workstation builds using their CPUs.
If they can't get the likes of Dell and HP onboard, pick a startup to partner with or build their own workstation reference design that system builders can implement.
Professional users don't want to mess around with DIY - AMD, don't force them to.
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gchernis - Monday, October 21, 2019 - link
256 GB L3. Nice!Valantar - Monday, October 21, 2019 - link
I wonder how big that die would need to be.Samus - Monday, October 21, 2019 - link
Literally the entire wafer :)deil - Tuesday, October 22, 2019 - link
nah, we already have 1G in 10x20 mm so propably like 2 rome CPU's for l3 alone. not that muchshabby - Monday, October 21, 2019 - link
The race to 1 gigabyte of l3 cache is on! 😁Kevin G - Tuesday, October 22, 2019 - link
Depending on how you define that, the Xeon Phi did that with its MCM. It didn't save on latency much it had much higher bandwidth than the six channel DDR4 bus it was socketed in. It would have been interesting to have had a third generation of Xeon Phi with larger HBM2 stacks. Shame Intel's 10 nm troubles killed off the part early on.Gondalf - Tuesday, October 22, 2019 - link
Xeon Phi was not killed for 10nm troubles but because there is a GPU for server at the horizon (on 10nm)Kevin G - Tuesday, October 22, 2019 - link
Check the time line. It was killed for lack of 10 nm availability. It was to be Intel's first big die on 10 nm with a release date of . Intel formally killed off Knight's Hill in 2017 which was the same year it was initially due. That wasn't supposed to be the first 10 nm chip either. Cannon Lake was originally due in late 2015/early 2016. With 10 nm slipping, Intel had nothing to compete with nVidia in the HPC space during this time. It made no sense to bring a relatively low volume product to market that would not be able to compete.Intel's Xe line up is indeed replacing Xeon Phi but that was only set in stone after they already had killed off Knight's Hill.
FullmetalTitan - Thursday, October 24, 2019 - link
According to one of the project managers at Intel during that time frame, that line of processors was already on precarious ground. Its continuance was predicated on a smooth 10nm development, which clearly didn't happen. Technically speaking, 10nm failures killed the product line, but more accurately phrased, 10nm failings just kicked out the last supporting post for the project.nandnandnand - Tuesday, October 22, 2019 - link
1-4 GB of L4 cache stacked on the Zen 4 I/O die. Hopefully on every part from mobile to server.29a - Tuesday, October 22, 2019 - link
AMD will win that one too.AshlayW - Monday, October 21, 2019 - link
All-core boost on these parts must be close to their maximum turbo speeds. 64 Zen2 cores churning along at 3.2-3.3 GHz~ that is truly scary (for Intel). These parts are likely what the Archer SC will useextide - Monday, October 21, 2019 - link
Servethehome was seeing 3.2Ghz actual all-core boost in integer loads on the 225W parts so I would imagine that you'd see the full 3.3 in integer and pretty close to that in FP & AVX loads. So, yeah, it's going to be a slaughtering, especially when you factor in price...abufrejoval - Tuesday, October 22, 2019 - link
That seems hard to believe: An integer workload basically means single cycle instructions, leaving the pipeline empty and most of the register file idle. Actually I can think of few integer-only workloads that have enough locality to not just strain the RAM channels with e.g. in-memory databases. Even at top clocks, the chip might not pull more than half its TDP, lots of it in cache operations.AVX and FP workloads on the other hand would fill the pipeline and the register file to the hilt and keep a maximum number of ALUs churning through the various stages in the pipelines: That's where you'd get base clock speeds, because pretty much every transistor on the chip lights up and turns electricity into heat. If that stuff would run at turbo speed any length of time, turbo would become the new base.
ERJ - Tuesday, October 22, 2019 - link
2.6 is the base speed, 3.3 is boost. You two are saying the same thing.Gondalf - Tuesday, October 22, 2019 - link
Depends....that 3.3Ghz turbo is really crap, not suited for a large numbers of server applications.AMD choses the very low power process from TSMC and now Epyc is in a niche leaving a lot of server market to Intel.
On a standard 7nm 64 cores are not even thinkable today, in fact desktop parts turbo much higher with a strong single thread performance. Anyway.....better a single digit market share than nothing.
zmatt - Tuesday, October 22, 2019 - link
Not sure what loads you are talking about but to me it sounds amazing. Most servers are VMs and have been for a long time. 64 cores/ 128 threads in one chip sounds amazing for a VM host. That degree of scale up, plus the extra PCIe lanes is just something Intel can't match. Before Epyc you had to cluster boxes to get those numbers and live with the incurred penalty. Now you don't.Korguz - Thursday, October 24, 2019 - link
Gandolf. " Epyc is in a niche leaving a lot of server market to Intel. " how so ?? more like intel will loose alot of the server market to amd." On a standard 7nm 64 cores are not even thinkable today " source for this, or you just speculating, and this is just your own thoughts??
" in fact desktop parts turbo much higher with a strong single thread performance " and this is for server, NOT desktop, point is ?
come gondalf, grasping at straws trying to make intel look better when with epyc, beats intel practically on every fronts ?
twtech - Tuesday, October 22, 2019 - link
I would like to see AMD partner up with an OEM on workstation builds using their CPUs.If they can't get the likes of Dell and HP onboard, pick a startup to partner with or build their own workstation reference design that system builders can implement.
Professional users don't want to mess around with DIY - AMD, don't force them to.
kgardas - Tuesday, October 22, 2019 - link
There are several makers of epyc based workstation in the market already. Just google for "amd epyc workstation" and you will see...mdriftmeyer - Wednesday, December 4, 2019 - link
I'm looking forward to Threadripper 4 inside Mac Pros.FreckledTrout - Tuesday, October 22, 2019 - link
This is a fun one. Should make a nice halo server product to say hey look ours is faster even if hardly anyone buys this model.