Quite possible! The 7nm still will be quite expensive next year. So Ryzen 4000 series could use 12+ production node to reduce electricity usage a Little bit and we would see 7nm IO chip at 2021 with Ryzen 5000 series, when 7nm most likely is more affordable than now (Also more mature, so better yealds)
This would be an improvement for AMD to migrate their IO die for the Milian generation of Epyc chips. AMD doesn't inherently need to change their IO die for that generation as the platform is staying the same as Rome for one more generation. Migrating the IO die to a slightly modified process would improve power consumption and gives them an opportunity to increase the number of chiplets in the same socket.
Interesting note about being able to work with HBM. However, the GPU manufacturers are all seemingly looking at TSMC which would constitute the block of chips leveraging HBM. I can only wonder if there is a switch ASIC or similar still contracted at GF that needs this. Then again, perhaps AMD is planning on coupling HBM to their IO die for a unified L4 cache? 32 GB of low(ish) latency memory at 1.5 TB/s of bandwidth would do wonders for AVX-512 or an on-package GPU.
The oddball Intel chip that had an on package AMD gpu with one stack of HBM or even their earlier E-DRAM chips showed the value of lots of bandwidth for the integrated GPU. The IGPU's are largely limited by power consumption and memory bandwidth and ultimately your performance is a result of how much you have of both of those and how efficient you are at using them. A laptop APU with some HBM acting as a cache or even just dedicated video memory would have pretty good performance potential.
HBM would be great for a laptop but it appears that AMD's future endeavors here are all with TSMC's 7 nm node, not GF's 12 nm production.
GF pointed out the HBM support means there should be some customer who wants it but AMD and nVidia are place their next wave of HBM supporting devices on TSMC 7 nm.
AMD could design their 4000 series APUs (using Zen 2) on this node. Since I/O doesn't scale well to 7nm and this seems cheaper to design (and maybe cheaper to manufacture), the lower cost APUs could be a good fit.
I think the I/O die is still on 14nm, if it could move to 12nm LP+, that could mean significant reduction in power. Although that die size is still huge even if it could scale down. ( I/O tends to not scale well )
Anandtech reported that consumer (Ryzen) products use 12nm LP I/O die, while servers use 14nm LP. I've personally found AMD communication confusing about the matter.
I disagree on the lawsuit end. GF is a competitor, and neither a patent troll (e.g., a patents holding company that does not practice any business other than litigation) nor a company that is abusing FRAND licenses. GF has a right to defend its IP. The merits of the case will decided on later, and lawsuits like this may be settled, who knows.
it absoletly is a patent troll. it is going out of semi manufacturing and into the patent troll business. for every gf patent TSMC has 100 patents that GF is infringing.
"the merits of the case" is code for a patent troll thats planning to shut down its fabs and wants TSMC to pay alimony
A 12LP+ APU with 4/8GB of HBM as a graphics cache would be pretty sweet. Dual DDR4 just doesn't cut it in bandwidth terms, example- 11 CU graphics in R5 3400G has ~50GB/s. 16 CU RX 560 has ~112GB/s. (And the APU has to share that with the CPU too). It's not enough.
And I'd say "why not". Intel managed to get very impressive gains out of their 14nm process, so if GF sticks to their 12 nm process for the next few years, they may also see good improvements.
And like danielfranklin says below, not all IC need to be on the latest nodes. I'd say this would even be an option for low(est) budget X86 or ARM CPU if the price is low enough.
Still doesn't look yo be competitive in terms of density power or performance to tsmc 7nm+. And by the time they would start volume manufacture this process - 2021 TSMC will already have 5nm at volume manufacturing for some time. The last aspect where GF could play a role is price but TSMC older processes will get more mature and compete in this front as well. As the saying goes too little too late.
TSMC (and other leading fabs) are going to have to spend ever-increasing amounts on new nodes. Sure, they'll want to improve existing ones to remain profitable and help fund development, but a lot of their funds are going to be going into making transistors even smaller, etc. So, there's definitely a market there for older, bigger nodes. How long that market will last is questionable if a wall is hit at the frontier, but by then smaller fabs might have access to smaller nodes.
If older consoles ever decided to remanufacture their actual silicon, the power savings compared to the last node they were on would be immense. That would be great for one last hurrah on power savings and getting a new manufacture of an older console for gaming preservation.
Would be cool to see this. Cell was shrunk twice from 90 nm to 65 then 45. I believe there were plans to bring it down to shrink it to 32nm that weren't followed through with. Imagine the yields and power efficiency you'd get with it on this process.
It's always good for AMD to have multiple chip sources to cover their bases and negotiate the best prices. GloFo has served AMD well in the past and is likely to continue.
Why are there so many comments about server CPUs and GPUs? Isn't this a low power process? They aren't going to be putting Epyc on a low power process. And volume production is expected in 2021. By that time cutting edge low power chips will be on the 5 nm node, not the 7 nm node. This seems like a lower cost alternative for non-high-end SOCs. So your lower and midrange smartphone SOCs might be built on this process. It also sounds like they are hoping for AI accelerators to use it, since they are mentioning compatibility with HBM, but that's probably more of a wish than something they are actually counting on.
If I were AMD, I would ask GloFo to update the Epyc 3000 socs. (and rename them Opteron). That should go in the microserver gen11 and the like. Now only supermicro really supplies Epyc soc boards. And that is a shame. I like low powered highly dependable servers, and dislike the 2000's performance of an atom. I bought a load of xeon E3's but am very willing to give AMD a try.
I think there's a typo in the first data column of the comparison table. It compares 12LP+ to "12LPP".
I don't think a node called 12LPP exists, certainly not from GlobalFoundries. It should be 12LP. That column means to compare the new node (12LP+) to its predecessor (12LP).
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azfacea - Wednesday, September 25, 2019 - link
stolen from TSMCJoeyJoJo123 - Wednesday, September 25, 2019 - link
And they're still on 12nm!!!https://i.imgur.com/lBQ1sxz.gif
levizx - Sunday, September 29, 2019 - link
Sure, steal SADP and change it completely to LELE GREAT strategydel42sa - Monday, November 4, 2019 - link
12nm EUV ? Coolyeeeeman - Wednesday, September 25, 2019 - link
Great, io die on zen 3 will be 12lp I guesshaukionkannel - Thursday, September 26, 2019 - link
Quite possible! The 7nm still will be quite expensive next year. So Ryzen 4000 series could use 12+ production node to reduce electricity usage a Little bit and we would see 7nm IO chip at 2021 with Ryzen 5000 series, when 7nm most likely is more affordable than now (Also more mature, so better yealds)levizx - Sunday, September 29, 2019 - link
They are already using 12LP (and 14LPP) for IO die AFAIKKevin G - Wednesday, September 25, 2019 - link
This would be an improvement for AMD to migrate their IO die for the Milian generation of Epyc chips. AMD doesn't inherently need to change their IO die for that generation as the platform is staying the same as Rome for one more generation. Migrating the IO die to a slightly modified process would improve power consumption and gives them an opportunity to increase the number of chiplets in the same socket.Interesting note about being able to work with HBM. However, the GPU manufacturers are all seemingly looking at TSMC which would constitute the block of chips leveraging HBM. I can only wonder if there is a switch ASIC or similar still contracted at GF that needs this. Then again, perhaps AMD is planning on coupling HBM to their IO die for a unified L4 cache? 32 GB of low(ish) latency memory at 1.5 TB/s of bandwidth would do wonders for AVX-512 or an on-package GPU.
kpb321 - Wednesday, September 25, 2019 - link
The oddball Intel chip that had an on package AMD gpu with one stack of HBM or even their earlier E-DRAM chips showed the value of lots of bandwidth for the integrated GPU. The IGPU's are largely limited by power consumption and memory bandwidth and ultimately your performance is a result of how much you have of both of those and how efficient you are at using them. A laptop APU with some HBM acting as a cache or even just dedicated video memory would have pretty good performance potential.Kevin G - Wednesday, September 25, 2019 - link
HBM would be great for a laptop but it appears that AMD's future endeavors here are all with TSMC's 7 nm node, not GF's 12 nm production.GF pointed out the HBM support means there should be some customer who wants it but AMD and nVidia are place their next wave of HBM supporting devices on TSMC 7 nm.
Hul8 - Thursday, September 26, 2019 - link
AMD could design their 4000 series APUs (using Zen 2) on this node. Since I/O doesn't scale well to 7nm and this seems cheaper to design (and maybe cheaper to manufacture), the lower cost APUs could be a good fit.scineram - Thursday, September 26, 2019 - link
No.ksec - Wednesday, September 25, 2019 - link
I think the I/O die is still on 14nm, if it could move to 12nm LP+, that could mean significant reduction in power. Although that die size is still huge even if it could scale down. ( I/O tends to not scale well )Death666Angel - Wednesday, September 25, 2019 - link
Epyc and TR are 14nm IO die. Ryzen 3000 is 12nm.scineram - Thursday, September 26, 2019 - link
No.Cooe - Thursday, September 26, 2019 - link
Yes. Maybe use Google first before you "No" something.levizx - Sunday, September 29, 2019 - link
No to your noJasonMZW20 - Thursday, September 26, 2019 - link
They're all on 12nm LP. An early engineering sample of Epyc Rome had a 14nm LPP IO die, but has since been moved to 12nm LP for final products.Epyc's IO die doesn't need to be any larger than it already is.
Rudde - Thursday, September 26, 2019 - link
Anandtech reported that consumer (Ryzen) products use 12nm LP I/O die, while servers use 14nm LP. I've personally found AMD communication confusing about the matter.levizx - Sunday, September 29, 2019 - link
Nope, Matisse IO Die is already 12LPquorm - Wednesday, September 25, 2019 - link
In isolation, that sounds great, but it's hard to see things at GF too favorably amid the lawsuit and asset sales.Mday - Wednesday, September 25, 2019 - link
I disagree on the lawsuit end. GF is a competitor, and neither a patent troll (e.g., a patents holding company that does not practice any business other than litigation) nor a company that is abusing FRAND licenses. GF has a right to defend its IP. The merits of the case will decided on later, and lawsuits like this may be settled, who knows.azfacea - Wednesday, September 25, 2019 - link
it absoletly is a patent troll. it is going out of semi manufacturing and into the patent troll business. for every gf patent TSMC has 100 patents that GF is infringing."the merits of the case" is code for a patent troll thats planning to shut down its fabs and wants TSMC to pay alimony
Haawser - Wednesday, September 25, 2019 - link
A 12LP+ APU with 4/8GB of HBM as a graphics cache would be pretty sweet. Dual DDR4 just doesn't cut it in bandwidth terms, example- 11 CU graphics in R5 3400G has ~50GB/s. 16 CU RX 560 has ~112GB/s. (And the APU has to share that with the CPU too). It's not enough.scineram - Thursday, September 26, 2019 - link
No.Cooe - Thursday, September 26, 2019 - link
What the hell is wrong with you?drexnx - Wednesday, September 25, 2019 - link
nice to see glofo actually iterating and still moving forward with new process tech, even though they dropped their 7nm nodeIrata - Thursday, September 26, 2019 - link
And I'd say "why not". Intel managed to get very impressive gains out of their 14nm process, so if GF sticks to their 12 nm process for the next few years, they may also see good improvements.And like danielfranklin says below, not all IC need to be on the latest nodes. I'd say this would even be an option for low(est) budget X86 or ARM CPU if the price is low enough.
Eliadbu - Wednesday, September 25, 2019 - link
Still doesn't look yo be competitive in terms of density power or performance to tsmc 7nm+. And by the time they would start volume manufacture this process - 2021 TSMC will already have 5nm at volume manufacturing for some time. The last aspect where GF could play a role is price but TSMC older processes will get more mature and compete in this front as well. As the saying goes too little too late.danielfranklin - Wednesday, September 25, 2019 - link
Its not intended to be bleeding edge.Far more of the worlds ICs are made on older nodes then the latest ones.
Tams80 - Thursday, September 26, 2019 - link
TSMC (and other leading fabs) are going to have to spend ever-increasing amounts on new nodes. Sure, they'll want to improve existing ones to remain profitable and help fund development, but a lot of their funds are going to be going into making transistors even smaller, etc.So, there's definitely a market there for older, bigger nodes. How long that market will last is questionable if a wall is hit at the frontier, but by then smaller fabs might have access to smaller nodes.
Kamen Rider Blade - Wednesday, September 25, 2019 - link
If older consoles ever decided to remanufacture their actual silicon, the power savings compared to the last node they were on would be immense. That would be great for one last hurrah on power savings and getting a new manufacture of an older console for gaming preservation.Tilmitt - Wednesday, September 25, 2019 - link
Would be cool to see this. Cell was shrunk twice from 90 nm to 65 then 45. I believe there were plans to bring it down to shrink it to 32nm that weren't followed through with. Imagine the yields and power efficiency you'd get with it on this process.Kamen Rider Blade - Thursday, September 26, 2019 - link
PS2's CPU/GPU ended on 65nm, imagine what you can do for that =DTechie2 - Wednesday, September 25, 2019 - link
It's always good for AMD to have multiple chip sources to cover their bases and negotiate the best prices. GloFo has served AMD well in the past and is likely to continue.Yojimbo - Wednesday, September 25, 2019 - link
Why are there so many comments about server CPUs and GPUs? Isn't this a low power process? They aren't going to be putting Epyc on a low power process. And volume production is expected in 2021. By that time cutting edge low power chips will be on the 5 nm node, not the 7 nm node. This seems like a lower cost alternative for non-high-end SOCs. So your lower and midrange smartphone SOCs might be built on this process. It also sounds like they are hoping for AI accelerators to use it, since they are mentioning compatibility with HBM, but that's probably more of a wish than something they are actually counting on.levizx - Sunday, September 29, 2019 - link
You do realise Epyc has an I/O die, right?Foeketijn - Thursday, September 26, 2019 - link
If I were AMD, I would ask GloFo to update the Epyc 3000 socs. (and rename them Opteron).That should go in the microserver gen11 and the like.
Now only supermicro really supplies Epyc soc boards. And that is a shame.
I like low powered highly dependable servers, and dislike the 2000's performance of an atom.
I bought a load of xeon E3's but am very willing to give AMD a try.
Kamen Rider Blade - Thursday, September 26, 2019 - link
Don't forget that AMD still has their Chipset & Central IO Die that they need to produce.The X570 could definitely use a node shrink along with the Central IO Die.
Don't forget the upcoming TRX40/80 & WRX80 chipsets.
All those could benefit from this process.
JoeDuarte - Monday, February 22, 2021 - link
I think there's a typo in the first data column of the comparison table. It compares 12LP+ to "12LPP".I don't think a node called 12LPP exists, certainly not from GlobalFoundries. It should be 12LP. That column means to compare the new node (12LP+) to its predecessor (12LP).
Matthias B V - Saturday, March 6, 2021 - link
AMD could use those for their I/O even untill 2022 as they scale worse anyway.I was wondering if they Port Zen+ to 12nm+ and sell them as Athlon or Duron. With the additional 20% they wouldn't bee too bad.
Or maybe a Vega 12nm+ for mining.