As you say, form-factor could be key: Even M.2 seems feasible with that, even if most notebooks have a UPS by default. Right-sizing the capacitors just to the point where over the life-time of the product you can sustain the worst possible dirty buffer flush say with a couple of block erases ongoing at the same time, may not be trivial while capacitance is neither cheap nor small.
Just the relief on the firmware designers who are asked to squeeze ever more tuples variations out of trapped electrons could be a good motive: At least the write-back cache can now be relied upon!
I know that MRAM technology is still in its early development, but I am really, really looking forward that a at least 64Gbit Spin Orbit Torque (SOT) MRAM chip (8GB) to be mass produced to replace L1 / L2 / L 3 SRAM cache and probably DRAM, for ecample in a smartphone use case : I believe it has the potential to importantly reduce software latency, which is a real pain...
I believe it will be disruptive a bit like NAND flash SSD is an important improvement compared to mechanical HDD in software latency on computers...
The fastest MRAM can reach L2 cache latencies, however only at small sizes and somewhat low densities (i.e. at older nodes). MRAM is like SRAM in some sense : as its size increases its latency starts deteriorating, quite fast. While MRAM *could* replace L2 & L3 cache at an equivalent latency (and possibly at a quite larger size due to its much higher density than 6T-SRAM) I am not sure if Everspin's STT-MRAM specific variant could do it. In any case L1 cache is off limits.
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abufrejoval - Wednesday, July 31, 2019 - link
As you say, form-factor could be key: Even M.2 seems feasible with that, even if most notebooks have a UPS by default. Right-sizing the capacitors just to the point where over the life-time of the product you can sustain the worst possible dirty buffer flush say with a couple of block erases ongoing at the same time, may not be trivial while capacitance is neither cheap nor small.Just the relief on the firmware designers who are asked to squeeze ever more tuples variations out of trapped electrons could be a good motive: At least the write-back cache can now be relied upon!
Diogene7 - Wednesday, July 31, 2019 - link
I know that MRAM technology is still in its early development, but I am really, really looking forward that a at least 64Gbit Spin Orbit Torque (SOT) MRAM chip (8GB) to be mass produced to replace L1 / L2 / L 3 SRAM cache and probably DRAM, for ecample in a smartphone use case : I believe it has the potential to importantly reduce software latency, which is a real pain...I believe it will be disruptive a bit like NAND flash SSD is an important improvement compared to mechanical HDD in software latency on computers...
AshlayW - Sunday, August 4, 2019 - link
Would that really have low enough latency to be useful as an L1 or even L2 cache?Santoval - Monday, October 28, 2019 - link
The fastest MRAM can reach L2 cache latencies, however only at small sizes and somewhat low densities (i.e. at older nodes). MRAM is like SRAM in some sense : as its size increases its latency starts deteriorating, quite fast. While MRAM *could* replace L2 & L3 cache at an equivalent latency (and possibly at a quite larger size due to its much higher density than 6T-SRAM) I am not sure if Everspin's STT-MRAM specific variant could do it. In any case L1 cache is off limits.