5nm likely is right now is a disaster for power density and leakage on high power SKUs. Looking at Ryzen 2 core temperatures, i have some doubts the suboptimal power savings of 5nm are enough to compensate the higher temperature spikes on silicon and the temperature leakage that severly limit right now the ability to clock high all cores up on the 7nm tech showed on Zen 2.
stability, usually more mature nodes have better yelds, its all end up more/less that bleeding edge have twice the cost of last gen. if they can offer same hardware, new tweaks -> better thing, at almost no cost. its not that bad of a deal, as long as you dont have to be top of the top.
TSMC is a FOUNDRY!!! Read that sentence ten times!!!
This means that they are NOT in the business of "leading edge and nothing else"; they are in the business of giving customers what's useful. And TSMC has MANY customers.
So if you are starting a design from scratch, sure, target 5nm. But if you have an existing design you can tweak it just very slightly and get a nice almost free boost.
People still use 28nm (let alone 45 or 65nm). They'll still be using 7nm many years from now. And if TSMC has, as part of their sales pitch, that they keep improving even the non-leading processes, well, that helps keep customers happy.
5nm isn't as refined yet, so you'll have more bad chips per wafer, pushing up costs, with probably lower performance, and it would have more issues binning as less chips.
7nm is already known and refined, so you know what the yields are, your architecture is tweaked to take advantage of the node, etc.
It would take a bit before they move to 5nm, maybe 2020 on some special, lower power parts, with 2021 probably hitting mainstream. It takes a couple of years from first customer orders with tests to actual launch in the customer's hands, TSM already had customer trials of 7nm end of 2017, and you've only seen 7nm parts in 2019, expect something similar for 5nm.
It, unfortunately, doesn't quite work that way. Maybe, yes, but then, maybe not. Gate leakage increases with smaller and smaller pitch sizes. So... It's more about making each core do more, rather than go faster. Faster is good, more efficient at doing the same per cycle is better.
There's work around new transistor architectures, to replace finfet while reducing leakage, improving density, lowering voltage/power, and reducing electrostatic lag: GAA, vertical nanowire, 3D-stacked complementary FET... All rumors to the contrary notwithstanding, we're still quite far from hitting the quantum wall, from the manufacturing side of things, in terms of improving processing density and performance. But yes, better processor architectures can be helpful also.
Right. Exactly Santoval. It's at this juncture we may really begin to see some decent speed increases, and that's a big maybe. That was why I made the point earlier about increasing efficiency, branching out architecture designs, and making each processor do more per cycle. GAA may allow for 5-7GHz if it's done in the manner they're describing (and not some pseudo-tech/science marketing jargon, which is all that these transistor size measurements have become at this point)
"Making each core do more" in what way exactly? A +7% performance at the same TDP suggests +7% higher clocks at the same TDP, assuming an identical μarch and CPU design. We are talking purely about the performance of the *node* here, so the μarch and the design of the CPU is irrelevant.
"more efficient at doing the same per cycle is better." Yes, that's swell, but that's just an alternative to the mentioned +7% higher performance of the article. It's an "either or" situation, as always : Either you retain the same TDP and extract 7% higher performance (via 7% higher clocks assuming an identical design) or you retain the same performance and lower your TDP budget by 10% at 7nm and 15% at 5nm.
7% higher clocks of the Ryzen 3000 series means 300 MHz higher base & boost clocks on average. Yes, it is harder to raise clocks with each smaller node due to the reasons you mentioned. However the Ryzen 3000 series was released on TSMC's original high performance 7nm node iteration. There is nothing to suggest that the clocks of the Ryzen 3000 series are the max clocks TSMC can reach at 7nm.
Further optimizing their 7nm node (without increasing its density and thus using smaller features at all, which is important) will allow them to reach 7% faster clocks at the same TDP (at least according to them, I am skeptical until I see products) *or* reducing the node's TDP further, which is just as important. The clocks of their 7nm+ and 6nm node will obviously be lower, due to the higher density of these nodes.
There is obviously a finite limit of ~5GHz single core clocks at a TDP of up to ~100W, and that cannot be normally exceeded due to the collapse of Dennard scaling and the slowing down of Koomey's law. The.. abnormal exception is Intel, since according to leaks their top end Comet Lake CPU will reach a single core boost clock of 5.2 GHz. That's because they have been optimizing their 14nm node since ... 2014, and bizarrely in 2020 they will still be releasing 14nm node based CPUs (after Comet Lake comes Rocket Lake) due to the continuing severe issues of their 10nm+ node.
Actually design of cores and ISA have a lot of to do with performance per W & so does the design choice not to persuit the insane clocks. Uper sustainable leaking limit for FinFET is 1.6~1.7 GHz, the final limit should be 2~2.2 GHz which we still see on power optimised many core systems (server chips). Choosing the HD libs instead HP ones when designing power optimised chip will hurt only 100~200 MHz on performance target while it can cut the size/power consumption by up to 50% which we see in mobile (phone) SoC's. The simple OoO designed core like A73 two instructions wide is still about 3~3.5x the size of an in order A55 while performance benefit is about 1.73~1.8x, as you go wider things only get worse regarding those metrics. Scalable ISA (beyond the 64 bit) regarding front end is a key for future performance benefits, especially for SIMD's & DSP's. Simplicity of ISA is crucial for replicating 64 bit general processing blocks (both integer and FP) & tieing them together to work as one, as waiting for instruction execution is also minimised. It's also easyer in such a case to make a simple predictor to go with micro switch. Leading ISA regarding all mentioned is of course RISC V (simplicity, 128 bit finalised & 256 bit on paper) while no one still didn't consider this approach seriously which I hope will change along with unified SIMD approach for which RISC V also left open doors (considering balanced design).
Very unlikely AMD will adopt this new process. It need of a new masks set and it is pretty expensive. Reportedly they want 7nm+ instead. Moreover IMO these clock speed increases are likely on low power phone socs, a little tricky on high power SLUs were the huge 7nm leakage destroy any power saving features implemented on processes. Nearly nothing for too much money in manufacturing
Not all numbers are equal, Intel 14nm++ 5GHz is probably about 4.4-4.5GHz Ryzen 3000 7nm performance, if not a little lower since it's ~15% IPC gain over Intel's.
depends on how much "dark silicon" they must contend with and EVERYONE as they shrink further and further have to increase more and more (losing ground at they go further into making smaller)
still dark silicon will make getting speed and actual performance very small % gains till at "best" Intel when they finally get to "true" 7nm after that it will be more of "how much regression can we handle while getting enough cores/cache to hide the dark silicon"
Nvidia might have pushed the speed way up for G 1xxx / RTX 2xxx however, their seeming "nitrous shot" is not going to be pushing the same frequency speed up as CPU did in years past (simpler design, also much simpler "do not pass go" walls because of such)
will be interesting to see the next 5 odd years as they are fast approaching the end of the silicon line (likely when optical come out and about for me and you, they will do similar "chiplet" so the stuff that not shrink well it at all can be kept in the "old but well known" shrinkage (lol) while the faster but more likely to get "dark silicon" they can only really use "wee bits and pieces"
I suppose, GPU and CPU folks might very well have to do what flash memory makers have done the last decade or what have you, SLC to MLC to TLC to QLC .. CPU/ GPU are more or less at the gap between MLC to TLC (happy spot where endurance and speed are meshing near perfect as is the cost for the capacity per wafer "cut" .. QLC on the other hand is "dark silicon" to keep my explain simple
QLC (much like cpu/gpu die shrink at this point) has very few advantages other than cost to produce (very little difference in cost for me and you) as well due to their "size they need to be" the capacity goes up (though performance drops significantly compared to the cost advantage i.e not much capacity/price advantage to really anyone vs "real world" usage (drop endurance a full 1/2 or more, few % less pricey .. seems more a way to get rid of crap wafers than viable drives (what do I know .. likely them makers not chuck anything in garbage if they find a way to make .01 become 100 ^.^
If we look at GPU .. 300mm/2 of today @ 12nm is something like 1200@ 65mn (something like that) so it seems "on paper" the newest fastest GPU/CPU are "fast" reality says they have just gotten far far better at "hiding deficits" (DDR4 higher bandwidth but more "sluggish" we as users only "see" the image painted, not being painted (i.e they get better at hiding or shifting the "deficit".
I honestly not see AMD really pushing to get 5+Ghz "all cores" as power use rises many times over going from 3-4Ghz, from 4-5 is WAY more power/heat even though was the same "% of increase" it is not a +1 = -1 scale .. +1 on speed might mean +15 power, minus 1 speed might mean save 5% power (they have very odd "sweet spots" though no one is immune from this, not Nvidia, not Intel, not IBM even (hell IBM had 5Ghz all core for a LONG TIME.. but, it cost a bunch of electricity and belch heat like crazy (9900k / Bulldozer / Pentium 965 ^.^
No it's not. TSMC's 5nm node will be even harder to reach clocks in the 4.8 to 5GHz range. Smaller features = higher leakage = more heat = lower clocks. TSMC's 2nd gen DUV 7nm node is different because apparently it is a highly optimized version of their original HP 7nm without increasing density at all. A Ryzen 9 3900X fabbed on that node could reach up to a single core 4.9 GHz boost clock with it.
5 GHz boost clocks might have been possible with GAA-FETs (not in their original iteration, after they were quite optimized), but TSMC is not going to introduce GAA-FETs at 5nm. They will at 3/4nm, because at this scale FinFETs will completely run out of steam.
edit : Sorry, I thought you were referring to TSMC's 5nm node (too bad there is no edit option). TSMC at 7nm+ might reach higher clocks, but probably not in the 5 GHz range. It will depend on how much clocks they will gain from the EUV layers and how much they will lose from the 18 - 20% higher transistor density (it will be a balance between these two).
Same clock at a lower node would be higher IPC, I don't understand why people care about hitting 5GHz instead of pure performance numbers. 5GHz is a marketing spiel.
It's in risk. None of this is silent, TSMC has been very open with the schedules.
The schedule is basically identical to 7nm, shifted by two years. Which almost certainly means Apple will be on 5nm with 2020 A14, as the first large volume release.
A13 is likely on this 7nmP. (It's all somewhat unclear, but it seems like Apple is NOT using 7nm+, probably because of concerns that TSMC won't be able to provide the volumes Apple needs with its current amount of EUV equipment.)
I just don't get it. The engineering is impressive but where is the benefit to the user. CPU technology using silicon hit the wall(s) many years ago and stalled at 4-5ghz. 12nm or 5nm performance is unchanged. 7nm and 5nm may reduce power for mobile devices but no performance gains for those of us with desktops. Intel once promised a 10ghz cpu - now a fairytale. Few single users will benefit from a 16, 32, or 64 core cpus. I see a lot of marketing hype with no real hope for any significant performance breakthroughs until we find a silicon replacement. Once found it may take a decade to reach consumers. Moore's law is long dead. Are we flogging a dead horse?
Wider cores, more cache and better predictors all help single core performance. E.g. Ice lake has similiar single core performance to Whiskey lake, even though Ice lake runs 1GHz slower. Gaming has seen used threads climb towards 16 threads, where as a few years ago 8 threads was the maximum. There is a shift toward accelerators doing the heavy work and cpus being used for shifting data and light processing.
I'm struggling with the suggestion that N6 will be a "long node", considering it's coming out just months before N5, and N7+ with better performance is reportedly being used for volume production already.
I get that we might see slight refreshes of Navi 10 and Zen 2 chiplets, but I doubt very high-volume mobile SoC vendors like Qualcomm and Apple will choose to reuse designs for N6 instead of making something from the ground up for N7+. And for 2021 updates they'll most probably use N5.
TSMC is trying to get 28nm customers over to N7. Those customers can move to N6 without having to redesign. TSMC expects those customers to stay at N6 for a long time.
Intel advetrise Ice Lake like plain 10nm, from the official process roadmap 10nm+ will be available only in 2020 with the Willow Cove core. If old data are valid at that point 14nm and 10nm will have the same drive current. This is consistent with some voices about a Sunny Cove/Willow Cove S for desktop in 2H/2020.
But i think the situation is fliud, the only certain thing is about a "silicon back" of Tiger Lake (Willow Cove +Xe) for Laptops.
In 2021 there will be 10nm ++ and first edition of 7(5)nm process.
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Rudde - Tuesday, July 30, 2019 - link
What is the downside? Is it more expensive per chance, or does it launch later? Why don't they jump straight to it on 5nm?Gondalf - Wednesday, July 31, 2019 - link
5nm likely is right now is a disaster for power density and leakage on high power SKUs.Looking at Ryzen 2 core temperatures, i have some doubts the suboptimal power savings of 5nm are enough to compensate the higher temperature spikes on silicon and the temperature leakage that severly limit right now the ability to clock high all cores up on the 7nm tech showed on Zen 2.
psychobriggsy - Wednesday, July 31, 2019 - link
https://fuse.wikichip.org/news/2567/tsmc-talks-7nm...Refinement that comes with time.
Rudde - Wednesday, July 31, 2019 - link
Thanks.deil - Wednesday, July 31, 2019 - link
stability, usually more mature nodes have better yelds, its all end up more/less that bleeding edge have twice the cost of last gen.if they can offer same hardware, new tweaks -> better thing, at almost no cost. its not that bad of a deal, as long as you dont have to be top of the top.
name99 - Wednesday, July 31, 2019 - link
TSMC is a FOUNDRY!!!Read that sentence ten times!!!
This means that they are NOT in the business of "leading edge and nothing else"; they are in the business of giving customers what's useful. And TSMC has MANY customers.
So if you are starting a design from scratch, sure, target 5nm. But if you have an existing design you can tweak it just very slightly and get a nice almost free boost.
People still use 28nm (let alone 45 or 65nm). They'll still be using 7nm many years from now. And if TSMC has, as part of their sales pitch, that they keep improving even the non-leading processes, well, that helps keep customers happy.
RSAUser - Thursday, August 1, 2019 - link
5nm isn't as refined yet, so you'll have more bad chips per wafer, pushing up costs, with probably lower performance, and it would have more issues binning as less chips.7nm is already known and refined, so you know what the yields are, your architecture is tweaked to take advantage of the node, etc.
It would take a bit before they move to 5nm, maybe 2020 on some special, lower power parts, with 2021 probably hitting mainstream. It takes a couple of years from first customer orders with tests to actual launch in the customer's hands, TSM already had customer trials of 7nm end of 2017, and you've only seen 7nm parts in 2019, expect something similar for 5nm.
azfacea - Tuesday, July 30, 2019 - link
ryzen 4000 5GHz yayLordSojar - Tuesday, July 30, 2019 - link
It, unfortunately, doesn't quite work that way. Maybe, yes, but then, maybe not. Gate leakage increases with smaller and smaller pitch sizes. So... It's more about making each core do more, rather than go faster. Faster is good, more efficient at doing the same per cycle is better.boeush - Tuesday, July 30, 2019 - link
There's work around new transistor architectures, to replace finfet while reducing leakage, improving density, lowering voltage/power, and reducing electrostatic lag: GAA, vertical nanowire, 3D-stacked complementary FET... All rumors to the contrary notwithstanding, we're still quite far from hitting the quantum wall, from the manufacturing side of things, in terms of improving processing density and performance. But yes, better processor architectures can be helpful also.FreckledTrout - Tuesday, July 30, 2019 - link
TSMC is being somewhat quiet about it but it's very likely the 5nm node will be some variant of GAA using nanosheets.name99 - Wednesday, July 31, 2019 - link
TSMC 5nm is already locked in, and it is FinFET, not GAA.https://www.tsmc.com/english/dedicatedFoundry/tech...
Threska - Saturday, August 3, 2019 - link
https://spectrum.ieee.org/semiconductors/devices/t...Still rather unproven.
Santoval - Tuesday, July 30, 2019 - link
GAA-FETs will be introduced at the 3/4nm node of the foundries, and possibly Intel's 7nm node.LordSojar - Wednesday, July 31, 2019 - link
Right. Exactly Santoval. It's at this juncture we may really begin to see some decent speed increases, and that's a big maybe. That was why I made the point earlier about increasing efficiency, branching out architecture designs, and making each processor do more per cycle. GAA may allow for 5-7GHz if it's done in the manner they're describing (and not some pseudo-tech/science marketing jargon, which is all that these transistor size measurements have become at this point)Santoval - Tuesday, July 30, 2019 - link
"Making each core do more" in what way exactly? A +7% performance at the same TDP suggests +7% higher clocks at the same TDP, assuming an identical μarch and CPU design. We are talking purely about the performance of the *node* here, so the μarch and the design of the CPU is irrelevant."more efficient at doing the same per cycle is better." Yes, that's swell, but that's just an alternative to the mentioned +7% higher performance of the article. It's an "either or" situation, as always : Either you retain the same TDP and extract 7% higher performance (via 7% higher clocks assuming an identical design) or you retain the same performance and lower your TDP budget by 10% at 7nm and 15% at 5nm.
7% higher clocks of the Ryzen 3000 series means 300 MHz higher base & boost clocks on average. Yes, it is harder to raise clocks with each smaller node due to the reasons you mentioned. However the Ryzen 3000 series was released on TSMC's original high performance 7nm node iteration. There is nothing to suggest that the clocks of the Ryzen 3000 series are the max clocks TSMC can reach at 7nm.
Further optimizing their 7nm node (without increasing its density and thus using smaller features at all, which is important) will allow them to reach 7% faster clocks at the same TDP (at least according to them, I am skeptical until I see products) *or* reducing the node's TDP further, which is just as important. The clocks of their 7nm+ and 6nm node will obviously be lower, due to the higher density of these nodes.
There is obviously a finite limit of ~5GHz single core clocks at a TDP of up to ~100W, and that cannot be normally exceeded due to the collapse of Dennard scaling and the slowing down of Koomey's law. The.. abnormal exception is Intel, since according to leaks their top end Comet Lake CPU will reach a single core boost clock of 5.2 GHz. That's because they have been optimizing their 14nm node since ... 2014, and bizarrely in 2020 they will still be releasing 14nm node based CPUs (after Comet Lake comes Rocket Lake) due to the continuing severe issues of their 10nm+ node.
ZolaIII - Wednesday, July 31, 2019 - link
Actually design of cores and ISA have a lot of to do with performance per W & so does the design choice not to persuit the insane clocks. Uper sustainable leaking limit for FinFET is 1.6~1.7 GHz, the final limit should be 2~2.2 GHz which we still see on power optimised many core systems (server chips). Choosing the HD libs instead HP ones when designing power optimised chip will hurt only 100~200 MHz on performance target while it can cut the size/power consumption by up to 50% which we see in mobile (phone) SoC's. The simple OoO designed core like A73 two instructions wide is still about 3~3.5x the size of an in order A55 while performance benefit is about 1.73~1.8x, as you go wider things only get worse regarding those metrics. Scalable ISA (beyond the 64 bit) regarding front end is a key for future performance benefits, especially for SIMD's & DSP's. Simplicity of ISA is crucial for replicating 64 bit general processing blocks (both integer and FP) & tieing them together to work as one, as waiting for instruction execution is also minimised. It's also easyer in such a case to make a simple predictor to go with micro switch. Leading ISA regarding all mentioned is of course RISC V (simplicity, 128 bit finalised & 256 bit on paper) while no one still didn't consider this approach seriously which I hope will change along with unified SIMD approach for which RISC V also left open doors (considering balanced design).Gondalf - Wednesday, July 31, 2019 - link
Very unlikely AMD will adopt this new process. It need of a new masks set and it is pretty expensive. Reportedly they want 7nm+ instead.Moreover IMO these clock speed increases are likely on low power phone socs, a little tricky on high power SLUs were the huge 7nm leakage destroy any power saving features implemented on processes.
Nearly nothing for too much money in manufacturing
RSAUser - Thursday, August 1, 2019 - link
Not all numbers are equal, Intel 14nm++ 5GHz is probably about 4.4-4.5GHz Ryzen 3000 7nm performance, if not a little lower since it's ~15% IPC gain over Intel's.FreckledTrout - Tuesday, July 30, 2019 - link
If we are taking about AMD moving to TSMC's N7+ for Ryzen 4000 then I don't think boosting to 5Ghz is out of the question in fact it's expected.Dragonstongue - Tuesday, July 30, 2019 - link
depends on how much "dark silicon" they must contend with and EVERYONE as they shrink further and further have to increase more and more (losing ground at they go further into making smaller)still dark silicon will make getting speed and actual performance very small % gains till at "best" Intel when they finally get to "true" 7nm after that it will be more of "how much regression can we handle while getting enough cores/cache to hide the dark silicon"
Nvidia might have pushed the speed way up for G 1xxx / RTX 2xxx however, their seeming "nitrous shot" is not going to be pushing the same frequency speed up as CPU did in years past (simpler design, also much simpler "do not pass go" walls because of such)
will be interesting to see the next 5 odd years as they are fast approaching the end of the silicon line (likely when optical come out and about for me and you, they will do similar "chiplet" so the stuff that not shrink well it at all can be kept in the "old but well known" shrinkage (lol) while the faster but more likely to get "dark silicon" they can only really use "wee bits and pieces"
I suppose, GPU and CPU folks might very well have to do what flash memory makers have done the last decade or what have you, SLC to MLC to TLC to QLC .. CPU/ GPU are more or less at the gap between MLC to TLC (happy spot where endurance and speed are meshing near perfect as is the cost for the capacity per wafer "cut" .. QLC on the other hand is "dark silicon" to keep my explain simple
QLC (much like cpu/gpu die shrink at this point) has very few advantages other than cost to produce (very little difference in cost for me and you) as well due to their "size they need to be" the capacity goes up (though performance drops significantly compared to the cost advantage i.e not much capacity/price advantage to really anyone vs "real world" usage (drop endurance a full 1/2 or more, few % less pricey .. seems more a way to get rid of crap wafers than viable drives (what do I know .. likely them makers not chuck anything in garbage if they find a way to make .01 become 100 ^.^
If we look at GPU .. 300mm/2 of today @ 12nm is something like 1200@ 65mn (something like that) so it seems "on paper" the newest fastest GPU/CPU are "fast" reality says they have just gotten far far better at "hiding deficits" (DDR4 higher bandwidth but more "sluggish" we as users only "see" the image painted, not being painted (i.e they get better at hiding or shifting the "deficit".
I honestly not see AMD really pushing to get 5+Ghz "all cores" as power use rises many times over going from 3-4Ghz, from 4-5 is WAY more power/heat even though was the same "% of increase" it is not a +1 = -1 scale .. +1 on speed might mean +15 power, minus 1 speed might mean save 5% power (they have very odd "sweet spots" though no one is immune from this, not Nvidia, not Intel, not IBM even (hell IBM had 5Ghz all core for a LONG TIME.. but, it cost a bunch of electricity and belch heat like crazy (9900k / Bulldozer / Pentium 965 ^.^
Santoval - Tuesday, July 30, 2019 - link
No it's not. TSMC's 5nm node will be even harder to reach clocks in the 4.8 to 5GHz range. Smaller features = higher leakage = more heat = lower clocks. TSMC's 2nd gen DUV 7nm node is different because apparently it is a highly optimized version of their original HP 7nm without increasing density at all. A Ryzen 9 3900X fabbed on that node could reach up to a single core 4.9 GHz boost clock with it.5 GHz boost clocks might have been possible with GAA-FETs (not in their original iteration, after they were quite optimized), but TSMC is not going to introduce GAA-FETs at 5nm. They will at 3/4nm, because at this scale FinFETs will completely run out of steam.
Santoval - Tuesday, July 30, 2019 - link
edit : Sorry, I thought you were referring to TSMC's 5nm node (too bad there is no edit option). TSMC at 7nm+ might reach higher clocks, but probably not in the 5 GHz range. It will depend on how much clocks they will gain from the EUV layers and how much they will lose from the 18 - 20% higher transistor density (it will be a balance between these two).name99 - Wednesday, July 31, 2019 - link
How come you're such an expert on TSMC 5nm capabilities that have not (as far as I can tell) been published? Where are you getting your "info" from?RSAUser - Thursday, August 1, 2019 - link
Same clock at a lower node would be higher IPC, I don't understand why people care about hitting 5GHz instead of pure performance numbers. 5GHz is a marketing spiel.deil - Wednesday, July 31, 2019 - link
I would opt for Ryzen 8 core with 35 TDPTeckk - Tuesday, July 30, 2019 - link
Is the 5nm process in HVM already? Considering it's on EUV and probably the first to get to that node, why do it silently then?Rudde - Wednesday, July 31, 2019 - link
5nm High performance is not at HVM yet.name99 - Wednesday, July 31, 2019 - link
It's in risk. None of this is silent, TSMC has been very open with the schedules.The schedule is basically identical to 7nm, shifted by two years. Which almost certainly means Apple will be on 5nm with 2020 A14, as the first large volume release.
A13 is likely on this 7nmP. (It's all somewhat unclear, but it seems like Apple is NOT using 7nm+, probably because of concerns that TSMC won't be able to provide the volumes Apple needs with its current amount of EUV equipment.)
AlbertS3 - Wednesday, July 31, 2019 - link
I just don't get it. The engineering is impressive but where is the benefit to the user. CPU technology using silicon hit the wall(s) many years ago and stalled at 4-5ghz. 12nm or 5nm performance is unchanged. 7nm and 5nm may reduce power for mobile devices but no performance gains for those of us with desktops. Intel once promised a 10ghz cpu - now a fairytale. Few single users will benefit from a 16, 32, or 64 core cpus. I see a lot of marketing hype with no real hope for any significant performance breakthroughs until we find a silicon replacement. Once found it may take a decade to reach consumers. Moore's law is long dead. Are we flogging a dead horse?Rudde - Wednesday, July 31, 2019 - link
Wider cores, more cache and better predictors all help single core performance. E.g. Ice lake has similiar single core performance to Whiskey lake, even though Ice lake runs 1GHz slower. Gaming has seen used threads climb towards 16 threads, where as a few years ago 8 threads was the maximum.There is a shift toward accelerators doing the heavy work and cpus being used for shifting data and light processing.
name99 - Wednesday, July 31, 2019 - link
Try looking outside the x86 bubble...Plenty of people ARE finding remarkably interesting ways to keep using more transistors. But those people don't work for INTC or AMD.
ET - Wednesday, July 31, 2019 - link
I wonder if AMD will use it for the next gen APU.ToTTenTranz - Wednesday, July 31, 2019 - link
I'm struggling with the suggestion that N6 will be a "long node", considering it's coming out just months before N5, and N7+ with better performance is reportedly being used for volume production already.I get that we might see slight refreshes of Navi 10 and Zen 2 chiplets, but I doubt very high-volume mobile SoC vendors like Qualcomm and Apple will choose to reuse designs for N6 instead of making something from the ground up for N7+. And for 2021 updates they'll most probably use N5.
Rudde - Wednesday, July 31, 2019 - link
TSMC is trying to get 28nm customers over to N7. Those customers can move to N6 without having to redesign. TSMC expects those customers to stay at N6 for a long time.Gondalf - Wednesday, July 31, 2019 - link
Intel advetrise Ice Lake like plain 10nm, from the official process roadmap 10nm+ will be available only in 2020 with the Willow Cove core. If old data are valid at that point 14nm and 10nm will have the same drive current.This is consistent with some voices about a Sunny Cove/Willow Cove S for desktop in 2H/2020.
But i think the situation is fliud, the only certain thing is about a "silicon back" of Tiger Lake (Willow Cove +Xe) for Laptops.
In 2021 there will be 10nm ++ and first edition of 7(5)nm process.