A hydrogen atom, for example, is about 0.1 nanometers, and a caesium atom is around 0.3nm. The atoms used in silicon chip fabrication are around 0.2nm. So you're going to have gates made up of about <50 atoms soon. That's amazing.
You got that wrong. When examined in depth marketing atoms are found to be far smaller than they initially appeared; however they have huge spin values.
Maybe if instead they cared about hiring the best person for the job 10nm would be out already. Is it really so hard to believe that men and women are attracted to different professions?
Deranged and ignorant SJWs and incompetent MBAs who hire them ruin everything, even the icon of American high tech. The company should fire everybody who is not an engineer or real scientist (physicist or chemist) by training and profession and get back to business.
It must take a pathetic amount of frustration to ignore the simple and well researched fact that diverse teams outperform non-diverse counterparts, especially in tasks which require creative thinking like in high tech R&D as done at intel. But I take from your rather sad comment that you wouldn’t be able to function at such a level. I hope you at least managed to finish high school?!?
Teams with the most talented and capable people regardless of their race or gender perform the best. You clearly have never worked in the industry before.
You should keep in mind while being amazed, which is totally justified, at this that like a previous poster mentioned, actual widths and marketing widths decoupled a few years ago.
Transistors are essentially frozen at 16 to 22nm due to the quantum effects that take precedent at smaller gate widths (which is where finFET and other techs come in by raising in 3d a wider transistor out of a trace), while the traces get smaller they aren't close to the 3nm claimed. IIRC the traces on the current 7nm tech are about 100 silicon atoms wide and each node is about a ~10-20% reduction so this "3nm" is probably around 60-80 atoms wide traces.
Still amazing, but just keep in mind marketing took over this term a few years ago and it became completely unreliable.
It's not true that transistors are frozen, transistor density is increasing rapidly each generation (eg. TSMC 7nm to 5nm is ~1.8x, and 5nm to 3nm is ~1.3x). Here is a good article detailing existing and future processes. As you can see, everything is scaling well, CPP, M2P, tracks and actual transistor density.
In any case the "nm" has had no meaning for at least 10 years and with FinFET it makes no sense at all - but all that matters is that smaller nm means higher density.
Btw a single transistor is effectively 2*CPP by track height/2, so for 7nm that would be 114nm by 120nm. So there is plenty of scope for further scaling.
I never said transistor density isn't increasing, only that the transistor "gap" is pretty much frozen and unable to shrink further due to quantum effects.
Manufacturers worked around this quantum restriction by building 3D transistors that allowed a wider gap on top of smaller traces. FinFET and other 3D transistor technology allows the wider gap to sit on smaller trace which allows transistor density to continue to increase.
>I never said transistor density isn't increasing, only that the transistor "gap" is pretty much frozen and unable to shrink further due to quantum effects
You didn't actually say that, but if you had you would still have been incorrect.
I have no idea what exactly you mean with "gap", but certainly the gaps between transistors and individual fins are still shrinking. The fins have become thinner and taller as well with each generation. There isn't anything at all that is frozen and unable to scale further. Everything scales.
No you will not ("have gates made up of about <50 atoms soon"). Not just because of the usual whining that feature size is "marketing", but because transistors are 3D objects.
Even if the smallest feature of your transistor (eg the width of a fin, which BTW is 7nm for 7nm...) is "process marketing size", the fin still has a height and a length, which boils down to incorporating a whole lot of atoms! And which shows that measuring these things in "atom widths" is meaningless; measure them in terms of something that actually matters.
If you manufacture artificial materials, like the materials used for QCLs, you lay down a one to a few atoms thick layer of atoms of type A, then another of type B, then C, then repeat 20 to 100 times. This can be done! And it works! Yes, the individual structures are one to a few atoms thick --- but they are also mesoscopically wide (ie width is microns to millimeters) so MANY MANY more than just a few atoms are involved, even when you ask about the behavior of just one layer.
So my question is what are all these companies going to do when they reach 1nm nodes and have no where left to go. That day is coming up pretty fast if they are already talking 3nm node.
just to add in here. No wonder Intel has stuck with 14nm+++++++ for so long they finally learned getting to 1nm doe snot make them the winners in this race and there is the fact they are having problems with 10nm....lol
Doe Snot. That has been Intel's problem all along... They aren't using enough Doe Snot.... In their push to shrink the nodes, there isn't sufficient space for the required quantities of Doe Snot.
I still remember a few years ago I posted TSMC 5nm in 2020 on Anandtech Forum and got stabbed front and back. Luckily I got someone with great reputation to back me up.
3nm is looking like 2021, 3nm+ / 2nm in 2022, 2nm / 1nm in 2023, Possibly 1nm in 2024.
Remember all these Node Number are marketing numbers. It is because someone started these number marketing TSMC had no choice but to follow suit. So there could be a few more nodes below 1nm.
As the article have stated, 3nm is in development. I don't even doubt we could reach 2nm and 1nm. The problem isn't even technical, it is the unit economics. Even Apple only ships around 100M leading node SoC per year. Somewhere post 5nm / 3nm the design cost could be a limiting factor.
So we have at least 5 years to go to figure out where we go next, that is from new material or stacked silicon.
"isn't even technical, it is the unit economics" Most things that are "proven to be technically possible" are hindered by absurd economic propositions.
From what I've read on the science of this there is going to be a hard limit on the trace size just like they've already encountered on the transistor size due to the quantum effects at this scale.
To move beyond this limit they will probably have to move away from Silicon or start looking toward moving away from either binary or digital computing to advance. There was a very good recent article on using trenary (or trinary if you prefer) on current microprocessor being a pretty easy thing to adapt current process tech to.
The move from binary to trenary would significantly expand the computer power. Even if this doesn't come to fruition when we hit those quantum limits on process tech, the only way forward will be a completely different path.
There isn't any magic quantum limit we're hitting. And ternary computing is quackery. If you said 1 in 4 hot encoding then that's a possibility, but CMOS transistors only have 2 stable states.
Last I heard (1990s? on comp.arch?), ternary had some advantages in log based computing, which could work wonders on things like GPUs and AI. Don't expect any other big benefits, as all it means is more transistors will be needed (and still leaking, and more transistor states need to change, meaning more power).
Presumably any fab that can make CMOS chips out of MOSFETS could make ternary out of the same, just expect to spend a decade or two characterizing all the effects you didn't *quite* expect.
3nm probably won't be in mobile SoCs until closer to 2023 (maybe 2022) and will likely be the first real gain on 7nm as 5nm is looking fairly modest by comparison. And 3nm GPUs will probably be a couple years after that, 2024 at the earliest. That might be the last full shrink for a little while though.
Ending litho shrinks does not mean density stops increasing! Even with no more litho shrink, there is ample scope for growth via 3D... (stacked N and P transistors, stacked logic, moving some metal layers below logic, ...)
CPUs, SOCs, and GPUs have been limited by local power density for quite some time. Stacked transistors seem to work fine in NAND flash (which doesn't use so much power), but don't count on stacking logic on top of each other.
There have been some [academic] improvements with moving things like initialization circuits to another level, but as local power density limits took over, I don't think there's any point in going to that well.
It may be prudent to remember the decimals when we get to these small sizes. N3 is technically a 3.5nm density scaling target compared to N5 (or 5.2nm). N2 is 2.5nm. N1A is 1.8nm. N1B is 1.2nm. I'm not sure if any foundries are currently even doing theoretical work on sub N1B nodes.
"3nm is looking like 2021, 3nm+ / 2nm in 2022, 2nm / 1nm in 2023, Possibly 1nm in 2024."
Too optimistic. Volume 5nm is 2020, risk 3nm may be 2021, with volume 3nm 2022.
Apple ships about 200M phones a year. About 2/3 of those are leading edge, so that would be about 140M chips. iPad Pro adds something to that. Watch we don't know --- but as of Watch 4 it's the same core, which suggests it's also fabricated on leading edge process, so that probably throws in another 10 million or so. 100M is right order of magnitude, but 150M is probably closer to the actual number.
They'll go to 700pm node give or take. This wasn't a show stopper a few decades ago when the 1 micron threshold was crossed, and won't be one in a few more years.
Um, 1nm is a measurement not some barrier. Nanometers are an arbitrary method of measuring an object. Below 1nm is the Picometer, which would be the method of measuring below nm, assuming we can get that small and that they don't go with decimals instead (0.9nm for instance).
It's already crazy enough that they are blasting tin droplets with high powered lasers to create EUV light. Now nanosheets. Almost certain this will be a Gate-All-Around approach maybee GAAFET? I'm kind of excited about what we can make using propper 3nm via GAAFET or MBCFET the densities will be insane.
That might be the times, when 3nm begin to manufacture, that I will have to sell all semiconductor stocks, this is insanely risky. Whoever uses first can got burnt~!
According to the info on Wikichip website, the Apple A12 chip in 7nm that measure ~84mm2 has nearly ~7 billion transitors.
That is a density > 80million transitors per mm2.
It is said that TSMC 5nm has a transitor density 1.8x compared to 7nm, which would mean that, in theory, it would be possible to make chip in 5nm with > 140 million transitors per mm2.
I would think that we may expect chip in 3nm to have ~ 200 million transistors or more per mm2.
It seems that an Intel Pentium 4 at the beginning from 2000 had roughly 50 million transistors. So in theory you could fit the processing power of 4 pentium 4 processor (from year 2000) in 1mm2 using TSMC 3nm node....
I would also think that we are getting closer to see the first chip with > 100 billion transistor in 2D...
The years between 2020 and 2025 looks very exciting in terms of reaching some significant milestones...
They are at least 1-2 years behind TSMC now, and 10nm still isn't fully working given it can only do low-end mobile chips. When you can buy 10nm 5GHz 100W desktop cores (maybe late 2020 or 2021?) you can say it finally matched 7nm TSMC.
I think from Intel's perspective having TSMC as a consultant for a serious fee, and possibly a % of every chip sold that is using TSMC's technology . Is pretty good business for TSMC. I guess INTEL would have to do the numbers. And a real gut check about where they actually are in their deployment of 10nm.
Is it safe to say Intel is well and truly left behind by TSMC now? What sort of timeframe is this, will it be up against Intel "7nm" ? Does anyone have any insight in technology leadership of TSMC Vs Intel's fabs. Thanks
I would say that TSMC plan to be in High Volume Manufacturing (HVM) of their 5nm node that will extensively use EUV up to 14 layers in H1 2020, and so it should be possible to purchase devices (iPhones) with a TSMC 5nm EUV chip in H2 2020.
Intel plan to introduce their 7nm EUV node only in 2021, and I would think that you would be able to get your hands on a device with an Intel 7nm EUV chip in H2 2021 at best (in reality, it might even be later than that like 2022 if Intel has the same kind of struggle as for their 10nm process...).
So yes, in H2 2020, I would consider that TSMC would have at least 12 months over Intel, because devices with TSMC chip using using extensively the most advanced EUV manufacturing will be on the market while Intel wouldn’t have even start their HVM manufacturing (it takes approx. 6 months to have the 1st devices on the market after that).
At some point the fixed cost of smaller nodes will be swamped, so to speak, by the lack of demand for such density. The only way to defray fixed cost (drive down average cost, which is all the bean counters care about) is to spit out ever more widgets. Where is it going to come from?
Years ago, AMD said that 14nm would cost more per transistor than 22nm. That’s getting worse with each succeeding generation. Even TSMC recently said that going to 5nm wouldn’t make much gain in efficiency and performance.
I’ve felt that more performance could be wrung out from each node if they stayed on it for a longer time. It would also allow them to better prepare the succeeding node. But marketing doesn’t want that. Advertising a new node seems better.
This is what has gotten Intel into such a bind. Their 14nm is better than it was, and their attempt at 10nm was much more ambitious than anyone else, and it set them back. But not really. It’s popular to think. But 10nm is coming on line, considered about as good as other 7nm l8nes. If they get 7nm on line on time, they’ll be crack in the leading edge Frey, even with 5nm moving in before.
In the first place, transistors are still cheaper every generation, at least for foundries. In the second place Intel's problem is more or less the precise opposite from what you say. Intel bet on GHz not on density. They optimized their designs for GHz, and their process for GHz. But GHz ain't going anywhere -- the best you get is a few hundred MHz over five years or so.
Apple (and ARM, and maybe AMD -- I can't tell how they think) bet on density -- on designs that run ever faster because they use ever more transistors, not because the transistors are clocked that much faster. With Apple it's really obvious: A12 is about 4x speed of A7, and is just under 2x the GHz --- even split between smarter design (lots! of transistors) and higher speed transistors.
Intel's path is a dead end. Half the company is designing for GHz, while the other half is creating processes optimized for density! And then, big surprise, it all falls apart when you try to manufacture the GHz-optimized design on the density optimized process?!?
And they STILL haven't got their act together! Look at their marketing! Same thing. When they advertise CPUs, it's all about "we has top GHz", then when they boast about their new processes, it's all about how the density is even higher. WTF guys, WTF???
It's great that we can have dream machines at ridiculously low prices, but these machines are valuable enough that we'd buy them at 2x or 3x the price, easily. There'll be a whole lot of grumbling and complaining, as always. But people have grumbled and complain since the iPhone 1 and every year there after --- and they've been MASSIVELY wrong about the value of these devices compared to their costs, and so, just how desirable they are.
At the end of the day, are you not willing to pay $5K extra from a car that's REALLY self-driving and ultra-safe? Would you not pay $3K for something like your phone, only with enough performance to translate any text or words you hear, and to behave as intelligently as a human secretary?
iPhone sales have gone flat, not sure people would pay much more for one without a lot more people NOT doing so... my 2+ year old S7 works fine, no way in hell I'm paying $1K for a phone, let alone $3K. https://www.statista.com/chart/12781/iphone-unit-s...
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webdoctors - Tuesday, July 23, 2019 - link
This is crazy news. Just as an FYI:A hydrogen atom, for example, is about 0.1 nanometers, and a caesium atom is around 0.3nm. The atoms used in silicon chip fabrication are around 0.2nm. So you're going to have gates made up of about <50 atoms soon. That's amazing.
A5 - Tuesday, July 23, 2019 - link
IIRC, the "marketing node" has been decoupled from the actual smallest feature size for several years now. Still impressive, though.Sivar - Tuesday, July 23, 2019 - link
Marketing atoms appear tiny at first glance, but show themselves to be much larger on average upon analysis of any depth.DanNeely - Tuesday, July 23, 2019 - link
You got that wrong. When examined in depth marketing atoms are found to be far smaller than they initially appeared; however they have huge spin values.0razor1 - Wednesday, July 24, 2019 - link
Oh, I signed in after ages to tip my hat to you, sir.SSTANIC - Wednesday, July 24, 2019 - link
Poetry in a standing wave :)PixyMisa - Wednesday, July 24, 2019 - link
Plus plus.spkay31 - Wednesday, July 24, 2019 - link
You get the "Walter Brattain and John Bardeen" award for humor in solid state physics! (Also know as the Schockley was an a-hole award.)gfkBill - Friday, July 26, 2019 - link
Where do I up-vote? Nailed it.Dragonstongue - Tuesday, July 23, 2019 - link
LMFAOI am pretty sure all lawyers, analyst and most politicians (most anyone when you go beyond making X per annum) causes that switch to flip :D
chrysrobyn - Wednesday, July 24, 2019 - link
For non-Intel, that number has largely followed the width of the fin. Except for GF's "12" node, which is just a 14 with enhancements.peevee - Wednesday, July 24, 2019 - link
In connected news, Intel reports new successes in their Divercity and Inclusion program.https://www.intel.com/content/www/us/en/diversity/...
Thunder 57 - Wednesday, July 24, 2019 - link
Maybe if instead they cared about hiring the best person for the job 10nm would be out already. Is it really so hard to believe that men and women are attracted to different professions?peevee - Thursday, July 25, 2019 - link
Deranged and ignorant SJWs and incompetent MBAs who hire them ruin everything, even the icon of American high tech. The company should fire everybody who is not an engineer or real scientist (physicist or chemist) by training and profession and get back to business.I am afraid it is too late now...
jospoortvliet - Friday, July 26, 2019 - link
It must take a pathetic amount of frustration to ignore the simple and well researched fact that diverse teams outperform non-diverse counterparts, especially in tasks which require creative thinking like in high tech R&D as done at intel. But I take from your rather sad comment that you wouldn’t be able to function at such a level. I hope you at least managed to finish high school?!?Jumangi - Saturday, July 27, 2019 - link
Teams with the most talented and capable people regardless of their race or gender perform the best. You clearly have never worked in the industry before.nivedita - Saturday, July 27, 2019 - link
You, on the other hand, have clearly never worked anywhere before.69369369 - Sunday, July 28, 2019 - link
^...
HAHAHAHAHAHAHA
ianmills - Monday, July 29, 2019 - link
Interesting that this is the path the Chinese government is taking. As long as you move to China you will be okrahvin - Tuesday, July 23, 2019 - link
You should keep in mind while being amazed, which is totally justified, at this that like a previous poster mentioned, actual widths and marketing widths decoupled a few years ago.Transistors are essentially frozen at 16 to 22nm due to the quantum effects that take precedent at smaller gate widths (which is where finFET and other techs come in by raising in 3d a wider transistor out of a trace), while the traces get smaller they aren't close to the 3nm claimed. IIRC the traces on the current 7nm tech are about 100 silicon atoms wide and each node is about a ~10-20% reduction so this "3nm" is probably around 60-80 atoms wide traces.
Still amazing, but just keep in mind marketing took over this term a few years ago and it became completely unreliable.
Wilco1 - Tuesday, July 23, 2019 - link
It's not true that transistors are frozen, transistor density is increasing rapidly each generation (eg. TSMC 7nm to 5nm is ~1.8x, and 5nm to 3nm is ~1.3x). Here is a good article detailing existing and future processes. As you can see, everything is scaling well, CPP, M2P, tracks and actual transistor density.https://semiwiki.com/semiconductor-manufacturers/i...
In any case the "nm" has had no meaning for at least 10 years and with FinFET it makes no sense at all - but all that matters is that smaller nm means higher density.
Wilco1 - Tuesday, July 23, 2019 - link
Btw a single transistor is effectively 2*CPP by track height/2, so for 7nm that would be 114nm by 120nm. So there is plenty of scope for further scaling.rahvin - Tuesday, July 23, 2019 - link
I never said transistor density isn't increasing, only that the transistor "gap" is pretty much frozen and unable to shrink further due to quantum effects.Manufacturers worked around this quantum restriction by building 3D transistors that allowed a wider gap on top of smaller traces. FinFET and other 3D transistor technology allows the wider gap to sit on smaller trace which allows transistor density to continue to increase.
saratoga4 - Tuesday, July 23, 2019 - link
>I never said transistor density isn't increasing, only that the transistor "gap" is pretty much frozen and unable to shrink further due to quantum effectsYou didn't actually say that, but if you had you would still have been incorrect.
Wilco1 - Tuesday, July 23, 2019 - link
I have no idea what exactly you mean with "gap", but certainly the gaps between transistors and individual fins are still shrinking. The fins have become thinner and taller as well with each generation. There isn't anything at all that is frozen and unable to scale further. Everything scales.Smell This - Wednesday, July 24, 2019 - link
If I recall, Kaby 14nm (++?) scaled "backwards" ~~ and it is likely that 'short-cell' transistor libraries pooched Chipzillah's 10nm . . .
Wilco1 - Wednesday, July 24, 2019 - link
Yes Intel's ++ processes typically have worse density unlike the rest of the industry.buxe2quec - Wednesday, July 24, 2019 - link
So what is that value referring to? any link explaining maybe graphically?Smell This - Thursday, July 25, 2019 - link
See if this works for you ...https://fuse.wikichip.org/news/2004/iedm-2018-inte...
name99 - Wednesday, July 24, 2019 - link
No you will not ("have gates made up of about <50 atoms soon"). Not just because of the usual whining that feature size is "marketing", but because transistors are 3D objects.Even if the smallest feature of your transistor (eg the width of a fin, which BTW is 7nm for 7nm...) is "process marketing size", the fin still has a height and a length, which boils down to incorporating a whole lot of atoms! And which shows that measuring these things in "atom widths" is meaningless; measure them in terms of something that actually matters.
If you manufacture artificial materials, like the materials used for QCLs, you lay down a one to a few atoms thick layer of atoms of type A, then another of type B, then C, then repeat 20 to 100 times. This can be done! And it works! Yes, the individual structures are one to a few atoms thick --- but they are also mesoscopically wide (ie width is microns to millimeters) so MANY MANY more than just a few atoms are involved, even when you ask about the behavior of just one layer.
rocky12345 - Tuesday, July 23, 2019 - link
So my question is what are all these companies going to do when they reach 1nm nodes and have no where left to go. That day is coming up pretty fast if they are already talking 3nm node.rocky12345 - Tuesday, July 23, 2019 - link
just to add in here. No wonder Intel has stuck with 14nm+++++++ for so long they finally learned getting to 1nm doe snot make them the winners in this race and there is the fact they are having problems with 10nm....lolrocky12345 - Tuesday, July 23, 2019 - link
Did not mean to type doe snot supposed to be ""does not"".HardwareDufus - Tuesday, July 23, 2019 - link
Doe Snot. That has been Intel's problem all along... They aren't using enough Doe Snot.... In their push to shrink the nodes, there isn't sufficient space for the required quantities of Doe Snot.HardwareDufus - Tuesday, July 23, 2019 - link
Buck Snot was disqualified from most processes around the 28nm node shrinks.drexnx - Tuesday, July 23, 2019 - link
right, that's what PDSOI stood for, Partially Doe Snot On Insulator,too bad FDSOI (Fawn & Doe Snot On Insulator) never got any traction
Ashinjuka - Tuesday, July 23, 2019 - link
OMG i am dying this is the best, simplest, funniest typo in this contextksec - Tuesday, July 23, 2019 - link
I still remember a few years ago I posted TSMC 5nm in 2020 on Anandtech Forum and got stabbed front and back. Luckily I got someone with great reputation to back me up.3nm is looking like 2021, 3nm+ / 2nm in 2022, 2nm / 1nm in 2023, Possibly 1nm in 2024.
Remember all these Node Number are marketing numbers. It is because someone started these number marketing TSMC had no choice but to follow suit. So there could be a few more nodes below 1nm.
As the article have stated, 3nm is in development. I don't even doubt we could reach 2nm and 1nm. The problem isn't even technical, it is the unit economics. Even Apple only ships around 100M leading node SoC per year. Somewhere post 5nm / 3nm the design cost could be a limiting factor.
So we have at least 5 years to go to figure out where we go next, that is from new material or stacked silicon.
Death666Angel - Tuesday, July 23, 2019 - link
"isn't even technical, it is the unit economics"Most things that are "proven to be technically possible" are hindered by absurd economic propositions.
rahvin - Tuesday, July 23, 2019 - link
From what I've read on the science of this there is going to be a hard limit on the trace size just like they've already encountered on the transistor size due to the quantum effects at this scale.To move beyond this limit they will probably have to move away from Silicon or start looking toward moving away from either binary or digital computing to advance. There was a very good recent article on using trenary (or trinary if you prefer) on current microprocessor being a pretty easy thing to adapt current process tech to.
The move from binary to trenary would significantly expand the computer power. Even if this doesn't come to fruition when we hit those quantum limits on process tech, the only way forward will be a completely different path.
Wilco1 - Wednesday, July 24, 2019 - link
There isn't any magic quantum limit we're hitting. And ternary computing is quackery. If you said 1 in 4 hot encoding then that's a possibility, but CMOS transistors only have 2 stable states.wumpus - Thursday, July 25, 2019 - link
Last I heard (1990s? on comp.arch?), ternary had some advantages in log based computing, which could work wonders on things like GPUs and AI. Don't expect any other big benefits, as all it means is more transistors will be needed (and still leaking, and more transistor states need to change, meaning more power).Presumably any fab that can make CMOS chips out of MOSFETS could make ternary out of the same, just expect to spend a decade or two characterizing all the effects you didn't *quite* expect.
axfelix - Wednesday, July 24, 2019 - link
3nm probably won't be in mobile SoCs until closer to 2023 (maybe 2022) and will likely be the first real gain on 7nm as 5nm is looking fairly modest by comparison. And 3nm GPUs will probably be a couple years after that, 2024 at the earliest. That might be the last full shrink for a little while though.name99 - Wednesday, July 24, 2019 - link
Ending litho shrinks does not mean density stops increasing!Even with no more litho shrink, there is ample scope for growth via 3D...
(stacked N and P transistors, stacked logic, moving some metal layers below logic, ...)
wumpus - Thursday, July 25, 2019 - link
CPUs, SOCs, and GPUs have been limited by local power density for quite some time. Stacked transistors seem to work fine in NAND flash (which doesn't use so much power), but don't count on stacking logic on top of each other.There have been some [academic] improvements with moving things like initialization circuits to another level, but as local power density limits took over, I don't think there's any point in going to that well.
SaturnusDK - Wednesday, July 24, 2019 - link
It may be prudent to remember the decimals when we get to these small sizes. N3 is technically a 3.5nm density scaling target compared to N5 (or 5.2nm). N2 is 2.5nm. N1A is 1.8nm. N1B is 1.2nm.I'm not sure if any foundries are currently even doing theoretical work on sub N1B nodes.
name99 - Wednesday, July 24, 2019 - link
"3nm is looking like 2021, 3nm+ / 2nm in 2022, 2nm / 1nm in 2023, Possibly 1nm in 2024."Too optimistic. Volume 5nm is 2020, risk 3nm may be 2021, with volume 3nm 2022.
Apple ships about 200M phones a year. About 2/3 of those are leading edge, so that would be about 140M chips. iPad Pro adds something to that.
Watch we don't know --- but as of Watch 4 it's the same core, which suggests it's also fabricated on leading edge process, so that probably throws in another 10 million or so.
100M is right order of magnitude, but 150M is probably closer to the actual number.
DanNeely - Tuesday, July 23, 2019 - link
They'll go to 700pm node give or take. This wasn't a show stopper a few decades ago when the 1 micron threshold was crossed, and won't be one in a few more years.azfacea - Tuesday, July 23, 2019 - link
WoW is the answerReflex - Tuesday, July 23, 2019 - link
Um, 1nm is a measurement not some barrier. Nanometers are an arbitrary method of measuring an object. Below 1nm is the Picometer, which would be the method of measuring below nm, assuming we can get that small and that they don't go with decimals instead (0.9nm for instance).29a - Wednesday, July 24, 2019 - link
Nano is not where the metric system ends.FreckledTrout - Tuesday, July 23, 2019 - link
It's already crazy enough that they are blasting tin droplets with high powered lasers to create EUV light. Now nanosheets. Almost certain this will be a Gate-All-Around approach maybee GAAFET? I'm kind of excited about what we can make using propper 3nm via GAAFET or MBCFET the densities will be insane.stephenho - Tuesday, July 23, 2019 - link
That might be the times, when 3nm begin to manufacture, that I will have to sell all semiconductor stocks, this is insanely risky. Whoever uses first can got burnt~!FreckledTrout - Thursday, July 25, 2019 - link
The risk is already there look at Intel's 10nm.III-V - Wednesday, July 24, 2019 - link
They're and blasting those droplets 10s of thousands of times per second. It's ridiculousIII-V - Wednesday, July 24, 2019 - link
Launching and blasting *Diogene7 - Thursday, July 25, 2019 - link
According to the info on Wikichip website, the Apple A12 chip in 7nm that measure ~84mm2 has nearly ~7 billion transitors.That is a density > 80million transitors per mm2.
It is said that TSMC 5nm has a transitor density 1.8x compared to 7nm, which would mean that, in theory, it would be possible to make chip in 5nm with > 140 million transitors per mm2.
I would think that we may expect chip in 3nm to have ~ 200 million transistors or more per mm2.
It seems that an Intel Pentium 4 at the beginning from 2000 had roughly 50 million transistors. So in theory you could fit the processing power of 4 pentium 4 processor (from year 2000) in 1mm2 using TSMC 3nm node....
I would also think that we are getting closer to see the first chip with > 100 billion transistor in 2D...
The years between 2020 and 2025 looks very exciting in terms of reaching some significant milestones...
Vitor - Tuesday, July 23, 2019 - link
Those next 5 years won't be very comfortable for Intel. The ultra dominance is over.Sychonut - Tuesday, July 23, 2019 - link
Cool. Looking forward to Intel's 14+++++.nunya112 - Wednesday, July 24, 2019 - link
I think Intel will have to pay TSMC to use its IP and manufacturing Copyright in order to advance and to learn how to get past 14nm+RSAUser - Wednesday, July 24, 2019 - link
I doubt it. Their 10nm should be doing a lot better very soon, matches 7nm TSMC, and they definitely have the money to throw at it.Wilco1 - Wednesday, July 24, 2019 - link
They are at least 1-2 years behind TSMC now, and 10nm still isn't fully working given it can only do low-end mobile chips. When you can buy 10nm 5GHz 100W desktop cores (maybe late 2020 or 2021?) you can say it finally matched 7nm TSMC.nunya112 - Wednesday, July 24, 2019 - link
I think from Intel's perspective having TSMC as a consultant for a serious fee, and possibly a % of every chip sold that is using TSMC's technology . Is pretty good business for TSMC. I guess INTEL would have to do the numbers. And a real gut check about where they actually are in their deployment of 10nm.29a - Wednesday, July 24, 2019 - link
Yes, their 10nm has been doing better very soon for a few years now.AshlayW - Wednesday, July 24, 2019 - link
Is it safe to say Intel is well and truly left behind by TSMC now? What sort of timeframe is this, will it be up against Intel "7nm" ? Does anyone have any insight in technology leadership of TSMC Vs Intel's fabs. Thanksshabby - Wednesday, July 24, 2019 - link
According to intel only 10nm is behind, 7nm is still on schedule 😂peevee - Thursday, July 25, 2019 - link
According to Intel's SJWs, 7nm is racist.Diogene7 - Friday, October 18, 2019 - link
I would say that TSMC plan to be in High Volume Manufacturing (HVM) of their 5nm node that will extensively use EUV up to 14 layers in H1 2020, and so it should be possible to purchase devices (iPhones) with a TSMC 5nm EUV chip in H2 2020.Intel plan to introduce their 7nm EUV node only in 2021, and I would think that you would be able to get your hands on a device with an Intel 7nm EUV chip in H2 2021 at best (in reality, it might even be later than that like 2022 if Intel has the same kind of struggle as for their 10nm process...).
So yes, in H2 2020, I would consider that TSMC would have at least 12 months over Intel, because devices with TSMC chip using using extensively the most advanced EUV manufacturing will be on the market while Intel wouldn’t have even start their HVM manufacturing (it takes approx. 6 months to have the 1st devices on the market after that).
melgross - Wednesday, July 24, 2019 - link
“The specification is under development and the company is confident it would meet requirements of its leading partnering customer.”Hmm, I wonder who that could be?
FunBunny2 - Wednesday, July 24, 2019 - link
At some point the fixed cost of smaller nodes will be swamped, so to speak, by the lack of demand for such density. The only way to defray fixed cost (drive down average cost, which is all the bean counters care about) is to spit out ever more widgets. Where is it going to come from?melgross - Wednesday, July 24, 2019 - link
Years ago, AMD said that 14nm would cost more per transistor than 22nm. That’s getting worse with each succeeding generation. Even TSMC recently said that going to 5nm wouldn’t make much gain in efficiency and performance.I’ve felt that more performance could be wrung out from each node if they stayed on it for a longer time. It would also allow them to better prepare the succeeding node. But marketing doesn’t want that. Advertising a new node seems better.
This is what has gotten Intel into such a bind. Their 14nm is better than it was, and their attempt at 10nm was much more ambitious than anyone else, and it set them back. But not really. It’s popular to think. But 10nm is coming on line, considered about as good as other 7nm l8nes. If they get 7nm on line on time, they’ll be crack in the leading edge Frey, even with 5nm moving in before.
name99 - Wednesday, July 24, 2019 - link
No, that's NOT what has got Intel into a bind.In the first place, transistors are still cheaper every generation, at least for foundries.
In the second place Intel's problem is more or less the precise opposite from what you say. Intel bet on GHz not on density. They optimized their designs for GHz, and their process for GHz. But GHz ain't going anywhere -- the best you get is a few hundred MHz over five years or so.
Apple (and ARM, and maybe AMD -- I can't tell how they think) bet on density -- on designs that run ever faster because they use ever more transistors, not because the transistors are clocked that much faster. With Apple it's really obvious: A12 is about 4x speed of A7, and is just under 2x the GHz --- even split between smarter design (lots! of transistors) and higher speed transistors.
Intel's path is a dead end. Half the company is designing for GHz, while the other half is creating processes optimized for density! And then, big surprise, it all falls apart when you try to manufacture the GHz-optimized design on the density optimized process?!?
And they STILL haven't got their act together! Look at their marketing! Same thing. When they advertise CPUs, it's all about "we has top GHz", then when they boast about their new processes, it's all about how the density is even higher. WTF guys, WTF???
melgross - Thursday, July 25, 2019 - link
What? Are you living in the past?name99 - Wednesday, July 24, 2019 - link
One day, maybe, but not soon.It's great that we can have dream machines at ridiculously low prices, but these machines are valuable enough that we'd buy them at 2x or 3x the price, easily. There'll be a whole lot of grumbling and complaining, as always. But people have grumbled and complain since the iPhone 1 and every year there after --- and they've been MASSIVELY wrong about the value of these devices compared to their costs, and so, just how desirable they are.
At the end of the day, are you not willing to pay $5K extra from a car that's REALLY self-driving and ultra-safe? Would you not pay $3K for something like your phone, only with enough performance to translate any text or words you hear, and to behave as intelligently as a human secretary?
gfkBill - Friday, July 26, 2019 - link
iPhone sales have gone flat, not sure people would pay much more for one without a lot more people NOT doing so... my 2+ year old S7 works fine, no way in hell I'm paying $1K for a phone, let alone $3K.https://www.statista.com/chart/12781/iphone-unit-s...