This is a marketing release - since they are not revealing the 2 painfully obvious points of improvement - what is the minimum fin pitch and is EUV inserted at MOL or only BEOL? The improvement in the process is re-assuring and TSMC does have a good track record of executing on its timelines. Lets see where this goes.
You simply don't understand the foundry business model!
TSMC does not sell one leading edge process and done! They sell a variety of processes, and part of the sale includes continual upgrades of the non-leading edge processes, so that even if you don't have the budget to fully redesign and run a new mask set for the newest process, you may be able to get some improvement (slightly denser, or lower power, or faster) with the much smaller modifications required to move from say 7nm to 7nm+ or 6nm. Just because these sorts of improvements (like ongoing improvements at 10 or 16, or even 28nm) are not of interest to, say, Apple, doesn't mean they're of no interest to anyone...
Will this become available before or after TSMC's N7+? The article appears to suggest that N6 will be released after N7+ ("..companies with complex N7-based chips will prefer to go directly to N7+..), however the table listing the various nodes appears to suggest the opposite. In any case, N6 looks like it will be identical to N7+ in transistor density gain, so for all intents and purposes it just might the same node.
This appears to be released over concern about initial usage of N7+. From the wording it seems 7+ chips aren't actually compatible with N7 designs, meaning companies would have to redesign their chips all over again to get relatively little power and density gains, while they wouldn't have to with N6.
No doubt Apple can afford N7+ designs and it'll show up in the next iPhone. N6 is probably meant for AMD and other companies that don't see the benefit to spending hundreds of millions for little improvement. So we might see a Navi refresh, and the PS5, and whatever on N6 next year.
Anton, how does this compare to Intel's 10nm and 7nm? Personally I think TSMC's choice of taking small steps is the right one going forward as the incremental changes are less risky. However there naming schemes of processes seem a bit overly optimistic in fact I would go as far is it's mostly marketing.
It is less risky but you have to realize the inputs to understand the outputs of why TSMC took this strategy and the associated strategy benefits and strategy downsides plus the strategy's credits and the strategy's tax.
TSMC has multiple customers and the first customer for the process (to test the process) are using both smaller chips and "known chips." It is easier to have multiple process running in the company and still be at full capacity and there is cheaper development for you needed to have all these different designs for you are foundry that other people bring their chips to instead of using the foundry for only internal use.
Intel by contrast has a lot less amount of designs in play, various chips for server, desktop, laptop, and mobile / modem (and the mobile / modems are being phased out.) Plus chips that run on older processes. This has its pros and cons for it is easier to tailor the maximum performance for these chips via process changes if you can actually get the process right, but if you have problems getting the process right TSMC choice of many designs and just make sure your fabs are at full capacity makes sense for it is easier to iterate to the next step in the process.
My point here is I think TSMC is doing the smarter thing style of strategy, but there is a reason why Intel is doing the strategies they have been doing, and it is not like overnight Intel could adopt TSMC strategies for the inputs are not there with lots of foundry customers to get the desired output of a specific style of strategy.
It does seem to be coming after 7+, which will be available this year, in 2019. This is intermediate between 7+ and 5. So depending on cost, manufacturers will have a transition point in 2020, before 5 will be available, apparently, if all goes well, in 2021.
After that, who knows? We read about 3nm, but will it really appear? Just a few years ago, most chip experts weren’t sure that 5nm could be achieved. Everyone has gotten over the 14nm hump, including Intel. But will there be a 3nm hump? Will 5nm come out on time? We don’t know the answer to either of those questions yet.
You have to remember that the so called 7nm product is not even near real 7nm size... It is purte marketing. So 3nm could really be 60nm in real size... because the marketing nm and real nm are so far away from each others...
Well, compared to what Intel does, it’s not. But the lines are 7nm, so that’s what we call it. The + labels are to show improvements, such as getting the lines closer together, improvements in sizing transistors, etc.
Intel is denser, but the others are about, depending on methodology and capability, about one node looser, not ten, as you’re saying.
Intel is certainly not denser. When they finally get 10nm out of the door, actual chips will have less than half the density of current 7nm TSMC chips.
The nm number is just a number, however it does represent an ordering between processes, and in that sense the numbers are close to reality.
From the earnings call, there's a little more information on the N6 node, but it's still confusing. It's coming out later than N7+ and its performance and density specs seem to be similar to N7+. TSMC say they expect customers to move from N7 to N6 and not use N7+. And I got the idea there seems to be some disappointment on the characteristics of N7+.
In some ways it seems like a replacement for a disappointing N7+, though I'm not sure if that's accurate or not. It also is going to be coming available around the time N5 is coming available. I am guessing TSMC expect high end smartphones to use N5 and higher-powered leading-edge compute to use N6. One more thing, TSMC said that N6 will use one more layer of EUV than N7+ and they also said something about learning from their N7+ experience when creating N6.
Here is on of the quotes by the CEO from the conference call: "As we continue to improve our 7-nanometer technology and by leveraging the EUV landing form, N7+, we now introduce N6 process. N6 has three major advantage. First, N6 have 100% compatible design rules with N7, which allows customer to directly migrate from N7-based design, which substantially shorten the time-to-market. Second, N6 can deliver 18% higher logical density as compared to N7 and provide customer with a highly competitive performance-to-cost advantage. Third, N6 will offer shortened cycle time and better defect density. Risk production of N6 is scheduled to begin in first quarter year 2020 with volume production starting before the end of 2020."
My guess is the third advantage is the advantage that N6 holds over N7+, regardless of whether a company is using N7 already or not. I am inferring that perhaps N7+ has proved to have long cycle times and/or high defect density. So the cost of N6 should be much less for big power-hungry chips. In other words, big GPUs
A couple more relevant quotes from the CEO on the issue:
"As I said, we have a very high tape-out activity for N7 for this year. Actually, a lot of customer from the [indiscernible], and mostly is from the HPC area, they are all designing their product with N7. A few of them has adopted N7+. But then that’s why we introduced our N6 that can be 100% compatible to the N7. So I’ll give you a taste of that probably starting year 2020. Most of the customer in the N7 will move to N6. And from that beyond probably, the N6 will pick up all the momentum and pick up all the volume production."
So N6 will pick up what would otherwise be N7/N7+ volume in 2021. N7+ will be skipped by all but a few customers. N7 customers will mostly move to N6 rather than N5 in that time frame. So it sounds like TSMC expect N7 in 2019 and 2020 and N6 in 2021, with only a few customers using N7+.
"Right. The question is about N6. It looks like N6 is behind N5 in terms of schedule. So what is the application? Well, again, I want to reiterate that N6 is coming from the N7, N7+ experience, learning. And so the N6, if you – a lot of customers are already entering N7 with a lot of tapeout. So N6 provide them a very good task that they can easily put in their current product into N6. So gain the benefit of either the performance, the tie area and also the shortened cycle time. N5 is a totally new node."
So, it sounds to me like GPUs will use N7 and N6 and not N7+. N6 sounds like a way of reducing the cost of big, complex chips, exactly the thing the GPU manufacturers are looking for, similar to what the 12FFN node seemed to be. So, for example, perhaps NVIDIA will introduce an N7-based GPU in 2020 and then an N6-based GPU in 2021 or 2022.
How much does it cost to make a factory ready to print 7nm chips? How much would it cost to make the factory ready to print the same in 6nm, given that you already did the 7nm? How much cheaper is that compared to going 6nm for the first time?
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MananDedhia - Wednesday, April 17, 2019 - link
This is a marketing release - since they are not revealing the 2 painfully obvious points of improvement - what is the minimum fin pitch and is EUV inserted at MOL or only BEOL? The improvement in the process is re-assuring and TSMC does have a good track record of executing on its timelines. Lets see where this goes.ZolaIII - Wednesday, April 17, 2019 - link
Lol it's a same old 7 nm utilising denser rooting libs.name99 - Thursday, April 18, 2019 - link
How many times do I have to repeat this?You simply don't understand the foundry business model!
TSMC does not sell one leading edge process and done! They sell a variety of processes, and part of the sale includes continual upgrades of the non-leading edge processes, so that even if you don't have the budget to fully redesign and run a new mask set for the newest process, you may be able to get some improvement (slightly denser, or lower power, or faster) with the much smaller modifications required to move from say 7nm to 7nm+ or 6nm.
Just because these sorts of improvements (like ongoing improvements at 10 or 16, or even 28nm) are not of interest to, say, Apple, doesn't mean they're of no interest to anyone...
Santoval - Wednesday, April 17, 2019 - link
Will this become available before or after TSMC's N7+? The article appears to suggest that N6 will be released after N7+ ("..companies with complex N7-based chips will prefer to go directly to N7+..), however the table listing the various nodes appears to suggest the opposite.In any case, N6 looks like it will be identical to N7+ in transistor density gain, so for all intents and purposes it just might the same node.
Santoval - Wednesday, April 17, 2019 - link
edit : I rather meant that "The article appears to suggest that N7+ will be released after N6..."Frenetic Pony - Wednesday, April 17, 2019 - link
This appears to be released over concern about initial usage of N7+. From the wording it seems 7+ chips aren't actually compatible with N7 designs, meaning companies would have to redesign their chips all over again to get relatively little power and density gains, while they wouldn't have to with N6.No doubt Apple can afford N7+ designs and it'll show up in the next iPhone. N6 is probably meant for AMD and other companies that don't see the benefit to spending hundreds of millions for little improvement. So we might see a Navi refresh, and the PS5, and whatever on N6 next year.
brakdoo - Wednesday, April 17, 2019 - link
You're so weird: This is a rebrand of N7+ at lower cost with very little difference. Just watch the earnings call tomorrow...FreckledTrout - Wednesday, April 17, 2019 - link
Anton, how does this compare to Intel's 10nm and 7nm? Personally I think TSMC's choice of taking small steps is the right one going forward as the incremental changes are less risky. However there naming schemes of processes seem a bit overly optimistic in fact I would go as far is it's mostly marketing.peevee - Thursday, April 18, 2019 - link
" Intel's 10nm and 7nm"What Intel's 10nm and 7nm?
Roland00Address - Thursday, April 18, 2019 - link
It is less risky but you have to realize the inputs to understand the outputs of why TSMC took this strategy and the associated strategy benefits and strategy downsides plus the strategy's credits and the strategy's tax.TSMC has multiple customers and the first customer for the process (to test the process) are using both smaller chips and "known chips." It is easier to have multiple process running in the company and still be at full capacity and there is cheaper development for you needed to have all these different designs for you are foundry that other people bring their chips to instead of using the foundry for only internal use.
Intel by contrast has a lot less amount of designs in play, various chips for server, desktop, laptop, and mobile / modem (and the mobile / modems are being phased out.) Plus chips that run on older processes. This has its pros and cons for it is easier to tailor the maximum performance for these chips via process changes if you can actually get the process right, but if you have problems getting the process right TSMC choice of many designs and just make sure your fabs are at full capacity makes sense for it is easier to iterate to the next step in the process.
My point here is I think TSMC is doing the smarter thing style of strategy, but there is a reason why Intel is doing the strategies they have been doing, and it is not like overnight Intel could adopt TSMC strategies for the inputs are not there with lots of foundry customers to get the desired output of a specific style of strategy.
stanleyipkiss - Wednesday, April 17, 2019 - link
This sounds like an nVidia "special node" ... just like the one developed for Turing.melgross - Wednesday, April 17, 2019 - link
It does seem to be coming after 7+, which will be available this year, in 2019. This is intermediate between 7+ and 5. So depending on cost, manufacturers will have a transition point in 2020, before 5 will be available, apparently, if all goes well, in 2021.After that, who knows? We read about 3nm, but will it really appear? Just a few years ago, most chip experts weren’t sure that 5nm could be achieved. Everyone has gotten over the 14nm hump, including Intel. But will there be a 3nm hump? Will 5nm come out on time? We don’t know the answer to either of those questions yet.
haukionkannel - Wednesday, April 17, 2019 - link
You have to remember that the so called 7nm product is not even near real 7nm size... It is purte marketing. So 3nm could really be 60nm in real size... because the marketing nm and real nm are so far away from each others...melgross - Wednesday, April 17, 2019 - link
Well, compared to what Intel does, it’s not. But the lines are 7nm, so that’s what we call it. The + labels are to show improvements, such as getting the lines closer together, improvements in sizing transistors, etc.Intel is denser, but the others are about, depending on methodology and capability, about one node looser, not ten, as you’re saying.
Wilco1 - Thursday, April 18, 2019 - link
Intel is certainly not denser. When they finally get 10nm out of the door, actual chips will have less than half the density of current 7nm TSMC chips.The nm number is just a number, however it does represent an ordering between processes, and in that sense the numbers are close to reality.
melgross - Friday, April 19, 2019 - link
That’s not true, but ok.peevee - Thursday, April 18, 2019 - link
"Just a few years ago, most chip experts weren’t sure that 5nm could be achieved."And it has not been. In reality, they are all more like 40nm+ with thinner wires for lower voltages.
Anymoore - Thursday, April 18, 2019 - link
Same design rules but higher density means it's not the lithography but track height change or diffusion break reduction.melgross - Thursday, April 18, 2019 - link
It doesn’t matter how it’s done. It’s all about minimizing wasted space.peevee - Thursday, April 18, 2019 - link
"Area Reduction:7FF+ vs 7FF ~17%
6FF vs 7FF ~15%"
Do I understand correctly that their "6FF" is actually LESS dense than their own 7FF+?
Yojimbo - Saturday, April 20, 2019 - link
From the earnings call, there's a little more information on the N6 node, but it's still confusing. It's coming out later than N7+ and its performance and density specs seem to be similar to N7+. TSMC say they expect customers to move from N7 to N6 and not use N7+. And I got the idea there seems to be some disappointment on the characteristics of N7+.In some ways it seems like a replacement for a disappointing N7+, though I'm not sure if that's accurate or not. It also is going to be coming available around the time N5 is coming available. I am guessing TSMC expect high end smartphones to use N5 and higher-powered leading-edge compute to use N6. One more thing, TSMC said that N6 will use one more layer of EUV than N7+ and they also said something about learning from their N7+ experience when creating N6.
Here is on of the quotes by the CEO from the conference call:
"As we continue to improve our 7-nanometer technology and by leveraging the EUV landing form, N7+, we now introduce N6 process. N6 has three major advantage. First, N6 have 100% compatible design rules with N7, which allows customer to directly migrate from N7-based design, which substantially shorten the time-to-market. Second, N6 can deliver 18% higher logical density as compared to N7 and provide customer with a highly competitive performance-to-cost advantage. Third, N6 will offer shortened cycle time and better defect density. Risk production of N6 is scheduled to begin in first quarter year 2020 with volume production starting before the end of 2020."
My guess is the third advantage is the advantage that N6 holds over N7+, regardless of whether a company is using N7 already or not. I am inferring that perhaps N7+ has proved to have long cycle times and/or high defect density. So the cost of N6 should be much less for big power-hungry chips. In other words, big GPUs
A couple more relevant quotes from the CEO on the issue:
"As I said, we have a very high tape-out activity for N7 for this year. Actually, a lot of customer from the [indiscernible], and mostly is from the HPC area, they are all designing their product with N7. A few of them has adopted N7+. But then that’s why we introduced our N6 that can be 100% compatible to the N7. So I’ll give you a taste of that probably starting year 2020. Most of the customer in the N7 will move to N6. And from that beyond probably, the N6 will pick up all the momentum and pick up all the volume production."
So N6 will pick up what would otherwise be N7/N7+ volume in 2021. N7+ will be skipped by all but a few customers. N7 customers will mostly move to N6 rather than N5 in that time frame. So it sounds like TSMC expect N7 in 2019 and 2020 and N6 in 2021, with only a few customers using N7+.
"Right. The question is about N6. It looks like N6 is behind N5 in terms of schedule. So what is the application? Well, again, I want to reiterate that N6 is coming from the N7, N7+ experience, learning. And so the N6, if you – a lot of customers are already entering N7 with a lot of tapeout. So N6 provide them a very good task that they can easily put in their current product into N6. So gain the benefit of either the performance, the tie area and also the shortened cycle time. N5 is a totally new node."
Yojimbo - Saturday, April 20, 2019 - link
So, it sounds to me like GPUs will use N7 and N6 and not N7+. N6 sounds like a way of reducing the cost of big, complex chips, exactly the thing the GPU manufacturers are looking for, similar to what the 12FFN node seemed to be. So, for example, perhaps NVIDIA will introduce an N7-based GPU in 2020 and then an N6-based GPU in 2021 or 2022.Adonisds - Sunday, October 27, 2019 - link
How much does it cost to make a factory ready to print 7nm chips? How much would it cost to make the factory ready to print the same in 6nm, given that you already did the 7nm? How much cheaper is that compared to going 6nm for the first time?