Get 4 Xeon Platinum 8180 's & if that isn't good enough get yourself 8 volta's. Still no ? Cloud But will all due respect, I doubt you make stuff an 8way volta can't handle in a decent amount of time.
Or simply get a Ryzen Threadripper, does the job for any professional content creator, be it games developers, movie cinematics creators, and all heavy-graphics rendering jobs out there. I guess this year's new gen will go up to 48/64 cores, 7nm technology.. will be a perfect beast for sure but also on the professional end of pricing, meaning it will most probably cost around 2000$.
8 (really equivalent to ~12 in as SMT adds ~50% load from each core) is WAY more than enough for 128-bit DRAM bus and caches way less than working sets of any reasonably performance-affected programs. Threadripper has 256 and EPIC has 512 for a good reason.
For many heavy usage you don't really need quad channel or extra pci-e lanes, more cores on mainstream totally makes sense. If you need extra features you go threadripper.
@Flunk: Yes, an 8 core simply can't handle all that self importance...
The problem here is not that 8 cores is not enough, it's that you stumbled onto an article about a product that's not for you, that you don't understand, that doesn't address the needs of a small niche you consider yourself to be in, and you were just confused and decided to post. Cool, it can happen to anyone... if they really don't even try to make an intellectual effort.
The vast majority users don't need more than this and the revenue doesn't come from the self-proclaimed ultra-professional who needs 10000 cores to make his comments look more weighty. An 8 physical cores CPU covers basically the entirety of the market with a few niches to be covered by more specialized parts, with a number of cores even in the 3 digits.
When people say something is enough they don't intend the statement to cover exactly 100% of the use cases in the world for eternity (like the parrot above also seems to think). Otherwise every car would be strapped to to a Saturn V because a handful of dudes really needed to go to the Moon once. And you'd have at least 2TB of RAM and 1024 cores because that's what I have in some machines.
So I'll ask you one question and if the answer is *anything* but a single number then you already proved yourself wrong and no amount of CPU cores will fix it for you: what is enough? ;)
Fighting about core count or who can get all the GHz is like fighting about cars. 1000hp would be great but I'm willing to bet that's less than 0.1% of the population is ever going to need it. The ones that do use 1000hp is another 0.1% of the population that actually races. Most dual cores out now are still fine for daily tasks. Why bother the general population with spending more money for that 0.1% of the time?
for games 6 is already a better choice. Dual core games are already in minority, most use 4 cores/threads. if you add OS (so game can get 100% from CPU) you need 4/8 at minimum with favor of 6/6 or 6/12. YES, we all benefit from 6/12 becoming mainstream.
Well... Guess the parrot got @Flunk's tongue. When asked how many cores is enough as a followup to his whines that 8 is not enough, Flunk went dark. Probably needs more cores to be able to answer.
Of course and if everyone followed this mentality application developers would still be working around a 256 KB memory space limit.
The fact of the matter is anything over 8 cores is nice to have and will push developers to use that additional power. As has happened many times in the past, it will be put to use. If AMD come out with a $400 16 core who in their right mind wouldn't want that? That's a hell of a lot better then 2 years ago when in order to play game you had to close everything just to get max FPS because Intel has been cucking the PC gaming community for a decade.
No, I think I'll always prefer progress over stagnation.
Read a paper a while ago, had to do with threads that a developer can actually use. Think it ended up that at about 500-600 threads, we get to the point where we can't feasibly optimize it anymore, outside of certain scientific workloads. Mostly has to do with a concurrency problem, current design is to use one main thread to manage all the other threads/work as a handover, e.g. login can be highly parallel, but still needs an entry point, that thread has to still pass on the request, and logins are an easy task to parallelize, there are a lot of things where that's not possible.
That said, more than 8 cores is fine, for most game devs, if you can get past 4 cores, making it split among 16 is just as easy as 8, well actually from 16 -> 32 due to SMT.
That said, for my personal use, I often render stuff, do a lot of code compiling that would save me substantial amounts of time. Went from a 4790 to a 2700X was about a 60% reduction in time due to the higher amount of threads.
It sounds like everybody assumes that nobody else needs it. I'm really looking for a combo of single threaded speed and many cores.
For audio recording tasks, you're fight against audio dropouts on the single threaded speed. It sucks re-recording a six minute segment five times in a row. For playback with multiple VSTs you're fighting a combo of single and multiple core usage.
No it's Not... I am an Architect and a CG artist... World is a big place and PC's are meant for more than just gaming... In the Arch Viz/ Film Industry/ Render farms/, more the number of cores, Better it is... So I say let them keep innovating, more is always better, There is a huge market for such things and huge render farms that can take advantage of this amazing core count and a well positioned price to performance ratio...
And if more cores don't start finding their way onto people's desktops, it will be enough forever - because the time investment required by software developers to make use of lots of cores won't happen if the users won't actually benefit from it.
I think what he/she meant was 8 cores should be more than enough for most people and most work loads they would be doing. For power users and those that run VM's yes they would like to see as many cores as possible because they probably can put more cores to use. For my own needs 8-12 cores is about right for what I do on a computer. Now if I can pick up a 16/32 CPU at a decent price of coarse I am gonna go for that even though the CPU probably will never get used to it's max.
If things go as I think they will I am sure AMD will be releasing a 16/32 CPU on the main stream desktop in 2019 more so if Intel's next CPU's have higher than 8 core counts for the main stream desktop. I personally think the CPU Lisa Su was holding up was a Ryzen 5 CPU and we will most likely have 12/24 Ryzen 7 CPU's in the spring of 2019 & maybe 16/32 Ryzen 9's as well. You can clearly see from the picture of the CPU there are traces where the next CPU die will go so I am sure they have plans of releasing something much better than what they have shown at CES.
8 cores is perfect today. It is the sweet spot. It is better than having 16 cores performing worse per core, which is the inevitable result of such a design. In a couple of years, 16 cores will be the sweet spot, but not before.
It depends on the workload, but not really. The only reason why you don't see a big difference from it in gaming, etc., now is that consoles don't have massive numbers of cores yet, and most games are written for the lowest-common-denominator in that regard.
With frequency scaling starting to hit a wall, the only way to increase power going forward is to increase core counts, and games will have to react to that. Eventually increasing the number of cores you have will probably be the standard way to increase game performance.
Most game engines today are still primarily single-threaded, with individual tasks - such as rendering, physics, audio - being given their own separate thread. It works, but it doesn't really scale.
There are also ways to build a fully-multithreaded game engine, but it's just not necessary/worth it - yet. When we have say, 32 cores in a game console, it will start to become unavoidable. Carmack also did a talk on basically how to do it at QuakeCon in 2013.
What it boils down to in a basic form is that, to implement lock-free multithreading, additional memory needs to be used to duplicate some of the data, and there is some efficiency loss in the duplication of some calculations. Once that up-front penalty is paid however, then performance can potentially scale almost infinitely with core count. It's questionable whether or not it's worth it to take that approach at lower core counts. But it almost certainly will be when the target hardware has llarge numbers of cores.
Yes... you have to wank on *all* of the internet's porn videos at once and that requires some serious processing power. Like... at least 9 cores. :)
Other similar issues; - Wallets are never big enough to accommodate the 2cuft of "spare change" $100 bills most people walk around with - Condoms don't come in the 2by4 size most guys require
Really? I run multiple server VMs plus whatever else is running locally with FOUR cores on my laptop, and it all runs just fine. Definitely not a peasant level function. I am SURE there are workloads that can use 16 or even 32 cores - but for Pete's sake, this is a CONSUMER processor. Not a HEDT part. 8 cores is massive overkill for the 90% of computer owners who read email and play Facebook games all day. Hmm, 90%? I'll bet it's even a higher percentage, and the percentage that actually do something that needs 8, let alone more, is WAY less than 10%. DESKTOP, not servers. You want more than 8, get a Threadripper, why complain that this one is "useless' or inadequate? You people make no sense..
So you want the product segmentation/stagnation? I am sure AMD will release a hex core to address the lower end market.
Why get a quad core if you can get a hex core for the same price with a higher performance? Your argument is dumb, software is designed around the current capabilities, if those capabilities increase, software developers will write applications that can take advantage of it.
For me personally 6-8 Cores (12 threads for my 8700k) combined with a really high CPU-frequency is the optimal combination. I use it mainly for DAW (music production). With loads of DSP going on with software synthesizers, digital effects and so on at the same time and in real time (not rendering) where low latency is key, CPU-power is extremely important. And the number of cores counts too, but not at the cost of CPU-frequency, since too low speed per core will cause spikes because a number of synths/effects will be running on the same core and if you add a heavy instrument (cpu wize) it will cause glitches/crackles if there isn't enough headroom for every core. Another thing is that AMD Ryzen is out of the picture for low latency work. Yes, they may work at high latencies for mastering engineers, where things aren't processed in real-time "at the fly", but not for recording/production. As it is now, it seems like an 8 core Intel Part like the 9900K is where core count meets high frequency. But if they could go up to 16 cores at the same speed, that would be put into use for a DAW. Yes, it may be a more fringe usage pattern, but there are actually a lot of people around the world that are making music with the PC as the main equipment these days (controlling it with Midi keyboards/drums and the likes).
Speak for yourself, for my workloads I can't get enough power. These aren't just for children's glorified Xboxes, where the statement may be true. They're better used for work.
Then you're looking at the wrong product. Have you ever thought of that? Do you have TBs of RAM in your box? Or 1000s of cores? Do you drive a formula 1 car? Or an 18 wheeler?
Whenever someone says "[something] should be enough" they're referring to the vast majority of people unless a specific use case is mentioned. In this case the statement stands, the vast majority of people in the world and even on AT can get by perfectly with a current gen 8 core CPU.
Me too. Six year old system. A HP z620 with xeon E5-1650 v2, 6 cores, 12 threads. I also use it for audio production, including lots of vsts, dsps. Sometimes, rarely, I have to bounce things around to get perfect performance, but that's far from often and always so late in a project that it doesn't ruin my creative workflow. And I haven't even overclocked it yet.
It's awesome to have choice. I would choose 16 cores if the cost is not crazy. Most likely we'll need a motherboard upgrade for the Ryzen 3000 cpus to correctly support PCI-E 4.
Really? I had the exact opposite reaction. If a normal $300-$500 desktop CPU comes out with the 16 cores that current $1000 HEDT CPUs have, I'd be pretty thrilled.
Are you concerned about power consumption, clocks, or something else?
going too high on the cores on AM4 would risk performance stagnation or regression due to not enough memory channels. IDK if 2 channels would be enough for 12-16 cores unless the datarates are super high.
The debate over cores vs memory channels has been taking place regarding the 32 core Threadripper vs the 32 core epyc. Many of the original claims about there being performance issues are now being put down to issues being found with the Windows scheduler, rather than a narrow memory channel.
AMD more likely do not see any need to talk about a 16 core solution until Intel has something that can better what they have already announced.
Ok I see the correlation with the scheduler but to be frank that was with TR4 (i.e. quad channel) and it is still unclear if we would run into bandwidth starvation using 16c in a dual channel AM4 environment.
I think it's more likely that they will stop at 12c and that the core chiplet can support 12c
The point is that the EPYC CPU with 8 memory channels sees the same performance degradation as the 2990WX with 4 memory channels. Both have the same number of cores and threads, we can therefore conclude that memory bandwidth is most likely not a problem except in very few instances where all cores need to read or write from memory at the same time which is incredibly unlikely to happen especially as the cache is doubled with Zen 2.
I don't see that as the conclusion though, the conclusion I get is that the core scheduler can impact memory channel utilization badly. If bandwidth wasn't an issue then why would Epyc use 8 memory channels, the additional cost is detrimental to the chips success.
Granted Epyc comes out to 4c per channel which is inline with the 8c AM4 dual channel use case, the additional cache might give us 12c but 16c seems a bit out there imo. But we will see when we get to product launch.
Then you aren't paying attention to the video or the other available articles. Past a certain workload the windows scheduler starts spending 100% CPU moving threads around instead of doing anything productive. Just bouncing threads from core to core. There's a simple rough fix that causes the whole issue to go away.
There always had to be something wrong with windows because Linux never showed the same issue.
And MS will fix it. They have to. Intel wants to go the same way as AMD with a chiplet design, so it would be foolish for MS to ignore the issue. I would expect to see some improvement on that front by the end of this year at the latest.
Edit: you are right, memory bandwidth isn't the issue for the performance degradation as discussed in the video but it is still unclear whether bandwidth would be an issue with regards to 16c/32t on a dual channel board.
Dual channel won't be a problem provided latency is managed - which is now the IO chip's job.
There will HAVE to be an SRAM of some form on the IO die to buffer, distribute, and collate memory accesses - it might just be 4MiB, but it could be 16MiB or 32MiB... GF has the IP.
In the rare situation that all cores are pulling max bandwidth, they have 3.125GB/s instead 6.25GB/s to chew on with dual channel delivering 50GB/s. However, you will find few cases where a single core can chew through that much data in consumer workloads... and even fewer cases where the memory is fully utilized on a system.
"Dual channel won't be a problem provided latency is managed - which is now the IO chip's job."
Memory-access latency in current server implementations is pretty much limited by speed of light in the wires. You cannot overcome it unless memory and CPU are close, and stacking only allows for very limited amounts of RAM (but still WAY better than the outdated DIMM arrangement).
Eventually MS will have to improve their scheduler to hande NUMA better. Intel is moving toward a chiplet design now as well, so it's pretty much a necessity.
If you're not running into bandwidth starvation with 32C64T quad channel (vs octa), how are you running into bandwidth starvation with 16C32T dual channel (vs quad)?
Ah right, didn't think it through and forgot the 2990WX which is basically using 8c/channel so it seems 16c in a dual channel environment would be inline with AMDs current design.
This showed that Epyc with 8 channels was equally performing compared to the 4 channel TR 32 core chip. So, except in certain circumstances, the 16-core mainstream chip should perform as well as the TR 1950/2950X lines.
You cannot prove a negative statement about a wide range of different things (like all programs with all kinds of internal data states and inputs) unless you have tried all of them. Check out the plateau on 16 cores on 256-bit Threadripper in such prosaic and parallel task as compilation.
I actually think this was just to show 8C parity. Nothing they said precluded higher core count. It was more a marketing move to say don't buy Intel now at over $500 per chip. Instead, wait 6 months and we will give you all the performance you want. And the die clearly showed that the second slot for a die has traces to it (not the pics above, but I saw them while watching the keynote on my TV). That means we should see 12 core and above variants coming soon. But that likely is announced for AMD's 50 year anniversary, like saying look how far mainstream has come in that time, with 16 cores.
The problem with the 2990WX is that some of the cores don't have direct access to memory, hence the "Non-Uniform Memory Access" moniker. Only some of the cores are directly connected to memory, whereas others are not, and have to route their memory requests through another core that is connected.
A smart scheduler wouldn't put memory-intensive workloads on those cores that don't have direct memory access - or would at least favor the cores that do - but the Windows scheduler isn't that smart.
Most AM4 motherboards even Xx70 based ones have anemic VRMs. Also improving memory compatibility and IPC are things I am looking at before I dump my current 4770 based PC in favour of a 8 core based for content creation.
Well your need is satisfied per 500W Intelripper. I was just about to build something small to fit under TV, and by all looks I can fit a 6/12 little bastard in there without a creative downsizing.... I will 100% wait for ryzen 3 to be on market....
If AMD released 16 cores now, what would they do with ryzen4 series? That will only be a small process refinement. I suspect we get the 12 and 16 core parts with the ryzen4 refresh in Q3 2020. If the release that now, many buyers won't need anything new for probably a decade.
That is weird form of logic. Between the 2600K and the 7700K there was 6 years of virtually no real improvements from Intel, yet people still bought and upgraded their products. However, even if we take your claim at face value, that would still mean that people would buy them now, and not an Intel product, so they've achieved exactly what they wanted.
There's no need for higher power rating. AM4 official supports "up to 140W TDP CPUs", and "up to 560W peak power consumption". There's a lot of head room in the platform already. Board manufacturers have even stated that many of their higher end boards can support PCIe 4.0 already with a simple BIOS update on the closest PCIe slot. You'd still need a new board, probably an x570 or certainly a redesigned lay out, to get PCIe 4.0 to the chipset and NVMe slots though as the routing distance of PCIe 4.0 lanes is only about 165mm before you need signal repeaters.
A bios update is always free. AMD has always been about open standards and added value whereever possible. There is absolutely no reason to think AMD wouldn't allow board manufacturers to make upgraded bioses available to their costumers, for free obviously, if the board in question can handle it. This is in direct contrast to Intel where it has been proven by board manufacturers and tweakers that have made it happen that z170 and z270 boards could in fact have support both 8th and 9th CPUs with a bios update, yet Intel disallowed it, and requires you to pay more money for superfluous new motherboards.
Don't cry too hard, they won't stay at 8 cores but maybe even you can find some joy in the fact that 8 cores would be prices where AMD's 6 cores are today so 180-230$ or about and not Intel's 500$.
I hope not, that will make them NOTHING. I hope $400+. Again, they've lost 1.2B in the last 4yrs, and 9-10B I guess over the life of the company. Meaning NEVER made a dime in their history. People don't seem to grasp that AMD has been broke & in debt their entire life. At what point do you people think they should make a buck for a year or two in a row? For all of 2017 with a ton of new product launches, they made ~45mil. Previous 3 years were ~400mil+ losses. You can't pay for R&D with 45mil...LOL. Time to make a billion a year! NV's R&D is approaching DOUBLE AMD's, due to NET INCOME. You can hate NV all you want, Intel too, but AMD needs to start acting like BOTH of them, or you're basically telling them "give me a cheap chip, I don't care if you go banktrupt AMD". Well, I don't want that to happen :(
I think Ian's diagram is right, though: That design was made for 2 chiplets. Now, maybe we see some 2x4 chips come out, or maybe 2x6 and never a 2x8, but you don't package things like that otherwise....
Maybe it's also for a GPU die in the upcoming APUs? It would make sense to design it as flexible as possible to have the least work to put another InfinityFabric connected chiplet in there and load some other microcode on the I/O die and have it work as an APU.
Because there is no such thing as a free lunch. Mainstream/Consumer workloads just don't need an endless amount of cores, and would instead benefit more from a focus on 8c with the best ST performance they can achieve with that, instead of possibly sacrificing ST for more cores. Thats ThreadRipper territory then.
Every Single one of your reply are similar. Unless you have actually tried to do parallelism programming in general software, and have proved to be successful, otherwise your need for 8 Core+ ( 16 Thread ) for 90% consumers will be negligible in the next 5 years.
Yes, I am a software developer who has successfully written MT code.
The primary constraint in MT programming is that at a given time, some data stored in memory can safely either be read by any number of cores simultaneously, or only read-from/written to by a single core. So the code just needs to be written in a way where you don't attempt to do both on the same data at the same time.
Sometimes the answer is as simple as just making a copy of the data, so any threads can read from one const/static copy, while a single thread writes any new updates to the other. Once the update is complete, publish the updated data to become the new read-only copy.
If you currently need 16 cores, then by definition you are not a mainstream user, you are a HEDT user. And there are a range of HEDT processors, AMD Threadripper, Intel i9 'X' series, etc.
guess what? TR is going to possibly knock the core count up another notch! *BAM*
So, if the 16-core variant, and there will be a two Core Die chip coming out this year (whether 12 or 16 cores is up for debate), then the HEDT chips could see a move to do a 64 core chip and make 32 core an entry point at 1/4th the cost of Intel's 48 core behemoth AP chip or the Xeon overclockable 28 core chip, kinda like kicking a guy in the nuts when he is down in the dirt.
They can scale up workstation/HEDT CPUs all they want, but that really doesn't change the fact that mainstream consumers just have no need for more then 8 cores right now. People asking for this are just HEDT users that want a cheaper platform instead. Sales of such CPUs would be minimal.
Instead, I wish they don't go down that rabbit hole, and instead make the best 8c CPU they possibly can. No sacrificing ST performance or all-core clocks just to one-up last gens core counts for no reason other then marketing - please!
People for years said quad-cores were enough before Ryzen. Yeah, Bulldozer-derivative quad-module octa-int cores sucked, and yeah the 5960X, 6900K, and 6950X were all there, but once Ryzen 7 1(7/8)00(X) launched, followed by Coffee Lake-S, 4 cores became the budget bare-minimum. And 2c/4t was the basis for 15W TDP mobile U-series chips. And same for the 45W mobile SKUs. And Skylake-X/SP versus earlier EP offerings dovetailed EPYC/TR, when people were formerly arguing a lack of need, sensibility, use, and demand. Also, look at ARM and big.little. I don't think they're sacrificing 1T performance for superior nT. PBO and similar really help with that. Higher core-count for equal money and/or equal core-count for less money can only be a good thing.
Hell, Quad cores are more then enough! There is not a single game on the market today that is not 100% playable on my quad core 3570k rig. On the ryzen 1700 rig, I rarely see more then 3 cores used much at all.
Hey, I'm still on a 6600K myself. But your 3570K will struggle with background multi-tasking while gaming and CPU encoding while gaming. And while it may be enough now, as soon as the majority of machines in the wild can handle it by having higher core counts, it'll be a wrap. China and other countries jumping on gaming may forestall this some, but it's happening right now. Just look at how core and thread counts have jumped at the budget end including low-TDP mobile chips.
got an i5-4960k, 16GB RAM and a GTX 1060 6GB and run into MAJOR problems playing Space engineers, it hits CPU & RAM limits every time. next PC if going to 8c/16t minimum and 32GB RAM
Imagine if you were talking about software in the early 1980s. "No mainstream software needs even 1MB of RAM." Yes, it would have been true, but things change over time. The presence of 16 core CPUs will help drive the development of software that can make full use of many-core CPUs.
True! We may afford 8 core chip... 16 core would make this very expensive thing! Those 7nm Are not cheap now. They will become cheaper in time, but now They Are the newest of the new. When 7nm EV or what ever it will be is released 2020 or even at the end of 2019, this will become cheaper and 16 core at 700-1000$ could be possible. I am happy if we get 8 core at 500$ that is speed of Intel best 8 core... that would be huge! Maybe 8 core will be near 600-700$; but I hope for the less.
It won't be that expensive for a few very good reasons: yields will be better than otherwise with smaller chiplets and better yields drives down the cost/chipet even if 7nm wafers are more expensive to process than 14nm. Also, since yields will be better, the binning gets better too.
actually, there not bad currently, The Ryzen 7 eight-core 2700x 4.35ghz is £350 at Overclockers (UK) The Ryzen threadripper sixteen core 1950x 4.00ghz is £560 at Overclockers (UK) 60% increase in price for 100% more cores/72% increase in performance in cinebench*
No, there's absolutely nothing good with that. Of course it's not good for those who need the performance or for prices if the lower end gear. It could be good for you if you want to hold back development so you don't have an urge to upgrade but ..
Personally the only reason I have the 2600X in the first place is to throw it out vs a 12 core or so chip with better per core performance. If I had kept the 2700X then I wouldn't bother for 15% performance boost and PCI-express 4.
It may be "good enough" for future buyers but it's shit for any of us who wanted progress and hoped for something better.
Hopefully they will put another chiplet there but if they launch this way I assume they can still charge $329 for their 8 core part (beats $599 for Intels ..) and then increase prices for say 12 core to $499 or so and 16 core for $650 or whatever, that scale worse than lineary but anyway .. :D
Why would it scale that badly? The leaked ROME engineering samples showed 16MB of L3 cache per CCX. That's twice summit/pinnacle ridge L3 sizes. That 12 core, two chiplet Ryzen 3xxx chip would likely have 4 x 3 core CCX units with a total of 64MB of L3 cache. It could clock for days, stay in the existing AM4 power envelope, and stay well fed with data! I MIGHT be concerned with a 16 core chip hitting high sustained all core clocks, but, data starvation is not something I'm worried about.
He means price scaling :) More cores is good but at this moment Intel has nothing to compete with AMD 16 core versions, so those would be higher margin products. In 8 core there is competition (if intel reduce prices) If intel does not reduce prices AMD don't have to neither, because they already have cheaper CPU and now it is getting better, so there is room to increase the price if needed. But we will see it in the next autumn when these gets to the shops! Hopefully...
Based on the bottom picture, I'd count on that core bump coming. Just a question of when, really - that off-center positioning that only becomes balanced with a 2nd die really doesn't seem like it could be any sort of accident or coincidence.
No problem with 8 but there should be an option for 16 for people who wants it. I build only ITX systems to use in my job and the more cores the better in a small package. Intel X299 ecosystem was too rich for my blood.
Still i am worried about the absence of any mention to 7nm mobile SKUs in AMD keynote. Fast cpus are nice but the revenue is low, mobile is a far larger market that accout the bulk of intel revenue in Pc space. With the conquer of 7nm AMD should be fully focused to do a dent in laptop space instead to insist in the dying high power segment. Honestly i am surprised.
Why would you be glad to see that? I'd like to see as many cores as possible get into the mainstream, so the impetus to make fully multithreaded software is maximized for software developers.
With just a few cores being standard, it still doesn't matter that much - multithreading might not make up for the initial losses in the form of extra memory usage and reduced efficiency associated with writing multithreaded code.
But those losses are more or less fixed-cost, so if the average desktop PC has 16, 32 cores, that's a fundamentally different scenario.
i presume that's the plan! there's plenty of space leftover, but the memory bandwidth with dual-channel DDR4 coupled to a big GPU is doing me a concern :/ I wonder how high AMD can go on APU graphics cores before mem. bandwidth starts diminishing returns?
I think they're already there, when you look at how the performance of Ryzen APUs scales with memory. The returns are diminishing, but not entirely gone. Having said that, right now AMD's likely not feeling the need to increase APU performance too much given that Intel isn't really competing.
I still think AMD might try to combine IO and APU on a chiplet, though, particularly since they've already laid out Vega on GloFo's 12nm libraries. The IO part would shrink, since you need less of it, and could get by with PCIe 3.0, etc.
The PCIe speed does not really matter if the Vega chiplet would be connected directly to the InfinityFabric (which would make far more sense imho) but the real problem is memory bandwidth... There is a reason why Vega is using HBM memory with far more bandwidth than DDR4. And I don't see a way they could fit even a small HBM stack in there, assuming the Vega chiplet is as big as a zen chiplet
It's worth saying that 'Vega' is a marketing term as much as anything. I think the comment was referring to a Vega module like we already see on APUs like the Ryzen 2400G, which uses system DDR4 memory. On the other end of things is the "Vega" in Intel's Kaby Lake-G parts, which does have HBM2 memory, but is basically Polaris otherwise (rapid packed math, etc.).
A shrink to 7nm for the mem controller, PCIe controller, and other IO items wouldn't pay off. It would shrink them maybe about 10% and wouldn't reduce the power they use, which wouldn't offset the added cost of the shrink. (That's in the AdoredTV video on AMD's chiplets.) We MIGHT see them put into an active interposer underneath the CPU cores, though. That depends on what tech they develop for it. I think Intel is already working on that.
They also have Vega on TSMCs 7nm libraries so thats not a concern, also the 7nm Vega has the shader intrinsics and rapid packed math fixed, so I would think they put the newer part in there.
presumably, the distance from the IO die to x86 compute chiplet is low enough that latency isn't notuceably affected. Memory controller tightly-integrated on-package is still going to be far lower latency than the old Northbridge arrangement
When you have memory controllers on separate CPU dies, then when one CPU needs to access memory that is connected to a different die there is a pretty large latency penalty and it makes memory access very non-linear.
The chiplet design with a centralized I/O controller makes memory accesses more consistent.
On a Ryzen CPU with only 1 CPU chiplet this may not be the fastest way to design the chip, but if they're doing modular CPU design it saves them from having to design 2 different CPUs, 1 with and another without a memory controller.
Plus having the I/O hub as part of the design allows for adding another CPU or GPU chiplet to the package without having to rearchitect memory and I/O.
Hmm... doing some back of the napkin math... it does look like AMD has enough space for a appropriately powerful GPU. Initially I had my doubts which is why I started trying to figure it out.
Based on Ian's math for the CPU chiplet size, we're looking at ~80mm^2. Assuming that TSMC 7nm is actually double the density of GF 14nm (if the actual scaling is known someone let me know - I don't know it offhand) and that they won't need memory controllers in the GPU (because they'll be in the I/O hub), then that should comfortably give enough room for an RX 560 levels of compute, maybe with a decent chunk of cache on the GPU die to help with bandwidth constraints...
And there's the limiting factor without HBM or some other memory architecture for on-package SoC-style iGPUs from AMD... bandwidth limitations. They're coming. People forget how Zen slides promised 5W TDP chips and GPU+CPU EPYC (IK about embedded...). It's all in the works, I'd guess.
In terms of functional units, RX 560 at 1024 Stream Processors across 16CUs isn't that much bigger than the 704 Stream Processors across 11CUs in a 2400G. With the shrink to 7nm power should come down nicely too.
I think they have both the thermal and package-area budget for something in the range of 11 to 16 CUs. Maybe they'll build a 16CU GPU and only enable 14CUs to account for yields and keep power in check. That leaves room for enough of a GPU performance gain over the previous generation to be compelling.
As I'm sure others have said and will say, AMD is probably running up against the ceiling of what they can accomplish with on-package graphics without adding memory channels, moving to next gen DDR for the whole APU package, having on-package HBM, or adding a significant cache a la Crystal Well for Intel.
The DRAM latency will always be bad. it's more important to have low cache latency but I'm not sure whether the L3$ or big L2$ are on the chiplet or the IO-chips...
L1 and L2 are typically core local, so they will be on the chiplet for sure, and I am also pretty sure they put L3$ on the chiplet to, because the same chiplets are used on epyc and without a pretty big cache you could run into infinity fabric bandwidth problems for cache access from all chiplets.
Maybe there is a second shared L3 or L4$ on the I/O hub? Some cache will be there for sure to buffer InfinityFabric and DRAM access, but they could put quite a big cache on there and use it as a L4$ victim cache, so that if 2 chiplets need the same data from DRAM that data is already in the I/O L4$ after the first read and you save the extra jump to DRAM. But that cache would be far less important on Ryzen where there is only one die
yes this is extremely surprising, in pre intel I series, this was the major advantage that AMD had over Intel. I hope for AMD stake this is a typo. Only thing I can think of it was more important to AMD to put the GPU on the chip then the memory control but ran in to difficulties putting memory controller on 7nm process.
What comes to mind as solutions is Intel EMiB and similar - which allows different components of different die process on same die - even different manufactures like 8705g on my XPS 15 2in1
Latency should be more linear and homogenized than Zen/Zen+ MCM designs. I don't see how near-latency isn't wrecked going out to main memory without sorting out far-latency, so there's got to be creative workarounds implemented there. I agree that Zen 2 DRAM latency may be better than some fear since clock domains, IF, the I/O die, and MCs may have more well-considered compromises than people have been accounting for. That opening on the package has got to be for a second die. Doesn't make sense otherwise. Minimizing trace-lengths, or maximizing heat dispersion would leave the layout bi-symmetrical or corner-to-corner. I'm just curious and confused why the I/O die for Matisse is so large compared to the features in Rome. Maybe it's for redundancy with yields... but 14nm yields were excellent and S/P Ridge didn't even utilize full PCIe lanes. I also doubt an L4 cache. Maybe this is necessary to maintain socket backwards-compatibility with both PCIe3 and PCIe4 on the I/O die? Only time will tell.
In order to service 16 cores I would expect SRAM to be present to buffer memory accesses. It might just be 2~4MiB, but it's pretty much going to be required.
The die is a good 30mm^2 larger than needed, which is enough room for some L4, but we also don't know how large PCI-e 4.0 is nor the additional die space required for other features.
Given that Lisa Su verified the die is a unique die for Ryzen, it only makes sense that it doesn't have a bunch useless server bits on it like earlier models.
I could see a small L4, but not a large one. You're correct that it would conserve power and bandwidth by buffering memory accesses, but it's not necessary per se. I would've expected the Ryzen I/O die to be a bit smaller versus Rome's, so there's definitely that. Although Rome's need for L4 would be at least as great proportionally as Matisse's if needed so clearly at all. I don't think an L4 is likely, though it is possible. It may be an idea for a future Zen derivative as well. I'd say that's definitely something being considered if nothing else, but at what cost and how to implement effectively?
There's potentially room for about 16MiB of L4, but that's making a LOT of assumptions about what else is on the die and the density of the L4 (just straight up using the L3 as a reference for 16MiB).
The most valuable buffer could be a write coalescing buffer as it could keep the infinity fabric from backing up, thus allowing higher burst speeds. With four CCXes issuing writes at a potential rate of 50~100GB/s there will be a real need for a buffer to handle write bursts.
How are you even surprised? Epyc chiplet/IO die told you nothing? They are not stupid enough to design 2 different IO subsystems requiring 2 different 7nm cores.
That's it? Even AMD's own propaganda doesn't put the MIRACLE RyZen 2 ahead of last year's 9900K... you know the chip that the AMD fansquad insulted as obsolete in 2018?
Oh, and insult it all you want the the IGP in the 9900K is literally infinitely faster than the non-existent integrated graphics that AMD couldn't be arsed to put in it's miracle chip even though Lisa Su gave the usual 10 minute copy-n-past screed about "heterogenous computing".
1. No AMD fantard is ever EVER allowed to claim that power consumption on the desktop is somehow vital after we've had to sit through the last decade of B.S. about how Bulldozer "is really pretty good" and how the abomination of the PCIe non-compliant RX 480 and the power-vacuum Vega 64 are "really good!"
2. Who says that in Q3 these CPUs are somehow going to be dirt cheap? TSMC isn't a charity and AMD has to buy the most expensive silicon from them PLUS pay GloFo for the northbridge that they can't seem to get integrated into their "miracle" chiplet even in a consumer product.
1. Where is the Intel Fantard rulebook you're using so we can communicate properly? I don't see anyone mentioning Bulldozer being good, just you being a corporate cheerleader.
2. No one. I said it's likely to cost much less based on what we know of the design philosophy and estimated costs floating around. This multi die solution has very obvious cost savings vs. Intel's monolithic die approach (which is why Intel is moving towards this solution itself).
Sometimes, I wonder why political disputes have to be so violent, and why mankind is so prone to war. Then I see that some people start foaming at the mouths because they don't like another company's CPU chip - when they're free to buy the one they want, and no one is forcing them to do anything they don't want to do!! Sigh. War: war never changes.
Some people get invested in Corporations like they do sports teams. AMD having a good product doesn't make Intel's suddenly bad (and vice versa). Ryzen is the first AMD product I've bought in some time because it represents an excellent value/performance proposition. If Intel fits my needs better the next time I'm buying something, they'll get my money.
It's hard not to respond to posts like this because they are so obviously based on emotional investment and not in the reality of the information presented. Even if you have interests in Intel you should want active competition to move the market forward.
I know right? Just don't communicate with anyone who can't use appropriate language to you. You shouldn't have replied to Cajun anyways, he's a nobody.
lol rabid Intel fanboy having a meltdown because AMD has again twice the cores at same price but this time around they also got the single core perf and clocks to match Intel. As for GPU, who said that AMD does not have 6 and 8 cores APUs with a GPU that is a few times faster than Intel's and ofc again half of Intel's price. Do please seek medication, sane humans to not have feelings for brands.
you are trying to compare last years Intel vs 2h 2019 AMD
Lets see how it fans out at end of year - right now anything from both AMD and Intel are both speculation. But my personal better is on Ice Lake Sunny Cove
It is not core count that matter but the core architexture. 2019 seriously changes that I would bet that 4 Core Sunny Cove base CPU could be a 8 core Zen 2 based computer any day.
Sunny Cove looks very promising, but I don't think we've seen working silicon. I HOPE Intel delivers on it this year, but with the execution problems plaguing them lately I'm not confident here.
If Sunny Cove is the big improvement we're being told it is, then we should see Intel comfortably ahead. I'm not as optimistic as you are about 1 SC core = 2 Zen 2 cores in most workloads, but I could see some very big leads in many use cases. Which will almost certainly prompt AMD to answer back. And we, the consumer, are the winner :D
Yeah, it doesn't make sense. HStewart is crazy. From SB to SKL, Intel widened the execution ports progressively. Now it'll deeper and wider with SC/IL. Should bring a few percent, but no doubling. The 2c to 1c comparison is meaningless babble due to thread scaling and programability. Whether discussing Amadahl's law (https://en.wikipedia.org/wiki/Amdahl%27s_law) or compiler optimizations, ISXs, and APIs, there is no simplification that accurately encompasses this issue. That remark sounds like a gamer talking about the weakness of BD-derivatives. I think SC should be a nice bump, but I can also see AMD deepening and widening the Zen core easily as well. Between the MCM approach, AM4 phasing out, DDR5 coming (Maybe PCIe4 being short-lived yielding to 5 sooner than expected), and how Zen was a comparatively small core from a transistor-count and die-area (Even with discrepancies between 14nmLPP versus Intel's 14nm node) perspective versus SKL derivatives, it's easy to see the Zen core become beefier. Also, Zen's core power efficiency is much better than Intel's (Not talking about uncore topologies). agner.org provides excellent historical context and perspective. See https://www.agner.org/optimize/microarchitecture.p...
Or they may only put in an IGP there. 12/16 core only make sense if AM4 can feed that load. I'm guessing it probably can with DDR4 speeds continuing to climb, but it may be a factor and I'm sure AMD has the numbers. As far as frequency and scaling, I think you're probably right. Validation samples (especially ones used at high profile presentations) are likely to be conservatively clocked. Headroom should at least reach 4.5GHz based on what we saw with the 2xxx refresh from AMD. 5GHz is possible, but might be a stretch. We should see soon enough.
IDK. There's an AWFUL LOT of symmetry on that package. 2 CPU dies seems awful likely. Also see https://twitter.com/IanCutress/status/108309908688... . Also take into account TSMC's 16nmFF power-frequency behavior versus Samsung's 14nmLPP when used in GP Pascal-based dies. TSMC's 7nm may do better than people think versus 12/14nm GF processes, between which there were 300MHz. I'd personally guess that 4.5GHz is conservative when you look at that and the 2950X's boosting. And architectural choices also contribute to the frequency tolerance of a design, not only the process. Zen 2 surely took that into consideration.
I would much rather see more cores than an iGPU. With a properly-written Windows scheduler, and software designed to take advantage of the hardware, it will work. Don't hold back the hardware because the software isn't there yet - the software may not get there until the hardware is available.
Or have everyone jump to Linux. And I think the most progress happens when hardware and software move in tandem. Look at GPUs. Specialized FF units were often built-in but never implemented or utilized. A total shame and waste.
Have you considered a possibility there might be some small GPU on the unusually big I/O die? It's much bigger than Rome I/O suggests and I doubt it's all cache.
Its on a brand new process, if it wouldn't use less power that would be the real tragedy (like Radeon 7).
Personally, I did hope for more then just catching up to Intels performance, even if its cheaper and less power, but what I'm ultimately interested in is performance. But of course there is still half a year to go, so we'll see where it really ends up standing when it releases.
Clocks, BIOS tweaks, microcode tweaks, all sorts of things.
Look at the improvements we've seen with BIOS from Ryzen launch to the latest AGESA's! We're looking at a chiplet design that's not even at launch yet, who knows what they need to iron out still that they're playing safe for now to make sure it doesn't crash during the presentation... including probably running the voltage high to ensure stability.
You are the worst kind of consumer. The kind whose identity is apparently wrapped up in one company versus another. Your comments are useless. Please stop posting them.
Rotate the CPU chiplets by 90 degrees and it looks like three of them can be squeezed into the same package with the IO die. This of course presumes that the IO die has the on package links for all of them already.
That's just bad math. What someone needs to do is analyze the gap measurement between Ian's 2 die mock-up and Rome package shots. And 24c on mainstream would encroach too much into next-gen TR territory without bringing enough extra fight to Intel. Not even to mention power requirements, symmetry, space for surface package components, and the offset.
More likely you would get a bigger chip with 2 more chiplets mirrored on the other side, that occupies a bigger socket. That seems like the logical solution for TR3.
I think TR3 will be based on Rome. Unlike 1st/2nd gen. TR though, I suspect we may see units without all of the EPYC dies. For example, there could easily be both 5 and 9 die TR configurations. But this depends on cache considerations, data feeding structures, and silicon harvesting.
Also, I think AMD wants to push past the 32-core 2990WX, if possible, for the right price of course... not to mention the power-efficiency gains won't likely go to all-core frequency of these heavily-threaded chips. Not in this age of core steppings and turbo states. A halo chip is good for marketing, costs little to develop this diversified option when SP3 and TR4 are a common socket layout, and easy to do.
Pretty sure it was the Ryzen 5 meant to be paired with a GPU chiplet she showed but time will tell. Obviously it was an early engineering sample as you'd not normally see unsymmetrical CPU designs in a finished product. There certainly is room for another core chiplet or a rather beefy Vega GPU.
Yup. So 65-75W for the actual CPU at full load compared to the I9 at 115-125W. Pretty darn impressive when you consider it's not final silicon and clock speeds, and it actually was a shade faster.
Of course there will be a 16 core. The layout is there. The power profile is there. This is a teaser-- "See, we can match a 9900k with only half a processor". Two possible reasons for not showing the full 16 core layout. 1. It's not ready. 2. It really isn't twice as fast by quite a bit due to memory bandwidth limitations with only two channels. Clearly a 16 core Treadripper will outperform. The sweet spot with this layout may be two cut back chiplets in a 12 core configuration (i.e. more cache BW per core and just about the limit of two channels usefulness). Also, depending on the actual release date, they could go for DDR5 compatibility along with pcie 4.
AMD's cadence would imply the Zen 3 is coming next year. If DDR5 is ready for mass production which we will likely see is both Zen 3 chiplets with this IO die for AM4 and a new IO die + Zen 3 chiplets for a new AM5 socket.
The more interesting question is if this same IO die will be used to put a Navi GPU into the same package alongside some HBM.
I'd say DDR5 is more slated for Zen 4 because of challenges in maintaining backwards-compatibility on AM4. Maybe shrinking and shifting the I/O die would allow for on-package HBM... I haven't checked the DDR5 standards, and while I remember both DDR2/3 support on Phenoms back in the day in a very pro-consumer move by AMD, I don't see it happening this go around.
DDR5 support would just mean a socket change to the hypothetical AM5 socket and require a new IO die. The CPU chiplets wouldn't inherently have to change though, hence why Zen 3 in 2020 could easily bridge both memory types as there would be two different sockets/IO dies they would connect to.
The development between IO and CPU chiplets is now disjointed and can proceed and their own individual paces based upon market demand. For this same reason, I strongly suspect the Zen 3 chiplets due next year will leverage the exact same IO die we are seeing used today.
Mark Papermaster suggested Zen 3 would bring opportunistic efficiency gains, indicating otherwise, Also, AM4 is a promised 4-year platform: 2017(1), 2018(2), 2019(3), 2020(4). They could have two overlapping sockets, but the product confusion for consumers and the high initial cost of new RAM types would probably outweigh the benefits. Recall how much DDR3/DDR4 cost when they were first brought to market.
Zen 3 would be a 2020 part so they'd still be honoring their commit to AM4 without issue.
You forget that AMD did pull off two sockets simultaneously before in the past: AM2+ and AM3. The first Phenom AM3 chips would work fine in AM2+ sockets.
Considering AMD's current chiplet strategy and past history, I don't see much of an issue for them to introduce AM5 at the tail end of 2020 with Zen 3 and upgrade it to Zen 4 in 2021. If DDR5 prices remain prohibitally expensive through 2021, they could again do a simultaneous release of Zen4 on socket AM4 and AM5 (though I don't consider this likely). Moving to AM5 would also permit AMD to resize the socket if they wanted to so they could include more and/or larger dies. Increased core count or features is an easy means of differentiating AM4 and AM5 products.
I did not forget that. I mentioned the backwards compatibility with DDR2/3 here: https://www.anandtech.com/comments/13829/amd-ryzen... . Given some context with SP3 server cadence, socket pin count utilization, DDR5 and PCIe5 generational timing, development of their "next-gen" GPU post-Navi, HBM3 and LCHBM, as well as Gen-Z, OpenCAPI, and TSMC's 7nm EUV HVM, a hard split between AM4/5 between Zen4/5 makes way too much sense with timing. Intel's Aurora delivery shows a focus on parallel data HPC that goes with their dGPU push in 2020/2021 and Mark Papermaster in an interview relayed with Ian Cutress: "IC: ...Can you make the same commitment with Zen 4 that was shown on the roadmap slides? MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change. IC: So one might assume that an intercept might occur with Zen 4? MP: No comment (!)". Interview @ https://www.anandtech.com/show/13578/naples-rome-m... He also told EETimes that Zen 3 CPUs would offer only “primarily leverage efficiency with some modest device performance opportunities” Papermaster’s sentiment hints at an approach with Zen 3 that’s not all that dissimilar to Zen+, especially when taken with how James prior said "It’s not an area statement, it’s a power efficiency statement,” with regards to the move to 12nm with Ryzen. EETimes Reference @ https://www.eetimes.com/document.asp?doc_id=133399... Also: https://www.pcgamesn.com/amd-zen-3-7nm-cpu-archite... All evidence would seem to indicate that your expectations for the AM4/5 transition are misplaced.
AMD played it wisely with the AM2 to AM3 transition as DDR3 price took awhile to fall to reach DDR2 levels. DDR4 prices are still inflated to the previous generation DDR3 and DDR5 is expected to start off more expensive than DDR4 is now. Yes, Mark is correct that a transition will need to happen but AMD's current strategy permits them to operate at their leisure to pick an optimal time frame: the CPU side isn't going to be delayed due to troubles of DDR5 deployment.
Also the quotes you cite hint more about the socket transition but they don't hint at what chiplet would be used. In otherwords, MP is referring more to the IO chip than anything else. They are are two separate entities now with different road maps now.
The problem with DDR5 is, that it's not backwards compatible, so you would need new motherboards. But AMD said, that the new Ryzen 3 CPUs can be used in any existing AM4 motherboard, so I'd guess there will be no DDR5 support
At the very least they will put an IGP in some SKUs on the desktop side and this space will be used for it. They may also opt for a another CPU chiplet as you're speculating
Because no one has these next chips in their testing labs.
And this isn't the first time two separate dies were leveraged for a memory controller (IO die) and CPU die: Intel did this nearly a decade ago with Clarkdale on socket 1156. Memory performance there compared to Lynnfield was poor as this setup still had a (then) traditional FSB setup but entirely in-package.
AMD's link between the dies is far higher bandwidth from all indications so that aspect should not suffer. The impact to memory latency is going to be the big question on desktop. For server though, average latency should see an improvement due to consolidation of all the NUMA nodes across multiple dies, though minimums should increase a bit.
@Kevin G, Right. Yeah, we know it's not released, yet. But, there's no mention of "Infinity Fabric is faster," or something like, high latency issue with Infinity Fabric is being addressed or something like that.
IC: Do the chiplets communicate with each other directly, or is all communication through the IO die?
MP: What we have is an IF link from each CPU chiplet to the IO die.
IC: When one core wants to access the cache of another core, it could have two latencies: when both cores are on the same chiplet, and when the cores are on different chiplets. How is that managed with a potentially bifurcated latency?
MP: I think you’re trying to reconstruct the detailed diagrams that we’ll show you at the product announcement!
IC: Under the situation where we now have a uniform main memory architecture, for on-chip compared to chip-to-chip there is still a near and a far latency…
MP: I know exactly where you’re going and as always with AnandTech it’s the right question! I can honestly say that we’ll share this info with the full product announcement.
The 2700x would need some 4.6GHz in Cinebench to match the 9900k isn't it? So same significant clock for clock gains would allow AMD to compete without very high clocks. The power numbers do suggest that clocks have room to go up a bit so that's good.
The dual die approach, let's see latency and let's see what kind of APUs we get. Looking good though, with IO die approach they can do lots of IO so we escape silly PCIe limitations they can do 16 cores at 500$ or less, they can do big APUs - hopefully with more memory channels so new mobos. As long as somehow memory latency isn't high but not quite sure how they would do that.
It would not neccessarily need a high clock to match the i9. We know that zen 2 has double the FPUs and 6µOP/cycle dispatch, if I remember correctly 4 of those can be FPU/AVX (2 ADD/ 2 MUL/FMA) or 4 ALU or 2 AGU. As far as I know Cinebench is pretty FPU heavy, so say it can do one AVX op and an AGU for memory access before hitting dependencies, then SMT could be very effective, because only half of the AVX unity would be used by one thread, and there is still enough dispatch bandwidth available. But I'm no expert in CPU design so I could be really wrong here, just a speculation.
The real question is if Zen 2 takes a clock speed penalty like some of Intel's chips do when running AVX code. So far AMD has hinted at 'no' but that was in the context of base clock, not turbo. If we take AMD at their word instead of a grain of salt, the question changes to what turbo frequencies can Zen 2 maintain while running full width AVX2 code vs. SSE?
7nm Ryzen compete with i9 9900K ??? And in Cinebench which is known to run better on AMD ryzen ?! I mean if Ryzen is equal in cinebench, then 9900K is probably faster overall
What a big joke. Why the hell desktop should care about power consumption, it is not laptop. Performance is what matter for high-end users.
This could be looked at as an estimate for how much power Rome will use; Data centers care a lot about power efficiency. Also it shows that at the same power consumption as Intel, they should beat the 9900k by a large margin
I'd say that's a fair guess, but it's an ES @ est. 75W TDP, with different tuning based on thread-loads, so I don't think this particular config will ever come to retail. But it's probably pretty close.
I'd like to know how many PCIe 3.0 lanes. It's rather frustrating with a mainstream CPU+mobo to be told that you have only two M.2 sockets, and one of them is only PCIe 2.0, and that if you use one of them, you lose a PCIe slot, etc. I'd like to see enough PCI 3.0 lanes to actually support all the PCIe slots and M.2 sockets on an ATX motherboard.
In any case an x4 PCIe3 NVMe drive should work similarly as an x2PCIe4 drive, so fewer lanes for cards should provide comparable end-user results for consumers. Compute is a different matter entirely where lanes can be a bottleneck of significance. XDMA CF works fine, so consumers needn't worry AFAIC.
One quick observation on cost scaling. They got the CPU die, IO die, packaging as major costs and when they add a second CPU die (or GPU) ,they have rather good cost scaling as the IO and packaging stay flat. So they can offer rather good prices at flat or better than flat margins for 12-16 and 6-8 cores+GPU.
Yep. AMD's earnings calls have heavily emphasized rising ASPs and margins creeping up faster than ever into the low-40s. 7nm may have lower yields, but the decrease in size and the MCM approach will make up for more than people are accounting for.
I'm wondering too. S/P Ridge did enable equal CCX parts, with cache enablement varying by SKU, but B Ridge didn't w/ its 4MB L3 and iGPU. APUs in this MCM design will probably leverage the CPU's L3 to an extent, so there will be some data traffic. But since 2 dies is different from 2 CCXs, I think the asymmetrical design might not be that unlikely depending on die harvesting on 7nm between EPYC and Ryzen parts, not to mention potential future mobile SKUs with the MCM design fitting on FP5. Also keeping all L3 traffic on one CPU die may be popular with gamers for high-percentile minimums. Only time will tell and speculating is for share-holders.
There's a reason that the mobile parts AMD announced at CES are still on 12nm - they don't want to deal with chiplets for lower-margin APUs. At the moment, AMD has a real lead on Intel on graphics performance.
This makes me think that they might be working on a combo IO/GPU die at 12nm (since there's not a pressing need to shrink the GPU to 7 until Intel can offer more of a performance fight). The IO part of the die can shrink, since there's less need to go off-package if the GPU is right there.
There's still the expense in packaging the chiplets up, but we don't know what kind of prices AMD is getting on the 12nm parts from GloFo these days...
But mobile SKUs have higher ASPs with OEMs than desktop APUs, so the margin argument isn't so fair. I think the real issue is waiting for Navi and sorting out the MCM design with the I/O die and how that'll fit into mobile with the FP5 socket and all that.
One thing re: shrinking from 12nm to 7nm: No one else has gone from GloFo 12nm to TSMC 7nm and released a chip, but AMD did go from 14nm GloFo to 12nm GloFo for its Ryzen chips, and from 14nm GloFo to 7nm TSMC on its Radeon Instinct line.
It's far from a perfect comparison, but the 7nm TSMC Radeon MI60's boost clock is 20% higher than the 14nm GloFo Radeon Instinct MI25 (1800MHz vs. 1500MHz, the base clock for the MI60 is unpublished). The 12nm Ryzen 2 (Zen+) clocks about 6% higher than the 14nm Ryzen (Zen).
That means that we can probably expect boost clocks on Ryzen 3000 (Zen 2) to be about 13% higher than Zen 2 and 20% higher than first-gen Ryzens.
If that's the case, then the numbers today either indicate no IPC improvement (which contradicts what AMD told us about Zen 2 for _years_) OR the clockspeeds we saw are likely to be significantly lower than final silicon.
Most likely. Early Ryzen silicon did run lower clockspeeds than the final version. Same is true with Intel prototypes. How much lower is the intersting question. Well we in it Q3.
Yeah, but frequency scaling on GPU is very different from CPU with power-delivery and thermal-caps. Also, look at single-thread CPU OCs versus GPUs OCing a smaller number of shaders (e.g. 1060 OCs vs 1080s). I don't think comparing CPUs to GPUs for process changes is all that meaningful whether talking about power-efficiency, equal-power for more performance, equal-performance for less power, or stock and OC frequency and power behavior.
This way they can use the same chiplet design for the whole range - Ryzen, Threadripper, EPYC if they want and they do not have to use expensive 7nm chip area for something that can be easily done at 14nm. It is probably only the need to keep socket compatibility that stops the PCIe lane count being increased to 32.
It'll be interesting to see how AMD balances high/low when AM5 comes out and they balance the need (for memory channels, PCIe lanes, etc.) between the low-end (Ryzen 3s/5s with APUs) and high end (Ryzen 7... maybe 9? with up to 16C/32T?).
Great news! I am not partial to either AMD or chipzilla, but a strong 3rd generation Ryzen can only be good for all of us. If Matisse is indeed the price/performance leader for a given use scenario, then AMD it is. If this removes the constipation in Intel's CPU pipeline and makes them more regular, it's good news if it's too be Intel's CPUs.
Regarding the number of cores: yes, more cores and threads are principally good, but a key challenge for anything x86 remains single core/ thread performance, and that performance crown is still owned by Intel. I hope that single core/thread performance is what AMD has focused on here. As backwards as it may seem, as long as, for example, browsers still use JavaScript, single thread performance is key for many every day use scenarios..
If you properly used Web Workers, then JS is not single threaded. Most of the time it doesn't matter though as the performance impact of the JS is not enough to slow down the page very much.
"The company did state that it is the world’s first 7nm gaming CPU, and will also be the world’s first mainstream CPU to support PCIe 4.0 x16."
WTF is a "gaming CPU?"
If, there is such a thing as a "gaming CPU," what makes this particularly more "gamer-y" than another CPU?
Or, does Ryzen 2 address the "gaming" aspect that prior Ryzen didn't?
Does this mean a "fix" to Infinity Fabric's high latency issue?
If so, how?
I am going to wildly speculate that if there is, indeed, a Ryzen "gaming CPU" that it might have embedded RAM? It's the only thing I can think of at the top of my head that would permanently fix that latency thing.
It's a CPU that makes sense for gaming, so it's a mainstream mid range to high performance CPU. Not an Atom, Celeron or Athlon, but also not a Threadripper or i9 x/xe.
Infinity Fabric will still have an impact on latency on new zen 3, but I don't know the detailed chiplet design, so I don't know if there is inter-core latency or just additional memory access latency, which would not be as bad, because the same latency increase that made a huge difference in L$3 access is almost negligible in DRAM access.
According to papers/articles already written about AMD's Infinity Fabric, the inter-core latency is not the issue. It is the Cross-CCX-latency... the latency associated with traversing and hopping on the so called magical Infinity Fabric highway....
There is no mention on this wonderful new tech AMD created at all. All they talk about is more cores, IPC, etc.
What about the highway you built, yo? That sounds more interesting to me. Wouldn't you other "Techies" agree?
Yeah, but to some extent you've got to speak to your audience. At CES, the intended audience is as much the tech journalist at mainstream media (wire services, Time Magazine, etc.) and gamers, and isn't really the right place to talk about architecture. AMD did a decent job outlining things at the EPYC Rome presentation a couple months ago, even though a lot of it was "we'll tell you more later."
Are you still yammering about Infinity Fabric? The fact that AMD didn't talk about it to your personal satisfaction implies nothing - except maybe that it's working fine. Give it a rest.
I'm pretty sure we will see that second 7nm die eventually. Honestly: why would they layout the CPU this way if it wasn't primed for a second die. Even from a pressure distribution perspective this would be nonsensical. Why they didn't show it that way... who knows. Might not work yet, might actually be to stir exactly this kind of speculation, might be they did want to show off they really can do high clock speeds on the same silicon that apparently has 100% core yield.
Also it simply makes sense from a yield perspective. With two chiplets they can recover even halfway wrecked chiplets to run in 8 core CPUs, which for all intends and purposes will remain the "sane" consumer core ceiling for some time, I think.
Will we really see 12 or even 16 core CPUs ... pretty sure 12, 16 probably. Memory bandwidth will be an issue with some workloads. Then again with some it won't. Hugely depends. And if it's just to 1up intel on the consumer platform... AMD will go beyond 8, and I think they've shown they theoretically can. And if TR keeps being "half" Epyc .... there really isn't much cannibalizing going on. It's hard to think of a TR3 with less than 16 cores among 4 chiplets. That would be true garbage silicon then.
I'm also pretty sure we'll see GPU's as the second chiplet at some point, however APU's lag behind the standard CPUs a full generation since Ryzen 1000. And two APU designs at the same time? Nah. Those will be Renoir and we won't see them before 2020. And considering how well even Raven Ridge is holding up ... that's kinda fine.
Ian, you didn't loose your money yet. There are traces to the second spot you point out on the PCB (hard to see in your photo, but I could see them at certain angles when Su held it up during the keynote). For latencies, since they are using the I/O die like on the Epyc CPU, they are able to mask the NUMA element so the entire package is a single NUMA node. That avoids the pitfalls of NUMA node issues we saw with first and second gen TR and first gen Epyc.
That space will be filled by release, I could guarantee that. Meanwhile, the IF2 controller and higher bandwidth, lower latencies of second gen Infinity Fabric will be present. In fact, the latency of going off die for every memory call will already be found by doing the I/O die with IF2, so please ask questions on the IF2 latency. Meanwhile, that means accessing the cache on the second die, since it was mentioned Epyc has it fully routed through the I/O die, will require the additive latency of going all the way round trip, 2 hops each way, unless they are using the enlarged L3 cache to be mirrored between the two chips, with some way setup to sync them and retire the data relatively to each other. That might be why the L3 was enlarged that much. So many more questions.
But don't pay up until after the release.
Also, with the cache on the active interposer for Foveros, likely L3 shared cache feeding the L2 for both the bigLITTLE cores, I have to also say I'm very impressed with the 3D stacking Intel is doing. I crapped on their statements last month and need to eat my words there, just as an aside.
I could see that they do not have a shared L3$ between chiplets, but rather some kind of L4$ in the I/O die. I would think it would make sense to have that L4$ as kind of memory bandwidth saving method, so that when two chiplets require the same data, it is already in L4 after the first fetch, but the CPUs don't have to talk to each other to first see if any L3 contains that data... Kind of the same as between L2$ per core and L3$ shared, the cores don't look into other L2$ to figure out if they have the data, they just look in L3, and if it misses, then it gets fetched from memory.
They could mask the NUMA configuration, but it probably wouldn't be a great idea in general. It's useful information to have, if only the operating system uses it properly.
I am actually ok with it just being 8 core and if it is 8 cores on a single die even better. From the looks of the CPU and the space left it does look like they left themselves the option to either add another chiplet if needed or this is not the top end chip and we just might be seeing a 10 or 12 or 16 core CPU as well. I myself plan on just going for the 8/16 CPU when they launch. If they do indeed release a 10 or 12 core part I might look into that as well but if adding a second Chiplet adds latency and causes games to have less FPS then I will just stick with the 8/16 CPU which is more than enough for me anyway.
This is great!! I'm planning a pcie4.0 build (hedt) and seeing how these cpus will perform and how Intel will answer is so fucking exciting! I CAN'T WAIT!!! :D
Ian Cutress, you can't "pre-announce" anything. You either announce it, or you do not announce it. There is no other status of announcing. "Pre" means "before", as in a sports pre-game show that occurs before the game that it announces. You can "early announce" something, but that is still an announcement. You also violated one of the rules of logic. Something cannot be both A and B at the same time and in the same context.
They didn't announce the SKUs with a launch date. They did demo the hardware though, before announcement. I don't think the pre-announcement phrasing was at all egregious. It's fair to call it a pre-announcement demo as they weren't announcing final products for sale.
You can easily "pre-announce" something. If I say "we have a new product coming up, we're not going to announce final clock speeds or configs yet but here's some info" that meets all the criteria for not announcing something but nevertheless providing information on it. Hence pre-announce.
It's announcing that there will be a product announcement. At a product announcement, you give the product a name, specifications, availability (and usually pricing). They did not do that, but they did preview one chip that they will be announcing later. Not every "announcement" is the same - yes, she did announce things, but she did not announce Ryzen 3 products specifically, so she made some "pre-product announcement" announcements, hence "pre-announce."
"later" necessitates a "before". pre (before) announcing the product. This is information being prior (before) announced before the product announcement. sing-electric is correct.
That IO die, like on the Epyc, is awfully big. I think there's more to it than just 24X PCIe, IF, USB 3.1g2 and a couple SATA ports. Is the memory controller on it? Could there be some L4 cache on it?
Seriously, the whole Ryzen 1000 line was 192mm^2, made with the same manufacturing process, with 8 cores, and this IO die is 122mm^2. How could the combined IO die and 7nm core die sizes be larger than the original Ryzen die if it contained the exact same features? There has to be more there.
192mm^2 - 88mm^2 = 104mm^2, so, yeah, perhaps that extra space might be made up for extra IF circuitry for another die to attach.
Still, the combined die sizes come out to bigger than the Zeppelin die. The old CPU CCXs at 14nm were 88mm^2 total, and this node shrink should reduce the CPU cores about 40% and the cache by about 10%, so I would think the CPU chiplet would be closer to 50-55mm^2, yet it is over 80mm^2.
I knew something looked too big. I was wrong about the IO die, but not about something being too big. My first thought was perhaps an inclusive L4 cache on the IO die to reduce cache snoop stalls, but that was wrong. Perhaps converting the L3 to an inclusive cache instead of the victim cache function it serves now? Perhaps an increase in cache size? I think increasing the L3 cache size while keeping it a victim cache would be counter productive. Anyone have any ideas on what they'd do that would increase the CPU chiplet size?
Availability Q2 or Q3. Isn't this when Intel 10 nm Sunny Cove will be around too? If AMD catches up to 9900K then Intel will increase the performance again. Is it ok to say, AMD Zen 2 comes a bit too late?
Intel was caught unaware when the initial Ryzen came out. They had to rush to get the 8700k out. The 9900k is at the limits of the ring bus that keeps the processor operating, and operates above it's specced TDP. I seriously doubt Intel could do anything to extend the performance of what they currently have out. They need to get new tech out to show AMD more competition, and that isn't coming for at least another year. Sunny Cove isn't expected to see the light of day until Q2 or Q3 of 2020, not 2019.
In the mean time, AMD is not only competing, but doing so at much lower prices. Intel is having a much harder time of this than most people think.
As dgingeri said, Intel is in a bit of a predicament currently, their architecture is at its limit and the new architecture is only expected around 2020. A die shrink could have helped them achieve parity/similar performance to AMD, but 10nm is still delayed.
They'll probably have 7nm out before/same time as 10nm in 2020/2021.
I just hope this is $400 or so, or even closer to Intel $478 if it is just as good. NO DISCOUNTS. It's time to make NET INCOME. Then add a 2nd chiplet and release 12/16 cores ASAP to slap those ON TOP of Intel. Don't charge $299 for this unless it really sucks perf wise. It seems it's directly competitive with Intel 9900, so PRICE it like that! Quit passing up opportunities to make INCOME, by attempting to either get market (with no margin) or be your customer's friend. Charge what your chips are WORTH! In the last 4yrs they've lost 1.2B+ (~400mil losses for 3yrs, 2017 finally made ~40mil NET INCOME). 2018 looks like a few hundred mil for the year, and we'll know that in a few weeks (29th or so Jan). If you want to FINALLY make money for 2yrs straight, don't give a dang discount on a chip that runs like Intel's $478 chip. Price it at $450. It is NOT your job as a company to GIVE away chips with every launch at major discounts.
IE see rumored Navi10 pricing, $249 for a GTX 1080/1070ti perf...Uh, should be $350-400 then min probably. But $249, well, I'd fire management for this price. They won't make money. Not sure if they'll make a dime on $699 card either, as 16GB HBM will kill the card most likely as it has done to EVERY consumer card they've put it on (besides holding up production on top). It should have been 16GB GDDR6 or GDDR5x. There is a reason NV made billions going GDDR5x instead of HBM/HBM2. There is no need for HBM in current cards as 2080ti shows. GDDR6 fine. They keep making the same dumb decisions (HBM, kill production+kill NET income). AMD should not be producing a consumer gpu with HBM (1/2 or 3). It gets you nothing but PROBLEMS (cost or production issues) and kills sales or profit. Charge what you're worth, but quit adding crap to your products that kill their INCOME or ability to sell them (hbm production issues constantly killing launches).
The manufacturing costs for Ryzen chips is less than $70. Even with this 2 chip package, it probably doesn't amount to more than $80. They can charge less and sell more and spread the engineering costs for the chip over a larger sales spread, and still capture market share. There are a lot of financial "experts" that just don't understand this aspect of business. They think in order to make more money they have to charge more. That's not true. If a business needs to recover $1 billion in engineering costs, they can do so more easily selling for a $200 markup across 5 million units more easily than charging a $2000 markup and expecting to sell 500,000 units. Plus, with the lower markup, it is more likely to sell additional units past the point of recovering costs for pure profit.
FC switch and storage makers didn't understand this, and they lost market share and sales to an inferior technology: iSCSI. Now, businesses are buying iSCSI storage hand over fist because the ethernet switches cost so much less, even if it performs far less effectively than FC. In 2005, the cost of physically manufacturing a 48 port 8Gb switch was under $800, not including the engineering and development costs. They charged over $30,000 for one with only 16 ports enabled, and an additional $8000 to license 16 more ports, for a total of $46,000 for a 48 port switch. Manufacturing FC storage was actually less expensive than iSCSI storage because the standards were much more simple, but the FC storage sold for more because the only ones buying it were the ones who could afford the switches. If they'd charged only $4000 for those switches, they could easily have sold a hundred times as many and made more profit. In addition, that would have allowed businesses with lower budgets to buy FC storage, thus reducing the costs from the makers and increasing adoption. Instead, they kept the market restricted with high prices, and small businesses adopted iSCSI. Then iSCSI became the "budget" standard, and higher end businesses began adopting it for cost savings. Now, FC storage SANs are practically dead, despite the fact that 32Gb FC can outperform 100Gb iSCSI by over 30%. Many FC switch companies lost profits and ended up being gobbled up by other companies, and FC storage is pretty much gone. The FC switch makers priced themselves out of business.
AMD would probably make twice the profit selling their top end AM4 chip for $300 than they could at $400. That extra $100 would likely discourage half of their buyers at least, and end up reducing the profits they would make substantially. It is a delicate balance, and ones their financial experts likely have already calculated.
@ Ian Cutress: Just wanted you to know: "we were told that the Core i9-9900K was allowed to run at its standard frequencies on an ASUS motherboard." Not what I saw in the press release footnotes @ https://globenewswire.com/news-release/2019/01/09/... Footnote #9: "Testing performed AMD CES 2019 Keynote. In Cinebench R15 nT, the 3rd Gen AMD Ryzen Desktop engineering sample processor achieved a score of 2057, better than the Intel Core i9-9900K score of 2040. During testing, system wall power was measured at 134W for the AMD system and 191W for the Intel system; for a difference of (191-134)/191=.298 or 30% lower power consumption. System configurations: AMD engineering sample silicon, Noctua NH-D15S thermal solution, AMD reference motherboard, 16GB (2x8) DDR4-2666 MHz memory, 512GB Samsung 850 PRO SSD, AMD Radeon RX Vega 64 GPU, graphics driver 18.30.19.01 (Adrenalin 18.9.3), Microsoft Windows 10 Pro (1809); Intel i909900K, Noctua NH-D15S thermal solution, Gigabyte Z390 Aorus, 16GB (2x8) DDR4-2666 MHz memory, 512GB Samsung 850 PRO SSD, AMD Radeon RX Vega 64 GPU, graphics driver 18.30.19.01 (Adrenalin 18.9.3), Microsoft Windows 10 Pro (1809)." Yeah they made a typographical error with "i909900K" instead of i9 9900K or i9-9900K. But they also specified "Gigabyte Z390 Aorus"
Gotta say: nothing Su presented yesterday was any bit surprising. So we got: higher clocks, tuned performance, lower consumption, lower manufacturing costs all-round. Yeah. The chiplet design is groundbreaking, but its benefits are part of a longer-term strategy (which is not exclusive to AMD, btw. Intel is going down the exact same route). The key to AMD's strategy right now is squarely pegged on the yields of 7nm output... much like Intel's on 14nm++, and that can be quite dangerous.
Early Zen 2 silicon is showing tit-for-tat performance with Intel's Core i9 on the same number of cores. That's good. That's what we want. Same performance, a few less bucks.
On the GPU side, I was seriously underwhelmed by the shrunken Vega. Same thing, different node.
Is it just me or is AMD's current strategy just bitch-slapping Intel where Intel is throwing money at? (eSports)
2600x and 2700x are already faster in CineBench by cca 5% than 8700k, 9900k respectively clock to clock.
Hypothetical situation. Had it been no IPC gain, just improved frequency and power consumption, 2700x on 7nm or 2700x even on their 14nm+ would have been faster by 5% if matched clock to clock - i7 9900k boosts @ 4.7ghz for all cores.
You're not looking at the all-core difference between the 2600X, 2700X, 8700K, 9900K, not to mention cooling solutions, motherboard configurations, RAM speeds, timings, bandwidth, and channels, and how the all-core is sustained in Cinebench R15 under varying considerations. Also the feeding data structures with core acceptance off of uncore can be a bottleneck at high core OCs with diminishing scaling and reduced IPC. This is why cache overclocking exists, and the interactions are also dependent upon and nuanced with IF mesh, MoDeX, and the Ringbus of SKL K-SKU derivatives.
"The key to AMD's strategy right now is squarely pegged on the yields of 7nm output... much like Intel's on 14nm++, and that can be quite dangerous" don't think there's much need to worry. TSMC was early to HVM 7nm, has a strong track record, and has worked well for Apple, Huawei, and Qualcomm. The chiplets are small enough that yield is more comparable to mobile dies than Intel's monster monolithic parts.
Zen 2 seems to have finally matched Intel's single-core IPC. Too bad the "leaked" specs last December does not match the 8-core's TDP at the keynote. Just hope the pricing will keep intel on its toes. Having said that, a 16-core Z2 would definitely be sweet for my next 3DS/Maya/Resolve build!
Don't know about that. It was an engineering sample. They probably set the clocks to edge out the 9900K and the 75W TDP was an incidental byproduct. There may well not be a final product with a 75W TDP. I'd say that's likely actually.
AMDs manufacturing strategy looks like it is taking another huge leap forward here. Fair bet says that they will use exactly the same 7nm CPU chiplet in *everything*. Server, desktop, HEDT, APUs, and even the next gen consoles.
Only having *one* 7nm chiplet to design/test/validate (and manufacture) has so many positive advantages it would be hard to list them all. But that's obviously their plan, and it's one that I doubt Intel will have an answer to anytime soon, even if they do get their 'relaxed 10nm' working.
IDEALLY, a MCM GPU would be better than monolithic. It just requires a creative scalable architecture that is transparent to software with the challenges of mGPU programming.
nVidia has done research into this published a research paper on the topic.
It would be foolish to think that AMD is not perusing the same ideas on the GPU side that they have shown on the CPU side.
In fact one of the obvious things to do for GPUs and chiplets is to spin off miscellaneous IO (PCIe, HDMI, DP controllers) and various codec engines to their own die as those don't need perpetual updates between GPU generations nor cutting edge manufacturing.
IK about the NV paper. And AMD is very aggressively pursuing scalability. I think MCM GPUs from AMD that aren't plagued with mGPU programming challenges are slated for post-GCN. Whoever makes it to MCM GPUs will have a MASSIVE advantage over the competition. But MCM GPUs are significantly more difficult than MCM CPUs as David Wang rightly pointed out. Some aspects of Zen will definitely migrate into the RTG side. Already has, even with Zen and Vega if you read the white papers.
The balanced performance would implement a cross bar die that housed the memory controllers so that every compute die would have even access to. The catch is that the cross bar is massive in current designs and scaling up the number of nodes here only further increases complexity. Getting enough memory bandwidth is conceptually also a challenge as they have to be placed close to the cross bar die. This does mimic AMD's strategy with the Zen 2 based Epyc.
A NUMA based GPU design with say, four nodes in a package each with their own pools of HBM memory on twos sides for a 4096 bit wide bus wouldn't be a bad decision either. However, scaling like the centralized idea above faces some physical layout challenges and doesn't inherently make individual dies smaller. nVidia's research paper explored this and was estimating around ~85% as fast as monothilic die due to the shear number of links and high bandwidth connections between each die (if you're using interposers, go all out here). While many think that this would be seen as a quad GPU setup (and for certain workloads, you'd probably want it to be), it can be virtualized to appear as a single GPU for gaming. The dies are close enough and have enough connectivity and bandwidth between each other that I don't see this as being an issue for most workloads.
An extension of the above idea would be to build compute dies and memory router dies which the HBM sits directly on top of. Essentially this is a tiled grid of compute and memory routers. Each router can coherently manage traffic form the four nearest neighbors. This enables scaling to higher compute, memory bandwidth and memory capacity but comes at the cost of far higher scalability issues. Instead of a single high bandwidth hop between nodes, we could be approaching 10 in a realistic design. The issue shifts from bandwidth to latency and being able to distribute a workload evenly.
Maybe. But their consoles might cut cache for power reasons. Other changes are also easily possible with mobile. It is almost certainly still a victim cache, but still needs to operate within a power budget. Jaguar, for example, cut some units it didn't much need while beefing up others. I wouldn't be surprised if you're right, but I wouldn't be surprised if you're wrong.
I was expecting to see 12 and 16 core chips. I hope those are still coming. 8 cores is not enough on desktop anymore and should be the minimum on notebooks and tablets now.
If all you're doing is browsing the internet or playing games then, sure, 8 cores is enough for you, today. Me? I do a lot of things simultaneously on my computer (on top of all the crap Windows is doing simultaneously out of view). More cores lets me keep multiple 3D art programs open simultaneously without waiting for loading, for example.
Lisa Su: So there is some extra room on that package. And I think you might expect that we will have more than eight cores. I didn’t say how many more.
If your machine isn't holding up, then you either need to revise your workflow or jump to an HEDT platform. If you really actually need that performance then even if its difficult to swallow the price tag, you can't afford not to. You also didn't indicate what CPU your using now as a basis for 8 is not enough. And while 8 is enough for most people now on mainstream, more at the same price or the same at a lower price is by no means a bad thing. Also, you seem to contradict yourself by calling 8 the minimum for notebooks and tablets while saying that browsing and gaming is served plenty by 8. As that is what the vast majority do, 8 is appropriate for mainstream desktop, and if you're not in that populace, you need HEDT, SHED, or server parts. This is not to say that I don't hope and expect still to see 12 & 16 parts.
If your machine isn't holding up, then you either need to revise your workflow or jump to an HEDT platform. If you really actually need that performance then even if its difficult to swallow the price tag, you can't afford not to. You also didn't indicate what CPU your using now as a basis for 8 is not enough. And while 8 is enough for most people now on mainstream, more at the same price or the same at a lower price is by no means a bad thing. Also, you seem to contradict yourself by calling 8 the minimum for notebooks and tablets while saying that browsing and gaming is served plenty by 8. As that is what the vast majority do, 8 is appropriate for mainstream desktop, and if you're not in that populace, you need HEDT, SHED, or server parts. This is not to say that I don't hope and expect still to see 12 & 16 parts.
"there’s just enough space for another CPU chiplet (or a GPU chiplet) on this package"
*OR* a huge chunk of level 3/4 cache.
I'd prefer to stick with 8 cores + HT and get 128 Mb or more of high speed Level 3/4 cache on the package. That could give some great improvements for certain work loads....
That's not possible as SRAM that large (128MB(Think you meant MB, not Mb)) would fit in that gap even at 7nm. Furthermore, copying data around is hardly power efficient, and that wouldn't work either. L4 might help justifiably with server workloads and could be used to help with power efficiency by reducing bandwidth constraints by having to copy out to DRAM. But not in the way that you're suggesting.
Possibly (Probably at that size.), but even still CW had huge die-space dedicated to that. This isn't happening here at that quantity. There are several other things they could try to alleviate these issues such as ChargeCache.
With the extra space, a "3400G" with 4GB of HBM2 and a newer GPU would be an amazing mid-tier product for gamers wouldn't it? It would cost less money and power than buying a separate video card and since Kaby-G Intel was already able to squeeze on a GPU solution that sits in between a GTX 1050 and 1060. For the same size/power, Navi should be a major leap over this into GTX 1070 territory if it used HBM2. This type of custom chip could have applications for consoles as well, just swapping out which chiplets are popped in and for consoles the HBM2 could be used as the sole memory. Using system RAM at current DDR4 speeds seems to be the major crippling factor for APU's.
I don't have any verified sources for current HBM2 costs, but posts from 2017 indicate it was around $75 per 4GB module. Assuming this has gone down some, for home use settling for a 6c/12t CPU and paying maybe $50 premium to include a gigantic GPU performance boost would be very enticing to me. And it isn't a true $50 (or whatever the current price is) since this also means you need less system memory that isn't shared. For a mid-grade system could easily get by with 8GB DDR4 instead of 16GB with dedicated GPU HBM2 replacing the cost of more system RAM. A 3400G with 4GB HBM2 and 8GB of system DDR4 would cost very similar to one with no HBM2 and 16GB of system RAM and perform WAYYYY better.
Doubt there's enough space on the package for HBM2 and a decent number of CUs on a GPU die, even at 7nm. Not to mention the niche demand as the whole upgrade, sell, buy, replace dynamic is different with integrated than discrete.
It's definitely a niche among hardcore ennthusiasts but I think we underestimate the market for people who buy whole systems and upgrade every 3 or so years by replacing the system. I would bet that this number eclipses the every 3-6 month upgrade 1 component cycle most of us live by. Is there a reason the Kaby-G can fit 8GB HBM2 and a nearly RX570 GPU on their package and Ryzen 3 couldn't fit 4GB HBM2 (1 less module) and a smaller Navi chiplet (my terminology is probably all off, I have no experience with chip design lol)?
Again not a huge market but the NUC concept has been successful enough to carry on for many years now. AMD could definitely claim a chunk of this with how good Ryzen/Navi APU combos could perform.
Also as far as sales/marketing for the very large population of whole system buyers, I believe the Kaby-G model can legally be sold as "discrete Vega graphics" products. Some of these products list in specs: Processor: Intel 8th Generation Core Processor, "Graphics Card": RX Vega M.
Not sure what the distinction is that allows a company to call the GPU a "graphics card" or "dGPU", but the average consumer would never know the difference in these types of systems. And they are in fact getting discrete graphics card performance although there isn't actually a card lol.
Problem is that for HBM2 to make sense, it needs a GPU that needs it. And even at 7nm, there doesn't seem to be enough space for a meaningfully large Navi chip AND an HBM2 stack on the AM4 package along side the I/O die and CPU die. https://hexus.net/media/uploaded/2018/6/5a1a21b1-a... for reference. Also, I don't think most people live by the cycle of a component every 3-6 months, even amongst PC gamers, even if factoring in peripherals. What will eventually happen is having dGPUs plug in to desktop boards via a physical interface more compact than a huge PCIe x16 card. Gen-Z or OpenCAPI and the like may well bring that.
Also, the niche covers Kaby Lake-G designs. AMD might want to hit those because of space, cooling, and power-delivery advantages versus a dGPU in a notebook that'll never be upgraded. It's more likely these are the target than the desktop chips that come on the side. This seems more likely to be their focus if/when they go this route.
Initially, my reaction was that it is very likely there will be a 16-core Ryzen, since the technique for doing that was pioneered on the 32-core Threadripper, so AMD knows how to do it. But the 32-core Threadripper served a purpose, because EPYC motherboards are expensive and hard to get. If you want 16 cores, why not get full performance, and get a Threadripper board? So AMD may have the ability to make a 16-core Ryzen, but they may be undecided as to whether it's really a worthwhile thing to make.
Threadripper is a different market segment. It's not only about the cores, it's also just as importantly the PCIe lanes, total memory bandwidth and maximum supported memory. A 12/16 core Ryzen will have very minor impact on the lowest end of the Threadripper line up, if any.
"The 8-core AMD processor scored 2023, and the Intel Core i9-9900K scored 2042." Uhhh Ian? You've got those two Cinebench scores backwards. It was the AMD chip that scored 2042, with the Intel i9-9900K pulling down 2023.
If AMD maxes out at 8 cores in mainstream (at least at first) then they must be very confident about Zen 2. Well, they did say they designed Zen 2 to compete with Ice Lake, din't they? If they do not need more cores to compete with the best 14nm based mainstream CPU from Intel why would they increase the cores? It might be best to reserve that little space in the corner for when Ice Lake / Sunny Cove is released, which would be 5 to 6 months later (if Intel does not screw up again).
At the end of the 'Attacking the Mainstream CPU Market: Toe to Toe with Core i9-9900K' paragraph do I read QUOTE: 'so it would appear that a lot of current 300 and 400 series motherboards, assuming the traces adhere to signal integrity specifications, could have their first PCIe slot rated at PCIe 4.0 with new firmware.'
My questen is how do you understand this. Will it be possible to have dual Graphics Cards, One using PCIe 4.0 and the other using PCIe 3.0 both running x8?
And will it then be possible to swap one of then out with a two or four way M.2 PCIe riser card? as i am looking into a system with two or tree M.2 NVMe x4 SSD's.
Haven't trawled through all 300+ comments, so someone perhaps already brought this up.
I *really* hope that this new chiplet approach doesn't mean that ECC support will be gone from the standard Ryzen CPUs. If there's anything I've always liked about AMD it is their lack of need to cripple their products.
FWIW I see a Ryzen 7 3xxx in my future ...provided it supports ECC memory, of course.
@IanCutress, any insights into that at this point?
Good to see AMD catching up with Intel at absolute performance numbers. Still sad though, because this is done at 2 about generations ahead in terms of node size. Well of course at some point , if you do no other significant improvements, but still improve your manufacturing process you will catch up, but this is no real catching up , right? And I don't think that it is so difficult for AMD to improve its performance per node process. I just can't believe this is due to an intrinsic disability of their engineers. The same way I can't believe Intel really encountered any obstacles in going from 22 to 7 nm as they have been claiming for a while now. Which means all this is set up somehow and for some reason. Personally, I like the model where "computing" is more important than "gaming" , because actual gaming (and not FPS or camera moving games only) really requires the "computing" philosophy, and because I like to do other things than gaming only.
Really? And the fact that AMD demo-ed a mid-range Zen 2 part CPU with 8 cores and 16 threads which slightly beat out the i9 9900K at half the power draw means nothing?
Or the fact that Zen 1 and Zen+ already closed a significant gap with Intel and that majority of industry developers code for Intel in the first place (and not AMD)?
AMD did good considering what kind of brute force approach they need to take to appear 'good' in people's eyes'. Once the industry is optimizing more for AMD products in general, the landscape will probably change even more.
I've been doing good with a 6/12 core/thread first gen Ryzen but what the hey, I want at least 8/16 and for my other computer I want 64/128. And hold on, who told everyone about my Saturn V addon.. Who told? It was going to be my best computer ever that would plaster me into the moon at 186K miles per decade.. LOL... Gotta have cores and more cores... But really, 8/16 should last a long time.
People seemingly complete discount/dismiss the impact that transitioning from Bulldozer through to First gen Ryzen/ThreadRipper/EPYC had to the global tech industry, it shot a "smart shot"
AMD could not compete on speed, raw performance etc etc etc, what they could however compete on is loading a single chip with numerous cores and/or split up a motherboard in it's entirety to slap upon a single processor (AMD was the first to a true dual core etc etc etc)
Point is, Intel was far too dedicated to optimizing power use (when not in turbo or overclocking it in any way) as well as performance everywhere they could though slapping more cores as well as more threads was not as interesting in getting something to run mach 20 and sip power while doing so (how many years did they mange to do exactly that)
problems of course become magnitudes more difficult the more crap you cram under that tiny little hood, so I suppose making a single wicked core "makes sense" a single anything no matter how large cannot compete vs many many little guys running a bit slower (reducing heat, power, complexity, wafer yields, keep all features available to every chip you put out for that generation etc)
GPU sped things up, then did FPGA, then did ASIC (which GPU "use" to be a completed "board")
anyways....long and short of it..AMD expertise in shrinking things, reverse engineering and the like allowed them to slam a load more everything into the same space, Ryzen 1 was a massive success, it hurt Intel and Nvidia and everyone else in their own fashion,
Ryzen+(12nm) just sped it up and optimized some of the key features ( XFR and Precision boost version 2 etc) made them smack the living crud out of intel, that is a fact, intel is already hurting dearly from their own "bad cake" sort of speak, AMD is just piling the hurt on.
AMD is doing targeted strikes against the weakness in the INDUSTRY not the individuals, I personally believe that, we need MORE to propel the way forward, more for less of a higher quality and reliability/support network backing it.
Ryzen 3 was/is truly the "right place at the right time" unless all of them are buddy buddy and allowing AMD massive "industry wins" ($$$$$$$$$$ sales therefore market and mindshare which are priceless)
Splitting up the I/O from the core, genius, are they the first, no, did they do it the best way thus far, oh hell yeh....my phones CPU/GPU while crazy fast for a phone simply does not stand a chance in the level of "smart" (clock speeds alone, slowest my phones cpu is "allowed" is 1.6Ghz x 4 cores (locked speed) 2.35Ghz on 4 cores (locked) where even second gen Phenom II are able to drop their clocks to as low as 400Mhz while still being able to autooverclock in excess of 4.3Ghz on up to 6 cores 6 threads.
anyways... AMD seen what the industry needed and has been doing what they could "to be a business" but more than that, in my honest to god opinion, I see Dr Lisa as one of those "rare folks" that see the path that needs to be taken before all should fail, where all the others sit back and are more or less ok to play the same old pissing match.
I suppose 20+ years all the ups and downs with economy is not enough warning for folks, last 3 years has been $%^&$%^ brutal for the tech world, more or less except for AMD that has hit all its targets between the eyes (the only way to take down a bull)
More of everything for less, this way here "simple things" that me and you might like to do, like ripping multiple tracks and such at same time has become (with AMD) much more easy to have, now we are talking 8 core 16 thread at less overall power use than the average single core was many decades prior (125w vs say 45w, ok the new one uses more, but, it can crunch metadata at magnitudes more effective rate as well the old chip was always at its max power use (more or less) the modern ones sip power to max performance back and forth constantly.
That is my story and I am sticking to it, Ryzen to change the world.
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Chaitanya - Wednesday, January 9, 2019 - link
Good to see core count on mainstream stay at 8 rather than bump as those rumours were suggesting.velanapontinha - Wednesday, January 9, 2019 - link
True. 8 is more than enough.notbillgates - Wednesday, January 9, 2019 - link
"8 cores is more than enough." ..."640kb should be enough for anybody" ...
nukunukoo - Thursday, January 10, 2019 - link
Spot on notbillgates! As a 3DS Max and Maya creator, I think 512,000 cores might be enough...BoemlauweBas - Thursday, January 10, 2019 - link
Your looking at a gaming Desktop CPUGet 4 Xeon Platinum 8180 's & if that isn't good enough get yourself 8 volta's. Still no ? Cloud
But will all due respect, I doubt you make stuff an 8way volta can't handle in a decent amount of time.
hanselltc - Saturday, January 12, 2019 - link
yo my buddy u dont seem to want that CHEAP low core count chip there?zer0cool3r - Saturday, February 9, 2019 - link
Or simply get a Ryzen Threadripper, does the job for any professional content creator, be it games developers, movie cinematics creators, and all heavy-graphics rendering jobs out there. I guess this year's new gen will go up to 48/64 cores, 7nm technology.. will be a perfect beast for sure but also on the professional end of pricing, meaning it will most probably cost around 2000$.Ironchef3500 - Thursday, January 10, 2019 - link
+1close - Thursday, January 10, 2019 - link
Just like every other parrot out there, some people still keep taking this out of context and running with it.TODAY. 8 cores is more than enough TODAY (and for the reasonably foreseeable future).
Flunk - Thursday, January 10, 2019 - link
For you, some of use do things that are very parallel on a regular basis. Games? Sure 4 cores is fine.Flunk - Thursday, January 10, 2019 - link
I admit that I might just buy a Threadripper.peevee - Thursday, January 10, 2019 - link
8 (really equivalent to ~12 in as SMT adds ~50% load from each core) is WAY more than enough for 128-bit DRAM bus and caches way less than working sets of any reasonably performance-affected programs. Threadripper has 256 and EPIC has 512 for a good reason.Flunk - Thursday, January 10, 2019 - link
That's a really wierd combination of conjecture and nonsequters. You really shouldn't write about things you know nothing about.CheapSushi - Thursday, January 10, 2019 - link
Well...that is the point of it.Lolimaster - Saturday, January 12, 2019 - link
For many heavy usage you don't really need quad channel or extra pci-e lanes, more cores on mainstream totally makes sense. If you need extra features you go threadripper.close - Friday, January 11, 2019 - link
@Flunk: Yes, an 8 core simply can't handle all that self importance...The problem here is not that 8 cores is not enough, it's that you stumbled onto an article about a product that's not for you, that you don't understand, that doesn't address the needs of a small niche you consider yourself to be in, and you were just confused and decided to post. Cool, it can happen to anyone... if they really don't even try to make an intellectual effort.
The vast majority users don't need more than this and the revenue doesn't come from the self-proclaimed ultra-professional who needs 10000 cores to make his comments look more weighty. An 8 physical cores CPU covers basically the entirety of the market with a few niches to be covered by more specialized parts, with a number of cores even in the 3 digits.
When people say something is enough they don't intend the statement to cover exactly 100% of the use cases in the world for eternity (like the parrot above also seems to think). Otherwise every car would be strapped to to a Saturn V because a handful of dudes really needed to go to the Moon once. And you'd have at least 2TB of RAM and 1024 cores because that's what I have in some machines.
So I'll ask you one question and if the answer is *anything* but a single number then you already proved yourself wrong and no amount of CPU cores will fix it for you: what is enough? ;)
AdhesiveTeflon - Friday, January 11, 2019 - link
This post makes the most sense.Fighting about core count or who can get all the GHz is like fighting about cars. 1000hp would be great but I'm willing to bet that's less than 0.1% of the population is ever going to need it. The ones that do use 1000hp is another 0.1% of the population that actually races. Most dual cores out now are still fine for daily tasks. Why bother the general population with spending more money for that 0.1% of the time?
deil - Monday, January 14, 2019 - link
for games 6 is already a better choice. Dual core games are already in minority, most use 4 cores/threads.if you add OS (so game can get 100% from CPU) you need 4/8 at minimum with favor of 6/6 or 6/12.
YES, we all benefit from 6/12 becoming mainstream.
close - Monday, January 14, 2019 - link
Well... Guess the parrot got @Flunk's tongue. When asked how many cores is enough as a followup to his whines that 8 is not enough, Flunk went dark. Probably needs more cores to be able to answer.Orange_Swan - Monday, January 14, 2019 - link
actually, a single game I play, space engineers, can benefit from more cores and more frequency.evernessince - Thursday, January 10, 2019 - link
Of course and if everyone followed this mentality application developers would still be working around a 256 KB memory space limit.The fact of the matter is anything over 8 cores is nice to have and will push developers to use that additional power. As has happened many times in the past, it will be put to use. If AMD come out with a $400 16 core who in their right mind wouldn't want that? That's a hell of a lot better then 2 years ago when in order to play game you had to close everything just to get max FPS because Intel has been cucking the PC gaming community for a decade.
No, I think I'll always prefer progress over stagnation.
RSAUser - Friday, January 11, 2019 - link
Read a paper a while ago, had to do with threads that a developer can actually use.Think it ended up that at about 500-600 threads, we get to the point where we can't feasibly optimize it anymore, outside of certain scientific workloads. Mostly has to do with a concurrency problem, current design is to use one main thread to manage all the other threads/work as a handover, e.g. login can be highly parallel, but still needs an entry point, that thread has to still pass on the request, and logins are an easy task to parallelize, there are a lot of things where that's not possible.
That said, more than 8 cores is fine, for most game devs, if you can get past 4 cores, making it split among 16 is just as easy as 8, well actually from 16 -> 32 due to SMT.
RSAUser - Friday, January 11, 2019 - link
That said, for my personal use, I often render stuff, do a lot of code compiling that would save me substantial amounts of time. Went from a 4790 to a 2700X was about a 60% reduction in time due to the higher amount of threads.plsbugmenot - Friday, January 11, 2019 - link
It sounds like everybody assumes that nobody else needs it. I'm really looking for a combo of single threaded speed and many cores.For audio recording tasks, you're fight against audio dropouts on the single threaded speed. It sucks re-recording a six minute segment five times in a row. For playback with multiple VSTs you're fighting a combo of single and multiple core usage.
tyaty1 - Sunday, January 13, 2019 - link
By the time 8 cores wont be enough, this CPU is going ti be obsolete anyways.The Architect - Monday, February 4, 2019 - link
No it's Not... I am an Architect and a CG artist... World is a big place and PC's are meant for more than just gaming... In the Arch Viz/ Film Industry/ Render farms/, more the number of cores, Better it is... So I say let them keep innovating, more is always better, There is a huge market for such things and huge render farms that can take advantage of this amazing core count and a well positioned price to performance ratio...twtech - Friday, February 8, 2019 - link
And if more cores don't start finding their way onto people's desktops, it will be enough forever - because the time investment required by software developers to make use of lots of cores won't happen if the users won't actually benefit from it.rocky12345 - Thursday, January 10, 2019 - link
I think what he/she meant was 8 cores should be more than enough for most people and most work loads they would be doing. For power users and those that run VM's yes they would like to see as many cores as possible because they probably can put more cores to use. For my own needs 8-12 cores is about right for what I do on a computer. Now if I can pick up a 16/32 CPU at a decent price of coarse I am gonna go for that even though the CPU probably will never get used to it's max.If things go as I think they will I am sure AMD will be releasing a 16/32 CPU on the main stream desktop in 2019 more so if Intel's next CPU's have higher than 8 core counts for the main stream desktop. I personally think the CPU Lisa Su was holding up was a Ryzen 5 CPU and we will most likely have 12/24 Ryzen 7 CPU's in the spring of 2019 & maybe 16/32 Ryzen 9's as well. You can clearly see from the picture of the CPU there are traces where the next CPU die will go so I am sure they have plans of releasing something much better than what they have shown at CES.
Owhan - Monday, January 14, 2019 - link
8 cores is perfect today. It is the sweet spot. It is better than having 16 cores performing worse per core, which is the inevitable result of such a design. In a couple of years, 16 cores will be the sweet spot, but not before.For around 90% of the market, that is.
damianrobertjones - Saturday, January 19, 2019 - link
""640kb should be enough for anybody" ..."This is often taken out of context. Go search for the 'entire' conversation (if bored).
mito0815 - Thursday, January 24, 2019 - link
Name checks out. That's assuming Gates actually said that.twtech - Thursday, January 10, 2019 - link
It depends on the workload, but not really. The only reason why you don't see a big difference from it in gaming, etc., now is that consoles don't have massive numbers of cores yet, and most games are written for the lowest-common-denominator in that regard.With frequency scaling starting to hit a wall, the only way to increase power going forward is to increase core counts, and games will have to react to that. Eventually increasing the number of cores you have will probably be the standard way to increase game performance.
Flunk - Thursday, January 10, 2019 - link
That and they don't really know what to do with the CPU cores in current-gen games. Most games are GPU limited.twtech - Friday, February 8, 2019 - link
Most game engines today are still primarily single-threaded, with individual tasks - such as rendering, physics, audio - being given their own separate thread. It works, but it doesn't really scale.There are also ways to build a fully-multithreaded game engine, but it's just not necessary/worth it - yet. When we have say, 32 cores in a game console, it will start to become unavoidable. Carmack also did a talk on basically how to do it at QuakeCon in 2013.
What it boils down to in a basic form is that, to implement lock-free multithreading, additional memory needs to be used to duplicate some of the data, and there is some efficiency loss in the duplication of some calculations. Once that up-front penalty is paid however, then performance can potentially scale almost infinitely with core count. It's questionable whether or not it's worth it to take that approach at lower core counts. But it almost certainly will be when the target hardware has llarge numbers of cores.
B3an - Thursday, January 10, 2019 - link
All you peasants must do is browse sites and write utter shit like that if you think 8 cores is enough.You're truly pathetic people with small inferior minds.
close - Thursday, January 10, 2019 - link
Yes... you have to wank on *all* of the internet's porn videos at once and that requires some serious processing power. Like... at least 9 cores. :)Other similar issues;
- Wallets are never big enough to accommodate the 2cuft of "spare change" $100 bills most people walk around with
- Condoms don't come in the 2by4 size most guys require
DillholeMcRib - Thursday, January 10, 2019 - link
Mine are more 3x9evernessince - Thursday, January 10, 2019 - link
What kind of low def videos are you watching? 8K or nothing. Takes 6 cores to decode a single video.rrinker - Thursday, January 10, 2019 - link
Really? I run multiple server VMs plus whatever else is running locally with FOUR cores on my laptop, and it all runs just fine. Definitely not a peasant level function. I am SURE there are workloads that can use 16 or even 32 cores - but for Pete's sake, this is a CONSUMER processor. Not a HEDT part. 8 cores is massive overkill for the 90% of computer owners who read email and play Facebook games all day. Hmm, 90%? I'll bet it's even a higher percentage, and the percentage that actually do something that needs 8, let alone more, is WAY less than 10%. DESKTOP, not servers. You want more than 8, get a Threadripper, why complain that this one is "useless' or inadequate? You people make no sense..RSAUser - Friday, January 11, 2019 - link
So you want the product segmentation/stagnation? I am sure AMD will release a hex core to address the lower end market.Why get a quad core if you can get a hex core for the same price with a higher performance? Your argument is dumb, software is designed around the current capabilities, if those capabilities increase, software developers will write applications that can take advantage of it.
Magnus101 - Sunday, January 13, 2019 - link
For me personally 6-8 Cores (12 threads for my 8700k) combined with a really high CPU-frequency is the optimal combination. I use it mainly for DAW (music production). With loads of DSP going on with software synthesizers, digital effects and so on at the same time and in real time (not rendering) where low latency is key, CPU-power is extremely important.And the number of cores counts too, but not at the cost of CPU-frequency, since too low speed per core will cause spikes because a number of synths/effects will be running on the same core and if you add a heavy instrument (cpu wize) it will cause glitches/crackles if there isn't enough headroom for every core.
Another thing is that AMD Ryzen is out of the picture for low latency work. Yes, they may work at high latencies for mastering engineers, where things aren't processed in real-time "at the fly", but not for recording/production.
As it is now, it seems like an 8 core Intel Part like the 9900K is where core count meets high frequency.
But if they could go up to 16 cores at the same speed, that would be put into use for a DAW.
Yes, it may be a more fringe usage pattern, but there are actually a lot of people around the world that are making music with the PC as the main equipment these days (controlling it with Midi keyboards/drums and the likes).
DillholeMcRib - Thursday, January 10, 2019 - link
They voted for Hillary? That's my gauge of sanity level: voting for job-killing left wing commiesdoggface - Saturday, January 12, 2019 - link
Name checks out.Whut?
CheapSushi - Thursday, January 10, 2019 - link
They mean 8 cores is enough on Ryzen. If you want more cores & more I/O, that's the purpose of HEDT, Threadripper.Flying Aardvark - Thursday, January 10, 2019 - link
Speak for yourself, for my workloads I can't get enough power. These aren't just for children's glorified Xboxes, where the statement may be true. They're better used for work.close - Friday, January 11, 2019 - link
Then you're looking at the wrong product. Have you ever thought of that? Do you have TBs of RAM in your box? Or 1000s of cores? Do you drive a formula 1 car? Or an 18 wheeler?Whenever someone says "[something] should be enough" they're referring to the vast majority of people unless a specific use case is mentioned. In this case the statement stands, the vast majority of people in the world and even on AT can get by perfectly with a current gen 8 core CPU.
StevoLincolnite - Thursday, January 10, 2019 - link
I still have an 8 year old rig with 6 cores, 12 threads.... And still runs the latest games fine at 1440P, still has years of life left in it still.The real strength of more Cores is not so much if games use all those threads... It's multi-tasking whilst gaming.
hanselltc - Saturday, January 12, 2019 - link
or running several games at once :vOwhan - Monday, January 14, 2019 - link
Me too. Six year old system. A HP z620 with xeon E5-1650 v2, 6 cores, 12 threads. I also use it for audio production, including lots of vsts, dsps. Sometimes, rarely, I have to bounce things around to get perfect performance, but that's far from often and always so late in a project that it doesn't ruin my creative workflow. And I haven't even overclocked it yet.lenghui - Saturday, January 12, 2019 - link
16-core would be awesome because then I can get 8-core for less:)Romulous - Tuesday, January 22, 2019 - link
It's awesome to have choice. I would choose 16 cores if the cost is not crazy. Most likely we'll need a motherboard upgrade for the Ryzen 3000 cpus to correctly support PCI-E 4.Mr Perfect - Wednesday, January 9, 2019 - link
Really? I had the exact opposite reaction. If a normal $300-$500 desktop CPU comes out with the 16 cores that current $1000 HEDT CPUs have, I'd be pretty thrilled.Are you concerned about power consumption, clocks, or something else?
madwolfa - Wednesday, January 9, 2019 - link
At this point, IPC increase and per-core efficiency are more important for AMD than anything else.KateH - Wednesday, January 9, 2019 - link
going too high on the cores on AM4 would risk performance stagnation or regression due to not enough memory channels. IDK if 2 channels would be enough for 12-16 cores unless the datarates are super high.RogerAndOut - Wednesday, January 9, 2019 - link
The debate over cores vs memory channels has been taking place regarding the 32 core Threadripper vs the 32 core epyc. Many of the original claims about there being performance issues are now being put down to issues being found with the Windows scheduler, rather than a narrow memory channel.AMD more likely do not see any need to talk about a 16 core solution until Intel has something that can better what they have already announced.
Eneq - Wednesday, January 9, 2019 - link
Not sure what windows scheduler has with CPU data fetch... can you add a link?SaturnusDK - Wednesday, January 9, 2019 - link
Here Level1techs video proving memory bandwidth is not the issuehttps://www.youtube.com/watch?v=M2LOMTpCtLA
Eneq - Wednesday, January 9, 2019 - link
Ok I see the correlation with the scheduler but to be frank that was with TR4 (i.e. quad channel) and it is still unclear if we would run into bandwidth starvation using 16c in a dual channel AM4 environment.I think it's more likely that they will stop at 12c and that the core chiplet can support 12c
SaturnusDK - Wednesday, January 9, 2019 - link
The point is that the EPYC CPU with 8 memory channels sees the same performance degradation as the 2990WX with 4 memory channels. Both have the same number of cores and threads, we can therefore conclude that memory bandwidth is most likely not a problem except in very few instances where all cores need to read or write from memory at the same time which is incredibly unlikely to happen especially as the cache is doubled with Zen 2.Eneq - Wednesday, January 9, 2019 - link
I don't see that as the conclusion though, the conclusion I get is that the core scheduler can impact memory channel utilization badly. If bandwidth wasn't an issue then why would Epyc use 8 memory channels, the additional cost is detrimental to the chips success.Granted Epyc comes out to 4c per channel which is inline with the 8c AM4 dual channel use case, the additional cache might give us 12c but 16c seems a bit out there imo. But we will see when we get to product launch.
rahvin - Wednesday, January 9, 2019 - link
Then you aren't paying attention to the video or the other available articles. Past a certain workload the windows scheduler starts spending 100% CPU moving threads around instead of doing anything productive. Just bouncing threads from core to core. There's a simple rough fix that causes the whole issue to go away.There always had to be something wrong with windows because Linux never showed the same issue.
twtech - Thursday, January 10, 2019 - link
And MS will fix it. They have to. Intel wants to go the same way as AMD with a chiplet design, so it would be foolish for MS to ignore the issue. I would expect to see some improvement on that front by the end of this year at the latest.Eneq - Wednesday, January 9, 2019 - link
Edit: you are right, memory bandwidth isn't the issue for the performance degradation as discussed in the video but it is still unclear whether bandwidth would be an issue with regards to 16c/32t on a dual channel board.looncraz - Wednesday, January 9, 2019 - link
Dual channel won't be a problem provided latency is managed - which is now the IO chip's job.There will HAVE to be an SRAM of some form on the IO die to buffer, distribute, and collate memory accesses - it might just be 4MiB, but it could be 16MiB or 32MiB... GF has the IP.
In the rare situation that all cores are pulling max bandwidth, they have 3.125GB/s instead 6.25GB/s to chew on with dual channel delivering 50GB/s. However, you will find few cases where a single core can chew through that much data in consumer workloads... and even fewer cases where the memory is fully utilized on a system.
peevee - Thursday, January 10, 2019 - link
"Dual channel won't be a problem provided latency is managed - which is now the IO chip's job."Memory-access latency in current server implementations is pretty much limited by speed of light in the wires. You cannot overcome it unless memory and CPU are close, and stacking only allows for very limited amounts of RAM (but still WAY better than the outdated DIMM arrangement).
twtech - Thursday, January 10, 2019 - link
Eventually MS will have to improve their scheduler to hande NUMA better. Intel is moving toward a chiplet design now as well, so it's pretty much a necessity.lagittaja - Wednesday, January 9, 2019 - link
If you're not running into bandwidth starvation with 32C64T quad channel (vs octa), how are you running into bandwidth starvation with 16C32T dual channel (vs quad)?Eneq - Wednesday, January 9, 2019 - link
Ah right, didn't think it through and forgot the 2990WX which is basically using 8c/channel so it seems 16c in a dual channel environment would be inline with AMDs current design.Cooe - Friday, January 11, 2019 - link
Everybody brain farts :). They're an inherent part of life.nevcairiel - Wednesday, January 9, 2019 - link
Scaling of these things is not necessarily linear.levizx - Thursday, January 10, 2019 - link
32C64T accessing memory all at once is rarer than 16C32T. So it's still more likely to happen.ajc9988 - Wednesday, January 9, 2019 - link
This showed that Epyc with 8 channels was equally performing compared to the 4 channel TR 32 core chip. So, except in certain circumstances, the 16-core mainstream chip should perform as well as the TR 1950/2950X lines.peevee - Thursday, January 10, 2019 - link
You cannot prove a negative statement about a wide range of different things (like all programs with all kinds of internal data states and inputs) unless you have tried all of them.Check out the plateau on 16 cores on 256-bit Threadripper in such prosaic and parallel task as compilation.
ajc9988 - Wednesday, January 9, 2019 - link
I actually think this was just to show 8C parity. Nothing they said precluded higher core count. It was more a marketing move to say don't buy Intel now at over $500 per chip. Instead, wait 6 months and we will give you all the performance you want. And the die clearly showed that the second slot for a die has traces to it (not the pics above, but I saw them while watching the keynote on my TV). That means we should see 12 core and above variants coming soon. But that likely is announced for AMD's 50 year anniversary, like saying look how far mainstream has come in that time, with 16 cores.Rudde - Wednesday, January 9, 2019 - link
I'd like to see a screenshot of the traces, they could reveal loads of fun stuff. Too bad I don't have time to watch the keynote.twtech - Friday, February 8, 2019 - link
The problem with the 2990WX is that some of the cores don't have direct access to memory, hence the "Non-Uniform Memory Access" moniker. Only some of the cores are directly connected to memory, whereas others are not, and have to route their memory requests through another core that is connected.A smart scheduler wouldn't put memory-intensive workloads on those cores that don't have direct memory access - or would at least favor the cores that do - but the Windows scheduler isn't that smart.
Kevin G - Wednesday, January 9, 2019 - link
Except there are already 16 core chips with only two memory channels: Xeon D.https://ark.intel.com/products/93353/Intel-Xeon-Pr...
The memory clock of that chip was relatively low, only 2133 Mhz max in spec.
Chaitanya - Wednesday, January 9, 2019 - link
Most AM4 motherboards even Xx70 based ones have anemic VRMs. Also improving memory compatibility and IPC are things I am looking at before I dump my current 4770 based PC in favour of a 8 core based for content creation.Alistair - Wednesday, January 9, 2019 - link
Most Z370 and Z390 boards have anemic VRMs. Ask me how I know... sigh...deil - Wednesday, January 9, 2019 - link
Well your need is satisfied per 500W Intelripper. I was just about to build something small to fit under TV, and by all looks I can fit a 6/12 little bastard in there without a creative downsizing....I will 100% wait for ryzen 3 to be on market....
beginner99 - Thursday, January 10, 2019 - link
If AMD released 16 cores now, what would they do with ryzen4 series? That will only be a small process refinement. I suspect we get the 12 and 16 core parts with the ryzen4 refresh in Q3 2020. If the release that now, many buyers won't need anything new for probably a decade.SaturnusDK - Thursday, January 10, 2019 - link
That is weird form of logic. Between the 2600K and the 7700K there was 6 years of virtually no real improvements from Intel, yet people still bought and upgraded their products. However, even if we take your claim at face value, that would still mean that people would buy them now, and not an Intel product, so they've achieved exactly what they wanted.Eastman - Thursday, January 10, 2019 - link
It would probably further IPC refinement and tuning. A bit like Ryzen1 and Ryzen2. Ryzen5 would be the next evolution in architecture.FMinus - Wednesday, January 9, 2019 - link
There will be a bump in the final SKUs, 16 should easily be expected, if it is needed on the AM4 platform is a different question.tarqsharq - Wednesday, January 9, 2019 - link
Perhaps an AM4+ with higher power ratings?sing_electric - Wednesday, January 9, 2019 - link
No, no, please no more half sockets. Please, I'm begging you.SaturnusDK - Thursday, January 10, 2019 - link
There's no need for higher power rating. AM4 official supports "up to 140W TDP CPUs", and "up to 560W peak power consumption". There's a lot of head room in the platform already. Board manufacturers have even stated that many of their higher end boards can support PCIe 4.0 already with a simple BIOS update on the closest PCIe slot. You'd still need a new board, probably an x570 or certainly a redesigned lay out, to get PCIe 4.0 to the chipset and NVMe slots though as the routing distance of PCIe 4.0 lanes is only about 165mm before you need signal repeaters.shabby - Thursday, January 10, 2019 - link
How much will this pcie3 > pcie4 bios update cost? Shirley it can't be free... can it?SaturnusDK - Friday, January 11, 2019 - link
A bios update is always free. AMD has always been about open standards and added value whereever possible. There is absolutely no reason to think AMD wouldn't allow board manufacturers to make upgraded bioses available to their costumers, for free obviously, if the board in question can handle it. This is in direct contrast to Intel where it has been proven by board manufacturers and tweakers that have made it happen that z170 and z270 boards could in fact have support both 8th and 9th CPUs with a bios update, yet Intel disallowed it, and requires you to pay more money for superfluous new motherboards.jjj - Wednesday, January 9, 2019 - link
Don't cry too hard, they won't stay at 8 cores but maybe even you can find some joy in the fact that 8 cores would be prices where AMD's 6 cores are today so 180-230$ or about and not Intel's 500$.TheJian - Wednesday, January 9, 2019 - link
I hope not, that will make them NOTHING. I hope $400+. Again, they've lost 1.2B in the last 4yrs, and 9-10B I guess over the life of the company. Meaning NEVER made a dime in their history. People don't seem to grasp that AMD has been broke & in debt their entire life. At what point do you people think they should make a buck for a year or two in a row? For all of 2017 with a ton of new product launches, they made ~45mil. Previous 3 years were ~400mil+ losses. You can't pay for R&D with 45mil...LOL. Time to make a billion a year! NV's R&D is approaching DOUBLE AMD's, due to NET INCOME. You can hate NV all you want, Intel too, but AMD needs to start acting like BOTH of them, or you're basically telling them "give me a cheap chip, I don't care if you go banktrupt AMD". Well, I don't want that to happen :(sing_electric - Wednesday, January 9, 2019 - link
I think Ian's diagram is right, though: That design was made for 2 chiplets. Now, maybe we see some 2x4 chips come out, or maybe 2x6 and never a 2x8, but you don't package things like that otherwise....AlexDaum - Wednesday, January 9, 2019 - link
Maybe it's also for a GPU die in the upcoming APUs? It would make sense to design it as flexible as possible to have the least work to put another InfinityFabric connected chiplet in there and load some other microcode on the I/O die and have it work as an APU.Gasaraki88 - Wednesday, January 9, 2019 - link
Yeah, thank goodness. We don't need 16 core mainstream CPUs.thxne - Wednesday, January 9, 2019 - link
Yes we DO. YOU don't. I DO.nevcairiel - Wednesday, January 9, 2019 - link
You have ThreadRipper if you need more cores. Mainstream should focus on actual mainstream needs, not cheap workstation needs.Fritzkier - Wednesday, January 9, 2019 - link
Why not? Why stop at 8 cores? :)nevcairiel - Wednesday, January 9, 2019 - link
Because there is no such thing as a free lunch. Mainstream/Consumer workloads just don't need an endless amount of cores, and would instead benefit more from a focus on 8c with the best ST performance they can achieve with that, instead of possibly sacrificing ST for more cores. Thats ThreadRipper territory then.twtech - Thursday, January 10, 2019 - link
It's a chicken-and-egg problem. But if enough people have 16+ cores, mainstream software will adapt to start taking advantage of it.iwod - Thursday, January 10, 2019 - link
Every Single one of your reply are similar. Unless you have actually tried to do parallelism programming in general software, and have proved to be successful, otherwise your need for 8 Core+ ( 16 Thread ) for 90% consumers will be negligible in the next 5 years.twtech - Friday, February 8, 2019 - link
Yes, I am a software developer who has successfully written MT code.The primary constraint in MT programming is that at a given time, some data stored in memory can safely either be read by any number of cores simultaneously, or only read-from/written to by a single core. So the code just needs to be written in a way where you don't attempt to do both on the same data at the same time.
Sometimes the answer is as simple as just making a copy of the data, so any threads can read from one const/static copy, while a single thread writes any new updates to the other. Once the update is complete, publish the updated data to become the new read-only copy.
levizx - Thursday, January 10, 2019 - link
Shortsightedness.eldakka - Wednesday, January 9, 2019 - link
If you currently need 16 cores, then by definition you are not a mainstream user, you are a HEDT user. And there are a range of HEDT processors, AMD Threadripper, Intel i9 'X' series, etc.ajc9988 - Wednesday, January 9, 2019 - link
guess what? TR is going to possibly knock the core count up another notch! *BAM*So, if the 16-core variant, and there will be a two Core Die chip coming out this year (whether 12 or 16 cores is up for debate), then the HEDT chips could see a move to do a 64 core chip and make 32 core an entry point at 1/4th the cost of Intel's 48 core behemoth AP chip or the Xeon overclockable 28 core chip, kinda like kicking a guy in the nuts when he is down in the dirt.
nevcairiel - Wednesday, January 9, 2019 - link
They can scale up workstation/HEDT CPUs all they want, but that really doesn't change the fact that mainstream consumers just have no need for more then 8 cores right now. People asking for this are just HEDT users that want a cheaper platform instead. Sales of such CPUs would be minimal.Instead, I wish they don't go down that rabbit hole, and instead make the best 8c CPU they possibly can. No sacrificing ST performance or all-core clocks just to one-up last gens core counts for no reason other then marketing - please!
KOneJ - Wednesday, January 9, 2019 - link
People for years said quad-cores were enough before Ryzen. Yeah, Bulldozer-derivative quad-module octa-int cores sucked, and yeah the 5960X, 6900K, and 6950X were all there, but once Ryzen 7 1(7/8)00(X) launched, followed by Coffee Lake-S, 4 cores became the budget bare-minimum. And 2c/4t was the basis for 15W TDP mobile U-series chips. And same for the 45W mobile SKUs. And Skylake-X/SP versus earlier EP offerings dovetailed EPYC/TR, when people were formerly arguing a lack of need, sensibility, use, and demand. Also, look at ARM and big.little. I don't think they're sacrificing 1T performance for superior nT. PBO and similar really help with that. Higher core-count for equal money and/or equal core-count for less money can only be a good thing.TheinsanegamerN - Wednesday, January 9, 2019 - link
Hell, Quad cores are more then enough! There is not a single game on the market today that is not 100% playable on my quad core 3570k rig. On the ryzen 1700 rig, I rarely see more then 3 cores used much at all.KOneJ - Thursday, January 10, 2019 - link
Hey, I'm still on a 6600K myself. But your 3570K will struggle with background multi-tasking while gaming and CPU encoding while gaming. And while it may be enough now, as soon as the majority of machines in the wild can handle it by having higher core counts, it'll be a wrap. China and other countries jumping on gaming may forestall this some, but it's happening right now. Just look at how core and thread counts have jumped at the budget end including low-TDP mobile chips.Orange_Swan - Monday, January 14, 2019 - link
got an i5-4960k, 16GB RAM and a GTX 1060 6GB and run into MAJOR problems playing Space engineers, it hits CPU & RAM limits every time.next PC if going to 8c/16t minimum and 32GB RAM
twtech - Thursday, January 10, 2019 - link
Imagine if you were talking about software in the early 1980s. "No mainstream software needs even 1MB of RAM." Yes, it would have been true, but things change over time. The presence of 16 core CPUs will help drive the development of software that can make full use of many-core CPUs.KOneJ - Thursday, January 10, 2019 - link
That's precisely it.Ironchef3500 - Thursday, January 10, 2019 - link
+1levizx - Thursday, January 10, 2019 - link
Speak for yourself. You can't stop progress.haukionkannel - Wednesday, January 9, 2019 - link
True!We may afford 8 core chip... 16 core would make this very expensive thing!
Those 7nm Are not cheap now. They will become cheaper in time, but now They Are the newest of the new. When 7nm EV or what ever it will be is released 2020 or even at the end of 2019, this will become cheaper and 16 core at 700-1000$ could be possible. I am happy if we get 8 core at 500$ that is speed of Intel best 8 core... that would be huge! Maybe 8 core will be near 600-700$; but I hope for the less.
jtd871 - Wednesday, January 9, 2019 - link
It won't be that expensive for a few very good reasons: yields will be better than otherwise with smaller chiplets and better yields drives down the cost/chipet even if 7nm wafers are more expensive to process than 14nm. Also, since yields will be better, the binning gets better too.Orange_Swan - Monday, January 14, 2019 - link
actually, there not bad currently,The Ryzen 7 eight-core 2700x 4.35ghz is £350 at Overclockers (UK)
The Ryzen threadripper sixteen core 1950x 4.00ghz is £560 at Overclockers (UK)
60% increase in price for 100% more cores/72% increase in performance in cinebench*
*2604 vs 1782 multicore in cinebench
https://www.cgdirector.com/cinebench-scores-update...
aliquis - Wednesday, January 9, 2019 - link
No, there's absolutely nothing good with that.Of course it's not good for those who need the performance or for prices if the lower end gear.
It could be good for you if you want to hold back development so you don't have an urge to upgrade but ..
Personally the only reason I have the 2600X in the first place is to throw it out vs a 12 core or so chip with better per core performance. If I had kept the 2700X then I wouldn't bother for 15% performance boost and PCI-express 4.
It may be "good enough" for future buyers but it's shit for any of us who wanted progress and hoped for something better.
Hopefully they will put another chiplet there but if they launch this way I assume they can still charge $329 for their 8 core part (beats $599 for Intels ..) and then increase prices for say 12 core to $499 or so and 16 core for $650 or whatever, that scale worse than lineary but anyway .. :D
lightningz71 - Wednesday, January 9, 2019 - link
Why would it scale that badly? The leaked ROME engineering samples showed 16MB of L3 cache per CCX. That's twice summit/pinnacle ridge L3 sizes. That 12 core, two chiplet Ryzen 3xxx chip would likely have 4 x 3 core CCX units with a total of 64MB of L3 cache. It could clock for days, stay in the existing AM4 power envelope, and stay well fed with data! I MIGHT be concerned with a 16 core chip hitting high sustained all core clocks, but, data starvation is not something I'm worried about.haukionkannel - Thursday, January 10, 2019 - link
He means price scaling :)More cores is good but at this moment Intel has nothing to compete with AMD 16 core versions, so those would be higher margin products. In 8 core there is competition (if intel reduce prices) If intel does not reduce prices AMD don't have to neither, because they already have cheaper CPU and now it is getting better, so there is room to increase the price if needed.
But we will see it in the next autumn when these gets to the shops! Hopefully...
twtech - Thursday, January 10, 2019 - link
Based on the bottom picture, I'd count on that core bump coming. Just a question of when, really - that off-center positioning that only becomes balanced with a 2nd die really doesn't seem like it could be any sort of accident or coincidence.Eastman - Thursday, January 10, 2019 - link
No problem with 8 but there should be an option for 16 for people who wants it. I build only ITX systems to use in my job and the more cores the better in a small package. Intel X299 ecosystem was too rich for my blood.Lolimaster - Saturday, January 12, 2019 - link
Encoders and video editors would drool at 16 cores for mainstream, they don't really need quad channel or 64pci-e lanes for those tasks.Gondalf - Sunday, January 13, 2019 - link
Still i am worried about the absence of any mention to 7nm mobile SKUs in AMD keynote. Fast cpus are nice but the revenue is low, mobile is a far larger market that accout the bulk of intel revenue in Pc space. With the conquer of 7nm AMD should be fully focused to do a dent in laptop space instead to insist in the dying high power segment.Honestly i am surprised.
twtech - Friday, February 8, 2019 - link
Why would you be glad to see that? I'd like to see as many cores as possible get into the mainstream, so the impetus to make fully multithreaded software is maximized for software developers.With just a few cores being standard, it still doesn't matter that much - multithreading might not make up for the initial losses in the form of extra memory usage and reduced efficiency associated with writing multithreaded code.
But those losses are more or less fixed-cost, so if the average desktop PC has 16, 32 cores, that's a fundamentally different scenario.
konroh77 - Wednesday, January 9, 2019 - link
8 core APU? Second chiplet would do nicely for graphics.KateH - Wednesday, January 9, 2019 - link
i presume that's the plan! there's plenty of space leftover, but the memory bandwidth with dual-channel DDR4 coupled to a big GPU is doing me a concern :/ I wonder how high AMD can go on APU graphics cores before mem. bandwidth starts diminishing returns?sing_electric - Wednesday, January 9, 2019 - link
I think they're already there, when you look at how the performance of Ryzen APUs scales with memory. The returns are diminishing, but not entirely gone. Having said that, right now AMD's likely not feeling the need to increase APU performance too much given that Intel isn't really competing.I still think AMD might try to combine IO and APU on a chiplet, though, particularly since they've already laid out Vega on GloFo's 12nm libraries. The IO part would shrink, since you need less of it, and could get by with PCIe 3.0, etc.
lightningz71 - Wednesday, January 9, 2019 - link
Maybe when TSMC 7nm volume increases, they can introduce a 7nm I/O die with a Vega 11 module?jtd871 - Wednesday, January 9, 2019 - link
Remember these will support PCIe 4. So more throughput per PCIe lane.AlexDaum - Wednesday, January 9, 2019 - link
The PCIe speed does not really matter if the Vega chiplet would be connected directly to the InfinityFabric (which would make far more sense imho) but the real problem is memory bandwidth...There is a reason why Vega is using HBM memory with far more bandwidth than DDR4. And I don't see a way they could fit even a small HBM stack in there, assuming the Vega chiplet is as big as a zen chiplet
sing_electric - Thursday, January 10, 2019 - link
It's worth saying that 'Vega' is a marketing term as much as anything. I think the comment was referring to a Vega module like we already see on APUs like the Ryzen 2400G, which uses system DDR4 memory. On the other end of things is the "Vega" in Intel's Kaby Lake-G parts, which does have HBM2 memory, but is basically Polaris otherwise (rapid packed math, etc.).dgingeri - Wednesday, January 9, 2019 - link
A shrink to 7nm for the mem controller, PCIe controller, and other IO items wouldn't pay off. It would shrink them maybe about 10% and wouldn't reduce the power they use, which wouldn't offset the added cost of the shrink. (That's in the AdoredTV video on AMD's chiplets.) We MIGHT see them put into an active interposer underneath the CPU cores, though. That depends on what tech they develop for it. I think Intel is already working on that.iwod - Thursday, January 10, 2019 - link
They are likely going to stick to GF for I/O. And may be moving to 12nm FD-SOI.AlexDaum - Wednesday, January 9, 2019 - link
They also have Vega on TSMCs 7nm libraries so thats not a concern, also the 7nm Vega has the shader intrinsics and rapid packed math fixed, so I would think they put the newer part in there.colinisation - Wednesday, January 9, 2019 - link
A little surprised the memory controller is on the IO die and not on the chiplet.It seemed that the whole industry pivoted to minimising CPU latency to main memory and now it seems like a step back.
KateH - Wednesday, January 9, 2019 - link
presumably, the distance from the IO die to x86 compute chiplet is low enough that latency isn't notuceably affected. Memory controller tightly-integrated on-package is still going to be far lower latency than the old Northbridge arrangementMrCommunistGen - Wednesday, January 9, 2019 - link
When you have memory controllers on separate CPU dies, then when one CPU needs to access memory that is connected to a different die there is a pretty large latency penalty and it makes memory access very non-linear.The chiplet design with a centralized I/O controller makes memory accesses more consistent.
On a Ryzen CPU with only 1 CPU chiplet this may not be the fastest way to design the chip, but if they're doing modular CPU design it saves them from having to design 2 different CPUs, 1 with and another without a memory controller.
Plus having the I/O hub as part of the design allows for adding another CPU or GPU chiplet to the package without having to rearchitect memory and I/O.
Overall makes pretty good sense to me.
MrCommunistGen - Wednesday, January 9, 2019 - link
Hmm... doing some back of the napkin math... it does look like AMD has enough space for a appropriately powerful GPU. Initially I had my doubts which is why I started trying to figure it out.Based on Ian's math for the CPU chiplet size, we're looking at ~80mm^2. Assuming that TSMC 7nm is actually double the density of GF 14nm (if the actual scaling is known someone let me know - I don't know it offhand) and that they won't need memory controllers in the GPU (because they'll be in the I/O hub), then that should comfortably give enough room for an RX 560 levels of compute, maybe with a decent chunk of cache on the GPU die to help with bandwidth constraints...
rahvin - Wednesday, January 9, 2019 - link
There's no way they could put one that big on there, the heat would overwhelm that 40mm die.PixyMisa - Wednesday, January 9, 2019 - link
Possibly 16 CUs but clocked lower than the 560, since it will be bandwidth limited anyway.KOneJ - Wednesday, January 9, 2019 - link
And there's the limiting factor without HBM or some other memory architecture for on-package SoC-style iGPUs from AMD... bandwidth limitations. They're coming. People forget how Zen slides promised 5W TDP chips and GPU+CPU EPYC (IK about embedded...). It's all in the works, I'd guess.MrCommunistGen - Thursday, January 10, 2019 - link
In terms of functional units, RX 560 at 1024 Stream Processors across 16CUs isn't that much bigger than the 704 Stream Processors across 11CUs in a 2400G. With the shrink to 7nm power should come down nicely too.I think they have both the thermal and package-area budget for something in the range of 11 to 16 CUs. Maybe they'll build a 16CU GPU and only enable 14CUs to account for yields and keep power in check. That leaves room for enough of a GPU performance gain over the previous generation to be compelling.
As I'm sure others have said and will say, AMD is probably running up against the ceiling of what they can accomplish with on-package graphics without adding memory channels, moving to next gen DDR for the whole APU package, having on-package HBM, or adding a significant cache a la Crystal Well for Intel.
brakdoo - Wednesday, January 9, 2019 - link
The DRAM latency will always be bad. it's more important to have low cache latency but I'm not sure whether the L3$ or big L2$ are on the chiplet or the IO-chips...AlexDaum - Wednesday, January 9, 2019 - link
L1 and L2 are typically core local, so they will be on the chiplet for sure, and I am also pretty sure they put L3$ on the chiplet to, because the same chiplets are used on epyc and without a pretty big cache you could run into infinity fabric bandwidth problems for cache access from all chiplets.Maybe there is a second shared L3 or L4$ on the I/O hub? Some cache will be there for sure to buffer InfinityFabric and DRAM access, but they could put quite a big cache on there and use it as a L4$ victim cache, so that if 2 chiplets need the same data from DRAM that data is already in the I/O L4$ after the first read and you save the extra jump to DRAM. But that cache would be far less important on Ryzen where there is only one die
HStewart - Wednesday, January 9, 2019 - link
yes this is extremely surprising, in pre intel I series, this was the major advantage that AMD had over Intel. I hope for AMD stake this is a typo. Only thing I can think of it was more important to AMD to put the GPU on the chip then the memory control but ran in to difficulties putting memory controller on 7nm process.What comes to mind as solutions is Intel EMiB and similar - which allows different components of different die process on same die - even different manufactures like 8705g on my XPS 15 2in1
looncraz - Wednesday, January 9, 2019 - link
Point to point IFOP latency should be reasonably low. 5ns low. If the IMC is improved a little we might break even (or even improve) on latency.KOneJ - Wednesday, January 9, 2019 - link
Latency should be more linear and homogenized than Zen/Zen+ MCM designs. I don't see how near-latency isn't wrecked going out to main memory without sorting out far-latency, so there's got to be creative workarounds implemented there. I agree that Zen 2 DRAM latency may be better than some fear since clock domains, IF, the I/O die, and MCs may have more well-considered compromises than people have been accounting for. That opening on the package has got to be for a second die. Doesn't make sense otherwise. Minimizing trace-lengths, or maximizing heat dispersion would leave the layout bi-symmetrical or corner-to-corner. I'm just curious and confused why the I/O die for Matisse is so large compared to the features in Rome. Maybe it's for redundancy with yields... but 14nm yields were excellent and S/P Ridge didn't even utilize full PCIe lanes. I also doubt an L4 cache. Maybe this is necessary to maintain socket backwards-compatibility with both PCIe3 and PCIe4 on the I/O die? Only time will tell.looncraz - Saturday, January 12, 2019 - link
In order to service 16 cores I would expect SRAM to be present to buffer memory accesses. It might just be 2~4MiB, but it's pretty much going to be required.The die is a good 30mm^2 larger than needed, which is enough room for some L4, but we also don't know how large PCI-e 4.0 is nor the additional die space required for other features.
Given that Lisa Su verified the die is a unique die for Ryzen, it only makes sense that it doesn't have a bunch useless server bits on it like earlier models.
KOneJ - Saturday, January 12, 2019 - link
I could see a small L4, but not a large one. You're correct that it would conserve power and bandwidth by buffering memory accesses, but it's not necessary per se. I would've expected the Ryzen I/O die to be a bit smaller versus Rome's, so there's definitely that. Although Rome's need for L4 would be at least as great proportionally as Matisse's if needed so clearly at all. I don't think an L4 is likely, though it is possible. It may be an idea for a future Zen derivative as well. I'd say that's definitely something being considered if nothing else, but at what cost and how to implement effectively?looncraz - Tuesday, January 15, 2019 - link
There's potentially room for about 16MiB of L4, but that's making a LOT of assumptions about what else is on the die and the density of the L4 (just straight up using the L3 as a reference for 16MiB).The most valuable buffer could be a write coalescing buffer as it could keep the infinity fabric from backing up, thus allowing higher burst speeds. With four CCXes issuing writes at a potential rate of 50~100GB/s there will be a real need for a buffer to handle write bursts.
levizx - Thursday, January 10, 2019 - link
How are you even surprised? Epyc chiplet/IO die told you nothing? They are not stupid enough to design 2 different IO subsystems requiring 2 different 7nm cores.CajunArson - Wednesday, January 9, 2019 - link
That's it? Even AMD's own propaganda doesn't put the MIRACLE RyZen 2 ahead of last year's 9900K... you know the chip that the AMD fansquad insulted as obsolete in 2018?Oh, and insult it all you want the the IGP in the 9900K is literally infinitely faster than the non-existent integrated graphics that AMD couldn't be arsed to put in it's miracle chip even though Lisa Su gave the usual 10 minute copy-n-past screed about "heterogenous computing".
DrKlahn - Wednesday, January 9, 2019 - link
Yeah that's it. A chip that takes much less power, is likely to cost hundreds less and matches Intel's best. What a bummer /sThere will be variants with IGP if you really want one too, they just didn't preview them. Have fun overpaying your corporate sweetheart.
CajunArson - Wednesday, January 9, 2019 - link
1. No AMD fantard is ever EVER allowed to claim that power consumption on the desktop is somehow vital after we've had to sit through the last decade of B.S. about how Bulldozer "is really pretty good" and how the abomination of the PCIe non-compliant RX 480 and the power-vacuum Vega 64 are "really good!"2. Who says that in Q3 these CPUs are somehow going to be dirt cheap? TSMC isn't a charity and AMD has to buy the most expensive silicon from them PLUS pay GloFo for the northbridge that they can't seem to get integrated into their "miracle" chiplet even in a consumer product.
DrKlahn - Wednesday, January 9, 2019 - link
1. Where is the Intel Fantard rulebook you're using so we can communicate properly? I don't see anyone mentioning Bulldozer being good, just you being a corporate cheerleader.2. No one. I said it's likely to cost much less based on what we know of the design philosophy and estimated costs floating around. This multi die solution has very obvious cost savings vs. Intel's monolithic die approach (which is why Intel is moving towards this solution itself).
Mikewind Dale - Wednesday, January 9, 2019 - link
Sometimes, I wonder why political disputes have to be so violent, and why mankind is so prone to war. Then I see that some people start foaming at the mouths because they don't like another company's CPU chip - when they're free to buy the one they want, and no one is forcing them to do anything they don't want to do!! Sigh. War: war never changes.DrKlahn - Wednesday, January 9, 2019 - link
Some people get invested in Corporations like they do sports teams. AMD having a good product doesn't make Intel's suddenly bad (and vice versa). Ryzen is the first AMD product I've bought in some time because it represents an excellent value/performance proposition. If Intel fits my needs better the next time I'm buying something, they'll get my money.It's hard not to respond to posts like this because they are so obviously based on emotional investment and not in the reality of the information presented. Even if you have interests in Intel you should want active competition to move the market forward.
Alistair - Wednesday, January 9, 2019 - link
I know right? Just don't communicate with anyone who can't use appropriate language to you. You shouldn't have replied to Cajun anyways, he's a nobody.jjj - Wednesday, January 9, 2019 - link
lol rabid Intel fanboy having a meltdown because AMD has again twice the cores at same price but this time around they also got the single core perf and clocks to match Intel.As for GPU, who said that AMD does not have 6 and 8 cores APUs with a GPU that is a few times faster than Intel's and ofc again half of Intel's price.
Do please seek medication, sane humans to not have feelings for brands.
HStewart - Wednesday, January 9, 2019 - link
you are trying to compare last years Intel vs 2h 2019 AMDLets see how it fans out at end of year - right now anything from both AMD and Intel are both speculation. But my personal better is on Ice Lake Sunny Cove
It is not core count that matter but the core architexture. 2019 seriously changes that I would bet that 4 Core Sunny Cove base CPU could be a 8 core Zen 2 based computer any day.
HStewart - Wednesday, January 9, 2019 - link
EDIT: Personal BetDrKlahn - Wednesday, January 9, 2019 - link
Sunny Cove looks very promising, but I don't think we've seen working silicon. I HOPE Intel delivers on it this year, but with the execution problems plaguing them lately I'm not confident here.If Sunny Cove is the big improvement we're being told it is, then we should see Intel comfortably ahead. I'm not as optimistic as you are about 1 SC core = 2 Zen 2 cores in most workloads, but I could see some very big leads in many use cases. Which will almost certainly prompt AMD to answer back. And we, the consumer, are the winner :D
Tamz_msc - Wednesday, January 9, 2019 - link
You expect double the IPC from a moderate architectural change?KOneJ - Wednesday, January 9, 2019 - link
Yeah, it doesn't make sense. HStewart is crazy. From SB to SKL, Intel widened the execution ports progressively. Now it'll deeper and wider with SC/IL. Should bring a few percent, but no doubling. The 2c to 1c comparison is meaningless babble due to thread scaling and programability. Whether discussing Amadahl's law (https://en.wikipedia.org/wiki/Amdahl%27s_law) or compiler optimizations, ISXs, and APIs, there is no simplification that accurately encompasses this issue. That remark sounds like a gamer talking about the weakness of BD-derivatives. I think SC should be a nice bump, but I can also see AMD deepening and widening the Zen core easily as well. Between the MCM approach, AM4 phasing out, DDR5 coming (Maybe PCIe4 being short-lived yielding to 5 sooner than expected), and how Zen was a comparatively small core from a transistor-count and die-area (Even with discrepancies between 14nmLPP versus Intel's 14nm node) perspective versus SKL derivatives, it's easy to see the Zen core become beefier. Also, Zen's core power efficiency is much better than Intel's (Not talking about uncore topologies). agner.org provides excellent historical context and perspective. See https://www.agner.org/optimize/microarchitecture.p...Arbie - Friday, January 11, 2019 - link
You're in the wrong place, Cajun. The mindlessly insulting trolling is over on WccfTech. Give that a try - and maybe never come back here.looncraz - Wednesday, January 9, 2019 - link
It was faster... and used only 2/3 the power.Lisa isn't like previous presenters, she usually doesn't over hype.
A 75W 8-core CPU likely means the thing is running at pretty reasonable clocks - we just saw the IPC gains and any SMT improvements. 15~17%.
A 5GHz 9900k hits 2150~2200, just 7% ahead... but how much more can be achieved by pushing Ryzen 3000? I'd bet it's more than 7%.
The IO die and chiplet position also only makes sense if there will be 12 & 16 core parts.
DrKlahn - Wednesday, January 9, 2019 - link
Or they may only put in an IGP there. 12/16 core only make sense if AM4 can feed that load. I'm guessing it probably can with DDR4 speeds continuing to climb, but it may be a factor and I'm sure AMD has the numbers. As far as frequency and scaling, I think you're probably right. Validation samples (especially ones used at high profile presentations) are likely to be conservatively clocked. Headroom should at least reach 4.5GHz based on what we saw with the 2xxx refresh from AMD. 5GHz is possible, but might be a stretch. We should see soon enough.KOneJ - Wednesday, January 9, 2019 - link
IDK. There's an AWFUL LOT of symmetry on that package. 2 CPU dies seems awful likely. Also see https://twitter.com/IanCutress/status/108309908688... . Also take into account TSMC's 16nmFF power-frequency behavior versus Samsung's 14nmLPP when used in GP Pascal-based dies. TSMC's 7nm may do better than people think versus 12/14nm GF processes, between which there were 300MHz. I'd personally guess that 4.5GHz is conservative when you look at that and the 2950X's boosting. And architectural choices also contribute to the frequency tolerance of a design, not only the process. Zen 2 surely took that into consideration.twtech - Thursday, January 10, 2019 - link
I would much rather see more cores than an iGPU. With a properly-written Windows scheduler, and software designed to take advantage of the hardware, it will work. Don't hold back the hardware because the software isn't there yet - the software may not get there until the hardware is available.KOneJ - Thursday, January 10, 2019 - link
Or have everyone jump to Linux. And I think the most progress happens when hardware and software move in tandem. Look at GPUs. Specialized FF units were often built-in but never implemented or utilized. A total shame and waste.1_rick - Wednesday, January 9, 2019 - link
"The IO die and chiplet position also only makes sense if there will be 12 & 16 core parts."Or APUs. That other section could take a slice o' Vega cores.
Dodozoid - Thursday, January 10, 2019 - link
Have you considered a possibility there might be some small GPU on the unusually big I/O die?It's much bigger than Rome I/O suggests and I doubt it's all cache.
nevcairiel - Wednesday, January 9, 2019 - link
Its on a brand new process, if it wouldn't use less power that would be the real tragedy (like Radeon 7).Personally, I did hope for more then just catching up to Intels performance, even if its cheaper and less power, but what I'm ultimately interested in is performance. But of course there is still half a year to go, so we'll see where it really ends up standing when it releases.
KOneJ - Wednesday, January 9, 2019 - link
People also forget the clock-to-clock comparison of Zen to 6900K with the ES at 3.4 with the 1800X at 3.6 base. The retail chip will be even better.Tamz_msc - Wednesday, January 9, 2019 - link
Lol, last year was less than a month back. Also, these aren't finalized clocks, and there's clearly room enough for a second chiplet.tarqsharq - Wednesday, January 9, 2019 - link
Clocks, BIOS tweaks, microcode tweaks, all sorts of things.Look at the improvements we've seen with BIOS from Ryzen launch to the latest AGESA's! We're looking at a chiplet design that's not even at launch yet, who knows what they need to iron out still that they're playing safe for now to make sure it doesn't crash during the presentation... including probably running the voltage high to ensure stability.
sing_electric - Wednesday, January 9, 2019 - link
I wouldn't read too much into that demo, either way: AMD had to balance getting the right numbers with the risk of a crash on pre-release silicon.bji - Wednesday, January 9, 2019 - link
You are the worst kind of consumer. The kind whose identity is apparently wrapped up in one company versus another. Your comments are useless. Please stop posting them.Drumsticks - Wednesday, January 9, 2019 - link
Things are going to get very exciting, very quickly.I wonder if Intel will find a way to pull in Icelake.
psychobriggsy - Wednesday, January 9, 2019 - link
TBH 8C is fine on AM4 this year.But that layout is clearly set up for a 16C solution, or a CPU + Small GPU solution.
Kevin G - Wednesday, January 9, 2019 - link
Rotate the CPU chiplets by 90 degrees and it looks like three of them can be squeezed into the same package with the IO die. This of course presumes that the IO die has the on package links for all of them already.KOneJ - Wednesday, January 9, 2019 - link
That's just bad math. What someone needs to do is analyze the gap measurement between Ian's 2 die mock-up and Rome package shots. And 24c on mainstream would encroach too much into next-gen TR territory without bringing enough extra fight to Intel. Not even to mention power requirements, symmetry, space for surface package components, and the offset.twtech - Thursday, January 10, 2019 - link
More likely you would get a bigger chip with 2 more chiplets mirrored on the other side, that occupies a bigger socket. That seems like the logical solution for TR3.KOneJ - Thursday, January 10, 2019 - link
I think TR3 will be based on Rome. Unlike 1st/2nd gen. TR though, I suspect we may see units without all of the EPYC dies. For example, there could easily be both 5 and 9 die TR configurations. But this depends on cache considerations, data feeding structures, and silicon harvesting.KOneJ - Thursday, January 10, 2019 - link
Also, I think AMD wants to push past the 32-core 2990WX, if possible, for the right price of course... not to mention the power-efficiency gains won't likely go to all-core frequency of these heavily-threaded chips. Not in this age of core steppings and turbo states. A halo chip is good for marketing, costs little to develop this diversified option when SP3 and TR4 are a common socket layout, and easy to do.Messican - Wednesday, January 9, 2019 - link
At the presentation :Ryzen 3 scored 2057 and 2040 for Intel at cinebench.
SaturnusDK - Wednesday, January 9, 2019 - link
Pretty sure it was the Ryzen 5 meant to be paired with a GPU chiplet she showed but time will tell. Obviously it was an early engineering sample as you'd not normally see unsymmetrical CPU designs in a finished product. There certainly is room for another core chiplet or a rather beefy Vega GPU.shabby - Wednesday, January 9, 2019 - link
135watt ryzen 3... lol oksilverblue - Wednesday, January 9, 2019 - link
Consumption of entire system, no?SaturnusDK - Wednesday, January 9, 2019 - link
Yup. So 65-75W for the actual CPU at full load compared to the I9 at 115-125W. Pretty darn impressive when you consider it's not final silicon and clock speeds, and it actually was a shade faster.hetzbh - Wednesday, January 9, 2019 - link
You might need to edit your post. The video shows (1:28:53) that the Ryzen Cinebench score was *2057* on the Ryzen, and 2040 on the Intel side.Ian Cutress - Thursday, January 10, 2019 - link
We had a pre-briefing and the scores I published were the ones we saw during that prebriefing.Dragonrider - Wednesday, January 9, 2019 - link
Of course there will be a 16 core. The layout is there. The power profile is there. This is a teaser-- "See, we can match a 9900k with only half a processor". Two possible reasons for not showing the full 16 core layout. 1. It's not ready. 2. It really isn't twice as fast by quite a bit due to memory bandwidth limitations with only two channels. Clearly a 16 core Treadripper will outperform. The sweet spot with this layout may be two cut back chiplets in a 12 core configuration (i.e. more cache BW per core and just about the limit of two channels usefulness). Also, depending on the actual release date, they could go for DDR5 compatibility along with pcie 4.Mikewind Dale - Wednesday, January 9, 2019 - link
Or with the separate IO chiplet, I wonder if the plan is to later support DDR5 by simply replacing the IO chiplet with a different one?Kevin G - Wednesday, January 9, 2019 - link
Both yes and no.AMD's cadence would imply the Zen 3 is coming next year. If DDR5 is ready for mass production which we will likely see is both Zen 3 chiplets with this IO die for AM4 and a new IO die + Zen 3 chiplets for a new AM5 socket.
The more interesting question is if this same IO die will be used to put a Navi GPU into the same package alongside some HBM.
KOneJ - Wednesday, January 9, 2019 - link
I'd say DDR5 is more slated for Zen 4 because of challenges in maintaining backwards-compatibility on AM4. Maybe shrinking and shifting the I/O die would allow for on-package HBM... I haven't checked the DDR5 standards, and while I remember both DDR2/3 support on Phenoms back in the day in a very pro-consumer move by AMD, I don't see it happening this go around.Kevin G - Wednesday, January 9, 2019 - link
DDR5 support would just mean a socket change to the hypothetical AM5 socket and require a new IO die. The CPU chiplets wouldn't inherently have to change though, hence why Zen 3 in 2020 could easily bridge both memory types as there would be two different sockets/IO dies they would connect to.The development between IO and CPU chiplets is now disjointed and can proceed and their own individual paces based upon market demand. For this same reason, I strongly suspect the Zen 3 chiplets due next year will leverage the exact same IO die we are seeing used today.
KOneJ - Thursday, January 10, 2019 - link
Mark Papermaster suggested Zen 3 would bring opportunistic efficiency gains, indicating otherwise, Also, AM4 is a promised 4-year platform: 2017(1), 2018(2), 2019(3), 2020(4). They could have two overlapping sockets, but the product confusion for consumers and the high initial cost of new RAM types would probably outweigh the benefits. Recall how much DDR3/DDR4 cost when they were first brought to market.Kevin G - Thursday, January 10, 2019 - link
Zen 3 would be a 2020 part so they'd still be honoring their commit to AM4 without issue.You forget that AMD did pull off two sockets simultaneously before in the past: AM2+ and AM3. The first Phenom AM3 chips would work fine in AM2+ sockets.
Considering AMD's current chiplet strategy and past history, I don't see much of an issue for them to introduce AM5 at the tail end of 2020 with Zen 3 and upgrade it to Zen 4 in 2021. If DDR5 prices remain prohibitally expensive through 2021, they could again do a simultaneous release of Zen4 on socket AM4 and AM5 (though I don't consider this likely). Moving to AM5 would also permit AMD to resize the socket if they wanted to so they could include more and/or larger dies. Increased core count or features is an easy means of differentiating AM4 and AM5 products.
KOneJ - Thursday, January 10, 2019 - link
I did not forget that. I mentioned the backwards compatibility with DDR2/3 here: https://www.anandtech.com/comments/13829/amd-ryzen... . Given some context with SP3 server cadence, socket pin count utilization, DDR5 and PCIe5 generational timing, development of their "next-gen" GPU post-Navi, HBM3 and LCHBM, as well as Gen-Z, OpenCAPI, and TSMC's 7nm EUV HVM, a hard split between AM4/5 between Zen4/5 makes way too much sense with timing. Intel's Aurora delivery shows a focus on parallel data HPC that goes with their dGPU push in 2020/2021 and Mark Papermaster in an interview relayed with Ian Cutress:"IC: ...Can you make the same commitment with Zen 4 that was shown on the roadmap slides?
MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change.
IC: So one might assume that an intercept might occur with Zen 4?
MP: No comment (!)".
Interview @ https://www.anandtech.com/show/13578/naples-rome-m...
He also told EETimes that Zen 3 CPUs would offer only “primarily leverage efficiency with some modest device performance opportunities”
Papermaster’s sentiment hints at an approach with Zen 3 that’s not all that dissimilar to Zen+, especially when taken with how James prior said "It’s not an area statement, it’s a power efficiency statement,” with regards to the move to 12nm with Ryzen.
EETimes Reference @ https://www.eetimes.com/document.asp?doc_id=133399...
Also: https://www.pcgamesn.com/amd-zen-3-7nm-cpu-archite...
All evidence would seem to indicate that your expectations for the AM4/5 transition are misplaced.
Kevin G - Friday, January 11, 2019 - link
AMD played it wisely with the AM2 to AM3 transition as DDR3 price took awhile to fall to reach DDR2 levels. DDR4 prices are still inflated to the previous generation DDR3 and DDR5 is expected to start off more expensive than DDR4 is now. Yes, Mark is correct that a transition will need to happen but AMD's current strategy permits them to operate at their leisure to pick an optimal time frame: the CPU side isn't going to be delayed due to troubles of DDR5 deployment.Also the quotes you cite hint more about the socket transition but they don't hint at what chiplet would be used. In otherwords, MP is referring more to the IO chip than anything else. They are are two separate entities now with different road maps now.
KOneJ - Saturday, January 12, 2019 - link
Agree to disagree on their strategy. Time will tell. :DKOneJ - Saturday, January 12, 2019 - link
Correction: AM4/5 between Zen3/4AlexDaum - Wednesday, January 9, 2019 - link
The problem with DDR5 is, that it's not backwards compatible, so you would need new motherboards. But AMD said, that the new Ryzen 3 CPUs can be used in any existing AM4 motherboard, so I'd guess there will be no DDR5 supportporcupineLTD - Wednesday, January 9, 2019 - link
Is there any reasoning for the asymmetrical positioning other than space for a second chiplet?DrKlahn - Wednesday, January 9, 2019 - link
At the very least they will put an IGP in some SKUs on the desktop side and this space will be used for it. They may also opt for a another CPU chiplet as you're speculatingdeathBOB - Wednesday, January 9, 2019 - link
Is there anything to be made of the use of “system power” vs a cpu power measurement?DrKlahn - Wednesday, January 9, 2019 - link
Since both companies use very different TDP measuring methods I'd imagine they used that measurement to cut through any marketing speak confusion.wurizen - Wednesday, January 9, 2019 - link
How come no one in these tech briefings and tech conferences talks more about AMD's Infinity Fabric and how it has high memory latency penalty issues?Kevin G - Wednesday, January 9, 2019 - link
Because no one has these next chips in their testing labs.And this isn't the first time two separate dies were leveraged for a memory controller (IO die) and CPU die: Intel did this nearly a decade ago with Clarkdale on socket 1156. Memory performance there compared to Lynnfield was poor as this setup still had a (then) traditional FSB setup but entirely in-package.
AMD's link between the dies is far higher bandwidth from all indications so that aspect should not suffer. The impact to memory latency is going to be the big question on desktop. For server though, average latency should see an improvement due to consolidation of all the NUMA nodes across multiple dies, though minimums should increase a bit.
wurizen - Wednesday, January 9, 2019 - link
@Kevin G, Right. Yeah, we know it's not released, yet. But, there's no mention of "Infinity Fabric is faster," or something like, high latency issue with Infinity Fabric is being addressed or something like that.Dodozoid - Thursday, January 10, 2019 - link
They talked about improved IF during Rome Epyc reveal.KOneJ - Friday, January 11, 2019 - link
They did, but they're definitely aware of the latency dynamic. As evidenced by an interview @ https://www.anandtech.com/show/13578/naples-rome-m...IC: Do the chiplets communicate with each other directly, or is all communication through the IO die?
MP: What we have is an IF link from each CPU chiplet to the IO die.
IC: When one core wants to access the cache of another core, it could have two latencies: when both cores are on the same chiplet, and when the cores are on different chiplets. How is that managed with a potentially bifurcated latency?
MP: I think you’re trying to reconstruct the detailed diagrams that we’ll show you at the product announcement!
IC: Under the situation where we now have a uniform main memory architecture, for on-chip compared to chip-to-chip there is still a near and a far latency…
MP: I know exactly where you’re going and as always with AnandTech it’s the right question! I can honestly say that we’ll share this info with the full product announcement.
jjj - Wednesday, January 9, 2019 - link
The 2700x would need some 4.6GHz in Cinebench to match the 9900k isn't it?So same significant clock for clock gains would allow AMD to compete without very high clocks. The power numbers do suggest that clocks have room to go up a bit so that's good.
The dual die approach, let's see latency and let's see what kind of APUs we get.
Looking good though, with IO die approach they can do lots of IO so we escape silly PCIe limitations they can do 16 cores at 500$ or less, they can do big APUs - hopefully with more memory channels so new mobos. As long as somehow memory latency isn't high but not quite sure how they would do that.
AlexDaum - Wednesday, January 9, 2019 - link
It would not neccessarily need a high clock to match the i9.We know that zen 2 has double the FPUs and 6µOP/cycle dispatch, if I remember correctly 4 of those can be FPU/AVX (2 ADD/ 2 MUL/FMA) or 4 ALU or 2 AGU. As far as I know Cinebench is pretty FPU heavy, so say it can do one AVX op and an AGU for memory access before hitting dependencies, then SMT could be very effective, because only half of the AVX unity would be used by one thread, and there is still enough dispatch bandwidth available.
But I'm no expert in CPU design so I could be really wrong here, just a speculation.
Kevin G - Friday, January 11, 2019 - link
The real question is if Zen 2 takes a clock speed penalty like some of Intel's chips do when running AVX code. So far AMD has hinted at 'no' but that was in the context of base clock, not turbo. If we take AMD at their word instead of a grain of salt, the question changes to what turbo frequencies can Zen 2 maintain while running full width AVX2 code vs. SSE?brakdoo - Wednesday, January 9, 2019 - link
Ryzen 2 scores 2057 in the vid at 133.X watts. Did you get your numbers from AMD?maroon1 - Wednesday, January 9, 2019 - link
7nm Ryzen compete with i9 9900K ??? And in Cinebench which is known to run better on AMD ryzen ?! I mean if Ryzen is equal in cinebench, then 9900K is probably faster overallWhat a big joke. Why the hell desktop should care about power consumption, it is not laptop. Performance is what matter for high-end users.
ishould - Wednesday, January 9, 2019 - link
This could be looked at as an estimate for how much power Rome will use; Data centers care a lot about power efficiency. Also it shows that at the same power consumption as Intel, they should beat the 9900k by a large margincheshirster - Wednesday, January 9, 2019 - link
This was probably a Ryzen 5 3600.KOneJ - Wednesday, January 9, 2019 - link
I'd say that's a fair guess, but it's an ES @ est. 75W TDP, with different tuning based on thread-loads, so I don't think this particular config will ever come to retail. But it's probably pretty close.TheinsanegamerN - Wednesday, January 9, 2019 - link
Those with overheating 9900ks care a whole hell of a lot about power consumption being too high. Lower TDP+more power headroom, easier cooling, ece.Mikewind Dale - Wednesday, January 9, 2019 - link
I'd like to know how many PCIe 3.0 lanes. It's rather frustrating with a mainstream CPU+mobo to be told that you have only two M.2 sockets, and one of them is only PCIe 2.0, and that if you use one of them, you lose a PCIe slot, etc. I'd like to see enough PCI 3.0 lanes to actually support all the PCIe slots and M.2 sockets on an ATX motherboard.SaturnusDK - Wednesday, January 9, 2019 - link
Since it's actually PCIe 4.0 lanes from the CPU the chipset should be able to support double the amount of PCIe 3.0 lanes that are branched of that.KOneJ - Wednesday, January 9, 2019 - link
In any case an x4 PCIe3 NVMe drive should work similarly as an x2PCIe4 drive, so fewer lanes for cards should provide comparable end-user results for consumers. Compute is a different matter entirely where lanes can be a bottleneck of significance. XDMA CF works fine, so consumers needn't worry AFAIC.RSAUser - Friday, January 11, 2019 - link
This shouldn't be a problem as you won't max all the lanes at the same time?jjj - Wednesday, January 9, 2019 - link
One quick observation on cost scaling. They got the CPU die, IO die, packaging as major costs and when they add a second CPU die (or GPU) ,they have rather good cost scaling as the IO and packaging stay flat. So they can offer rather good prices at flat or better than flat margins for 12-16 and 6-8 cores+GPU.KOneJ - Wednesday, January 9, 2019 - link
Yep. AMD's earnings calls have heavily emphasized rising ASPs and margins creeping up faster than ever into the low-40s. 7nm may have lower yields, but the decrease in size and the MCM approach will make up for more than people are accounting for.SaturnusDK - Wednesday, January 9, 2019 - link
It's rather obvious this is early engineering sample. Probably of the Ryzen 5 series meant to be paired a GPU chiplet.You would most likely not see an unsymmetrical CPU design like that in a final product.
KOneJ - Wednesday, January 9, 2019 - link
I'm wondering too. S/P Ridge did enable equal CCX parts, with cache enablement varying by SKU, but B Ridge didn't w/ its 4MB L3 and iGPU. APUs in this MCM design will probably leverage the CPU's L3 to an extent, so there will be some data traffic. But since 2 dies is different from 2 CCXs, I think the asymmetrical design might not be that unlikely depending on die harvesting on 7nm between EPYC and Ryzen parts, not to mention potential future mobile SKUs with the MCM design fitting on FP5. Also keeping all L3 traffic on one CPU die may be popular with gamers for high-percentile minimums. Only time will tell and speculating is for share-holders.KOneJ - Saturday, January 12, 2019 - link
Correction: R Ridgesing_electric - Wednesday, January 9, 2019 - link
There's a reason that the mobile parts AMD announced at CES are still on 12nm - they don't want to deal with chiplets for lower-margin APUs. At the moment, AMD has a real lead on Intel on graphics performance.This makes me think that they might be working on a combo IO/GPU die at 12nm (since there's not a pressing need to shrink the GPU to 7 until Intel can offer more of a performance fight). The IO part of the die can shrink, since there's less need to go off-package if the GPU is right there.
There's still the expense in packaging the chiplets up, but we don't know what kind of prices AMD is getting on the 12nm parts from GloFo these days...
SaturnusDK - Wednesday, January 9, 2019 - link
They really don't have to do anything. They can just use the 16/20 part used in the MBP and be done with it.KOneJ - Wednesday, January 9, 2019 - link
But mobile SKUs have higher ASPs with OEMs than desktop APUs, so the margin argument isn't so fair. I think the real issue is waiting for Navi and sorting out the MCM design with the I/O die and how that'll fit into mobile with the FP5 socket and all that.sing_electric - Wednesday, January 9, 2019 - link
One thing re: shrinking from 12nm to 7nm: No one else has gone from GloFo 12nm to TSMC 7nm and released a chip, but AMD did go from 14nm GloFo to 12nm GloFo for its Ryzen chips, and from 14nm GloFo to 7nm TSMC on its Radeon Instinct line.It's far from a perfect comparison, but the 7nm TSMC Radeon MI60's boost clock is 20% higher than the 14nm GloFo Radeon Instinct MI25 (1800MHz vs. 1500MHz, the base clock for the MI60 is unpublished). The 12nm Ryzen 2 (Zen+) clocks about 6% higher than the 14nm Ryzen (Zen).
That means that we can probably expect boost clocks on Ryzen 3000 (Zen 2) to be about 13% higher than Zen 2 and 20% higher than first-gen Ryzens.
If that's the case, then the numbers today either indicate no IPC improvement (which contradicts what AMD told us about Zen 2 for _years_) OR the clockspeeds we saw are likely to be significantly lower than final silicon.
haukionkannel - Wednesday, January 9, 2019 - link
Most likely. Early Ryzen silicon did run lower clockspeeds than the final version. Same is true with Intel prototypes. How much lower is the intersting question. Well we in it Q3.KOneJ - Wednesday, January 9, 2019 - link
Yeah, but frequency scaling on GPU is very different from CPU with power-delivery and thermal-caps. Also, look at single-thread CPU OCs versus GPUs OCing a smaller number of shaders (e.g. 1060 OCs vs 1080s). I don't think comparing CPUs to GPUs for process changes is all that meaningful whether talking about power-efficiency, equal-power for more performance, equal-performance for less power, or stock and OC frequency and power behavior.Duncan Macdonald - Wednesday, January 9, 2019 - link
This way they can use the same chiplet design for the whole range - Ryzen, Threadripper, EPYC if they want and they do not have to use expensive 7nm chip area for something that can be easily done at 14nm. It is probably only the need to keep socket compatibility that stops the PCIe lane count being increased to 32.sing_electric - Thursday, January 10, 2019 - link
It'll be interesting to see how AMD balances high/low when AM5 comes out and they balance the need (for memory channels, PCIe lanes, etc.) between the low-end (Ryzen 3s/5s with APUs) and high end (Ryzen 7... maybe 9? with up to 16C/32T?).eastcoast_pete - Wednesday, January 9, 2019 - link
Great news! I am not partial to either AMD or chipzilla, but a strong 3rd generation Ryzen can only be good for all of us. If Matisse is indeed the price/performance leader for a given use scenario, then AMD it is. If this removes the constipation in Intel's CPU pipeline and makes them more regular, it's good news if it's too be Intel's CPUs.Regarding the number of cores: yes, more cores and threads are principally good, but a key challenge for anything x86 remains single core/ thread performance, and that performance crown is still owned by Intel. I hope that single core/thread performance is what AMD has focused on here. As backwards as it may seem, as long as, for example, browsers still use JavaScript, single thread performance is key for many every day use scenarios..
RSAUser - Friday, January 11, 2019 - link
If you properly used Web Workers, then JS is not single threaded.Most of the time it doesn't matter though as the performance impact of the JS is not enough to slow down the page very much.
wurizen - Wednesday, January 9, 2019 - link
"The company did state that it is the world’s first 7nm gaming CPU, and will also be the world’s first mainstream CPU to support PCIe 4.0 x16."WTF is a "gaming CPU?"
If, there is such a thing as a "gaming CPU," what makes this particularly more "gamer-y" than another CPU?
Or, does Ryzen 2 address the "gaming" aspect that prior Ryzen didn't?
Does this mean a "fix" to Infinity Fabric's high latency issue?
If so, how?
I am going to wildly speculate that if there is, indeed, a Ryzen "gaming CPU" that it might have embedded RAM? It's the only thing I can think of at the top of my head that would permanently fix that latency thing.
SaturnusDK - Wednesday, January 9, 2019 - link
It's a typo... she said gaming GPU.wurizen - Wednesday, January 9, 2019 - link
SaturnSDK, Oh, ok. That makes more sense. But, still, WTF is a "gaming GPU?"Just kidding.
Well, half-kidding, anyway....
AlexDaum - Wednesday, January 9, 2019 - link
It's a CPU that makes sense for gaming, so it's a mainstream mid range to high performance CPU. Not an Atom, Celeron or Athlon, but also not a Threadripper or i9 x/xe.Infinity Fabric will still have an impact on latency on new zen 3, but I don't know the detailed chiplet design, so I don't know if there is inter-core latency or just additional memory access latency, which would not be as bad, because the same latency increase that made a huge difference in L$3 access is almost negligible in DRAM access.
wurizen - Wednesday, January 9, 2019 - link
AlexDaum,According to papers/articles already written about AMD's Infinity Fabric, the inter-core latency is not the issue. It is the Cross-CCX-latency... the latency associated with traversing and hopping on the so called magical Infinity Fabric highway....
There is no mention on this wonderful new tech AMD created at all. All they talk about is more cores, IPC, etc.
What about the highway you built, yo? That sounds more interesting to me. Wouldn't you other "Techies" agree?
sing_electric - Thursday, January 10, 2019 - link
Yeah, but to some extent you've got to speak to your audience. At CES, the intended audience is as much the tech journalist at mainstream media (wire services, Time Magazine, etc.) and gamers, and isn't really the right place to talk about architecture. AMD did a decent job outlining things at the EPYC Rome presentation a couple months ago, even though a lot of it was "we'll tell you more later."Arbie - Friday, January 11, 2019 - link
Are you still yammering about Infinity Fabric? The fact that AMD didn't talk about it to your personal satisfaction implies nothing - except maybe that it's working fine. Give it a rest.jeffpeng - Wednesday, January 9, 2019 - link
I'm pretty sure we will see that second 7nm die eventually. Honestly: why would they layout the CPU this way if it wasn't primed for a second die. Even from a pressure distribution perspective this would be nonsensical. Why they didn't show it that way... who knows. Might not work yet, might actually be to stir exactly this kind of speculation, might be they did want to show off they really can do high clock speeds on the same silicon that apparently has 100% core yield.Also it simply makes sense from a yield perspective. With two chiplets they can recover even halfway wrecked chiplets to run in 8 core CPUs, which for all intends and purposes will remain the "sane" consumer core ceiling for some time, I think.
Will we really see 12 or even 16 core CPUs ... pretty sure 12, 16 probably. Memory bandwidth will be an issue with some workloads. Then again with some it won't. Hugely depends. And if it's just to 1up intel on the consumer platform... AMD will go beyond 8, and I think they've shown they theoretically can. And if TR keeps being "half" Epyc .... there really isn't much cannibalizing going on. It's hard to think of a TR3 with less than 16 cores among 4 chiplets. That would be true garbage silicon then.
I'm also pretty sure we'll see GPU's as the second chiplet at some point, however APU's lag behind the standard CPUs a full generation since Ryzen 1000. And two APU designs at the same time? Nah. Those will be Renoir and we won't see them before 2020. And considering how well even Raven Ridge is holding up ... that's kinda fine.
Harry_Wild - Wednesday, January 9, 2019 - link
I decide to buy an AMD Zen 2 instead of an Intel i9 9900K when I do my PC build desktop. 7nm - yes..............!ajc9988 - Wednesday, January 9, 2019 - link
Ian, you didn't loose your money yet. There are traces to the second spot you point out on the PCB (hard to see in your photo, but I could see them at certain angles when Su held it up during the keynote). For latencies, since they are using the I/O die like on the Epyc CPU, they are able to mask the NUMA element so the entire package is a single NUMA node. That avoids the pitfalls of NUMA node issues we saw with first and second gen TR and first gen Epyc.That space will be filled by release, I could guarantee that. Meanwhile, the IF2 controller and higher bandwidth, lower latencies of second gen Infinity Fabric will be present. In fact, the latency of going off die for every memory call will already be found by doing the I/O die with IF2, so please ask questions on the IF2 latency. Meanwhile, that means accessing the cache on the second die, since it was mentioned Epyc has it fully routed through the I/O die, will require the additive latency of going all the way round trip, 2 hops each way, unless they are using the enlarged L3 cache to be mirrored between the two chips, with some way setup to sync them and retire the data relatively to each other. That might be why the L3 was enlarged that much. So many more questions.
But don't pay up until after the release.
Also, with the cache on the active interposer for Foveros, likely L3 shared cache feeding the L2 for both the bigLITTLE cores, I have to also say I'm very impressed with the 3D stacking Intel is doing. I crapped on their statements last month and need to eat my words there, just as an aside.
AlexDaum - Wednesday, January 9, 2019 - link
I could see that they do not have a shared L3$ between chiplets, but rather some kind of L4$ in the I/O die. I would think it would make sense to have that L4$ as kind of memory bandwidth saving method, so that when two chiplets require the same data, it is already in L4 after the first fetch, but the CPUs don't have to talk to each other to first see if any L3 contains that data... Kind of the same as between L2$ per core and L3$ shared, the cores don't look into other L2$ to figure out if they have the data, they just look in L3, and if it misses, then it gets fetched from memory.GreenReaper - Wednesday, January 9, 2019 - link
They could mask the NUMA configuration, but it probably wouldn't be a great idea in general. It's useful information to have, if only the operating system uses it properly.KOneJ - Wednesday, January 9, 2019 - link
They can't bank on that with Windows though.rocky12345 - Wednesday, January 9, 2019 - link
I am actually ok with it just being 8 core and if it is 8 cores on a single die even better. From the looks of the CPU and the space left it does look like they left themselves the option to either add another chiplet if needed or this is not the top end chip and we just might be seeing a 10 or 12 or 16 core CPU as well. I myself plan on just going for the 8/16 CPU when they launch. If they do indeed release a 10 or 12 core part I might look into that as well but if adding a second Chiplet adds latency and causes games to have less FPS then I will just stick with the 8/16 CPU which is more than enough for me anyway.JKJK - Wednesday, January 9, 2019 - link
This is great!! I'm planning a pcie4.0 build (hedt) and seeing how these cpus will perform and how Intel will answer is so fucking exciting! I CAN'T WAIT!!! :DRakman - Wednesday, January 9, 2019 - link
Ian Cutress, you can't "pre-announce" anything. You either announce it, or you do not announce it. There is no other status of announcing. "Pre" means "before", as in a sports pre-game show that occurs before the game that it announces. You can "early announce" something, but that is still an announcement. You also violated one of the rules of logic. Something cannot be both A and B at the same time and in the same context.KOneJ - Wednesday, January 9, 2019 - link
They didn't announce the SKUs with a launch date. They did demo the hardware though, before announcement. I don't think the pre-announcement phrasing was at all egregious. It's fair to call it a pre-announcement demo as they weren't announcing final products for sale.mkaibear - Thursday, January 10, 2019 - link
Sorry, that's incorrect.You can easily "pre-announce" something. If I say "we have a new product coming up, we're not going to announce final clock speeds or configs yet but here's some info" that meets all the criteria for not announcing something but nevertheless providing information on it. Hence pre-announce.
GreenReaper - Thursday, January 10, 2019 - link
That's still announcing that there will be more information later.sing_electric - Thursday, January 10, 2019 - link
It's announcing that there will be a product announcement. At a product announcement, you give the product a name, specifications, availability (and usually pricing). They did not do that, but they did preview one chip that they will be announcing later. Not every "announcement" is the same - yes, she did announce things, but she did not announce Ryzen 3 products specifically, so she made some "pre-product announcement" announcements, hence "pre-announce."KOneJ - Thursday, January 10, 2019 - link
"later" necessitates a "before". pre (before) announcing the product. This is information being prior (before) announced before the product announcement. sing-electric is correct.dgingeri - Wednesday, January 9, 2019 - link
That IO die, like on the Epyc, is awfully big. I think there's more to it than just 24X PCIe, IF, USB 3.1g2 and a couple SATA ports. Is the memory controller on it? Could there be some L4 cache on it?Seriously, the whole Ryzen 1000 line was 192mm^2, made with the same manufacturing process, with 8 cores, and this IO die is 122mm^2. How could the combined IO die and 7nm core die sizes be larger than the original Ryzen die if it contained the exact same features? There has to be more there.
PixyMisa - Wednesday, January 9, 2019 - link
WikiChip puts the size of the CCX at 44mm^2, so that IO die actually looks about the right size for everything else on the Zeppelin die.dgingeri - Wednesday, January 9, 2019 - link
192mm^2 - 88mm^2 = 104mm^2, so, yeah, perhaps that extra space might be made up for extra IF circuitry for another die to attach.Still, the combined die sizes come out to bigger than the Zeppelin die. The old CPU CCXs at 14nm were 88mm^2 total, and this node shrink should reduce the CPU cores about 40% and the cache by about 10%, so I would think the CPU chiplet would be closer to 50-55mm^2, yet it is over 80mm^2.
I knew something looked too big. I was wrong about the IO die, but not about something being too big. My first thought was perhaps an inclusive L4 cache on the IO die to reduce cache snoop stalls, but that was wrong. Perhaps converting the L3 to an inclusive cache instead of the victim cache function it serves now? Perhaps an increase in cache size? I think increasing the L3 cache size while keeping it a victim cache would be counter productive. Anyone have any ideas on what they'd do that would increase the CPU chiplet size?
F1Lane - Wednesday, January 9, 2019 - link
"AMD is committing itself to 7nm as the future process note that will drive the company's innovations starting in 2019"Note? you mean NODE?
Darcey R. Epperly - Wednesday, January 9, 2019 - link
Availability Q2 or Q3. Isn't this when Intel 10 nm Sunny Cove will be around too? If AMD catches up to 9900K then Intel will increase the performance again. Is it ok to say, AMD Zen 2 comes a bit too late?dgingeri - Thursday, January 10, 2019 - link
Intel was caught unaware when the initial Ryzen came out. They had to rush to get the 8700k out. The 9900k is at the limits of the ring bus that keeps the processor operating, and operates above it's specced TDP. I seriously doubt Intel could do anything to extend the performance of what they currently have out. They need to get new tech out to show AMD more competition, and that isn't coming for at least another year. Sunny Cove isn't expected to see the light of day until Q2 or Q3 of 2020, not 2019.In the mean time, AMD is not only competing, but doing so at much lower prices. Intel is having a much harder time of this than most people think.
RSAUser - Friday, January 11, 2019 - link
As dgingeri said, Intel is in a bit of a predicament currently, their architecture is at its limit and the new architecture is only expected around 2020. A die shrink could have helped them achieve parity/similar performance to AMD, but 10nm is still delayed.They'll probably have 7nm out before/same time as 10nm in 2020/2021.
TheJian - Wednesday, January 9, 2019 - link
I just hope this is $400 or so, or even closer to Intel $478 if it is just as good. NO DISCOUNTS. It's time to make NET INCOME. Then add a 2nd chiplet and release 12/16 cores ASAP to slap those ON TOP of Intel. Don't charge $299 for this unless it really sucks perf wise. It seems it's directly competitive with Intel 9900, so PRICE it like that! Quit passing up opportunities to make INCOME, by attempting to either get market (with no margin) or be your customer's friend. Charge what your chips are WORTH! In the last 4yrs they've lost 1.2B+ (~400mil losses for 3yrs, 2017 finally made ~40mil NET INCOME). 2018 looks like a few hundred mil for the year, and we'll know that in a few weeks (29th or so Jan). If you want to FINALLY make money for 2yrs straight, don't give a dang discount on a chip that runs like Intel's $478 chip. Price it at $450. It is NOT your job as a company to GIVE away chips with every launch at major discounts.IE see rumored Navi10 pricing, $249 for a GTX 1080/1070ti perf...Uh, should be $350-400 then min probably. But $249, well, I'd fire management for this price. They won't make money. Not sure if they'll make a dime on $699 card either, as 16GB HBM will kill the card most likely as it has done to EVERY consumer card they've put it on (besides holding up production on top). It should have been 16GB GDDR6 or GDDR5x. There is a reason NV made billions going GDDR5x instead of HBM/HBM2. There is no need for HBM in current cards as 2080ti shows. GDDR6 fine. They keep making the same dumb decisions (HBM, kill production+kill NET income). AMD should not be producing a consumer gpu with HBM (1/2 or 3). It gets you nothing but PROBLEMS (cost or production issues) and kills sales or profit. Charge what you're worth, but quit adding crap to your products that kill their INCOME or ability to sell them (hbm production issues constantly killing launches).
dgingeri - Thursday, January 10, 2019 - link
The manufacturing costs for Ryzen chips is less than $70. Even with this 2 chip package, it probably doesn't amount to more than $80. They can charge less and sell more and spread the engineering costs for the chip over a larger sales spread, and still capture market share. There are a lot of financial "experts" that just don't understand this aspect of business. They think in order to make more money they have to charge more. That's not true. If a business needs to recover $1 billion in engineering costs, they can do so more easily selling for a $200 markup across 5 million units more easily than charging a $2000 markup and expecting to sell 500,000 units. Plus, with the lower markup, it is more likely to sell additional units past the point of recovering costs for pure profit.FC switch and storage makers didn't understand this, and they lost market share and sales to an inferior technology: iSCSI. Now, businesses are buying iSCSI storage hand over fist because the ethernet switches cost so much less, even if it performs far less effectively than FC. In 2005, the cost of physically manufacturing a 48 port 8Gb switch was under $800, not including the engineering and development costs. They charged over $30,000 for one with only 16 ports enabled, and an additional $8000 to license 16 more ports, for a total of $46,000 for a 48 port switch. Manufacturing FC storage was actually less expensive than iSCSI storage because the standards were much more simple, but the FC storage sold for more because the only ones buying it were the ones who could afford the switches. If they'd charged only $4000 for those switches, they could easily have sold a hundred times as many and made more profit. In addition, that would have allowed businesses with lower budgets to buy FC storage, thus reducing the costs from the makers and increasing adoption. Instead, they kept the market restricted with high prices, and small businesses adopted iSCSI. Then iSCSI became the "budget" standard, and higher end businesses began adopting it for cost savings. Now, FC storage SANs are practically dead, despite the fact that 32Gb FC can outperform 100Gb iSCSI by over 30%. Many FC switch companies lost profits and ended up being gobbled up by other companies, and FC storage is pretty much gone. The FC switch makers priced themselves out of business.
AMD would probably make twice the profit selling their top end AM4 chip for $300 than they could at $400. That extra $100 would likely discourage half of their buyers at least, and end up reducing the profits they would make substantially. It is a delicate balance, and ones their financial experts likely have already calculated.
RSAUser - Friday, January 11, 2019 - link
+1 dgingeriArbie - Friday, January 11, 2019 - link
It's too bad none of the AMD management knows anything about the chip business or finances. If only they were as smart as you...hencok456 - Thursday, January 10, 2019 - link
Very nice post thanks for sharing. visit for any help related QuickBooks http://www.quickbooks-help.net/KOneJ - Thursday, January 10, 2019 - link
@ Ian Cutress: Just wanted you to know:"we were told that the Core i9-9900K was allowed to run at its standard frequencies on an ASUS motherboard."
Not what I saw in the press release footnotes @ https://globenewswire.com/news-release/2019/01/09/...
Footnote #9: "Testing performed AMD CES 2019 Keynote. In Cinebench R15 nT, the 3rd Gen AMD Ryzen Desktop engineering sample processor achieved a score of 2057, better than the Intel Core i9-9900K score of 2040. During testing, system wall power was measured at 134W for the AMD system and 191W for the Intel system; for a difference of (191-134)/191=.298 or 30% lower power consumption.
System configurations: AMD engineering sample silicon, Noctua NH-D15S thermal solution, AMD reference motherboard, 16GB (2x8) DDR4-2666 MHz memory, 512GB Samsung 850 PRO SSD, AMD Radeon RX Vega 64 GPU, graphics driver 18.30.19.01 (Adrenalin 18.9.3), Microsoft Windows 10 Pro (1809); Intel i909900K, Noctua NH-D15S thermal solution, Gigabyte Z390 Aorus, 16GB (2x8) DDR4-2666 MHz memory, 512GB Samsung 850 PRO SSD, AMD Radeon RX Vega 64 GPU, graphics driver 18.30.19.01 (Adrenalin 18.9.3), Microsoft Windows 10 Pro (1809)."
Yeah they made a typographical error with "i909900K" instead of i9 9900K or i9-9900K.
But they also specified "Gigabyte Z390 Aorus"
KOneJ - Thursday, January 10, 2019 - link
Anybody else notice that demo was run with DDR4-2666?LemmingOverlord - Thursday, January 10, 2019 - link
Gotta say: nothing Su presented yesterday was any bit surprising. So we got: higher clocks, tuned performance, lower consumption, lower manufacturing costs all-round. Yeah. The chiplet design is groundbreaking, but its benefits are part of a longer-term strategy (which is not exclusive to AMD, btw. Intel is going down the exact same route). The key to AMD's strategy right now is squarely pegged on the yields of 7nm output... much like Intel's on 14nm++, and that can be quite dangerous.Early Zen 2 silicon is showing tit-for-tat performance with Intel's Core i9 on the same number of cores. That's good. That's what we want. Same performance, a few less bucks.
On the GPU side, I was seriously underwhelmed by the shrunken Vega. Same thing, different node.
Is it just me or is AMD's current strategy just bitch-slapping Intel where Intel is throwing money at? (eSports)
Maxiking - Thursday, January 10, 2019 - link
We do not know anything about Zen 2 performance.2600x and 2700x are already faster in CineBench by cca 5% than 8700k, 9900k respectively clock to clock.
Hypothetical situation. Had it been no IPC gain, just improved frequency and power consumption, 2700x on 7nm or 2700x even on their 14nm+ would have been faster by 5% if matched clock to clock - i7 9900k boosts @ 4.7ghz for all cores.
KOneJ - Thursday, January 10, 2019 - link
You're not looking at the all-core difference between the 2600X, 2700X, 8700K, 9900K, not to mention cooling solutions, motherboard configurations, RAM speeds, timings, bandwidth, and channels, and how the all-core is sustained in Cinebench R15 under varying considerations. Also the feeding data structures with core acceptance off of uncore can be a bottleneck at high core OCs with diminishing scaling and reduced IPC. This is why cache overclocking exists, and the interactions are also dependent upon and nuanced with IF mesh, MoDeX, and the Ringbus of SKL K-SKU derivatives.KOneJ - Thursday, January 10, 2019 - link
At least Radeon Vega VII has 128 ROPs. Good news for Navi methinks.KOneJ - Thursday, January 10, 2019 - link
"The key to AMD's strategy right now is squarely pegged on the yields of 7nm output... much like Intel's on 14nm++, and that can be quite dangerous"don't think there's much need to worry. TSMC was early to HVM 7nm, has a strong track record, and has worked well for Apple, Huawei, and Qualcomm. The chiplets are small enough that yield is more comparable to mobile dies than Intel's monster monolithic parts.
nukunukoo - Thursday, January 10, 2019 - link
Zen 2 seems to have finally matched Intel's single-core IPC. Too bad the "leaked" specs last December does not match the 8-core's TDP at the keynote. Just hope the pricing will keep intel on its toes. Having said that, a 16-core Z2 would definitely be sweet for my next 3DS/Maya/Resolve build!willis936 - Thursday, January 10, 2019 - link
Zen 1 has higher IPC than intel’s past half decade generation.KOneJ - Thursday, January 10, 2019 - link
Don't know about that. It was an engineering sample. They probably set the clocks to edge out the 9900K and the 75W TDP was an incidental byproduct. There may well not be a final product with a 75W TDP. I'd say that's likely actually.Haawser - Thursday, January 10, 2019 - link
AMDs manufacturing strategy looks like it is taking another huge leap forward here. Fair bet says that they will use exactly the same 7nm CPU chiplet in *everything*. Server, desktop, HEDT, APUs, and even the next gen consoles.Only having *one* 7nm chiplet to design/test/validate (and manufacture) has so many positive advantages it would be hard to list them all. But that's obviously their plan, and it's one that I doubt Intel will have an answer to anytime soon, even if they do get their 'relaxed 10nm' working.
PixyMisa - Thursday, January 10, 2019 - link
Yes, the ideal design for a next-gen console is a big custom die with GPU, memory, and I/O, and then a standard 8-core CPU chiplet.KOneJ - Thursday, January 10, 2019 - link
IDEALLY, a MCM GPU would be better than monolithic. It just requires a creative scalable architecture that is transparent to software with the challenges of mGPU programming.Kevin G - Friday, January 11, 2019 - link
nVidia has done research into this published a research paper on the topic.It would be foolish to think that AMD is not perusing the same ideas on the GPU side that they have shown on the CPU side.
In fact one of the obvious things to do for GPUs and chiplets is to spin off miscellaneous IO (PCIe, HDMI, DP controllers) and various codec engines to their own die as those don't need perpetual updates between GPU generations nor cutting edge manufacturing.
KOneJ - Saturday, January 12, 2019 - link
IK about the NV paper. And AMD is very aggressively pursuing scalability. I think MCM GPUs from AMD that aren't plagued with mGPU programming challenges are slated for post-GCN. Whoever makes it to MCM GPUs will have a MASSIVE advantage over the competition. But MCM GPUs are significantly more difficult than MCM CPUs as David Wang rightly pointed out. Some aspects of Zen will definitely migrate into the RTG side. Already has, even with Zen and Vega if you read the white papers.Kevin G - Monday, January 14, 2019 - link
It depends entirely on how they are split up.The balanced performance would implement a cross bar die that housed the memory controllers so that every compute die would have even access to. The catch is that the cross bar is massive in current designs and scaling up the number of nodes here only further increases complexity. Getting enough memory bandwidth is conceptually also a challenge as they have to be placed close to the cross bar die. This does mimic AMD's strategy with the Zen 2 based Epyc.
A NUMA based GPU design with say, four nodes in a package each with their own pools of HBM memory on twos sides for a 4096 bit wide bus wouldn't be a bad decision either. However, scaling like the centralized idea above faces some physical layout challenges and doesn't inherently make individual dies smaller. nVidia's research paper explored this and was estimating around ~85% as fast as monothilic die due to the shear number of links and high bandwidth connections between each die (if you're using interposers, go all out here). While many think that this would be seen as a quad GPU setup (and for certain workloads, you'd probably want it to be), it can be virtualized to appear as a single GPU for gaming. The dies are close enough and have enough connectivity and bandwidth between each other that I don't see this as being an issue for most workloads.
An extension of the above idea would be to build compute dies and memory router dies which the HBM sits directly on top of. Essentially this is a tiled grid of compute and memory routers. Each router can coherently manage traffic form the four nearest neighbors. This enables scaling to higher compute, memory bandwidth and memory capacity but comes at the cost of far higher scalability issues. Instead of a single high bandwidth hop between nodes, we could be approaching 10 in a realistic design. The issue shifts from bandwidth to latency and being able to distribute a workload evenly.
KOneJ - Thursday, January 10, 2019 - link
Maybe. But their consoles might cut cache for power reasons. Other changes are also easily possible with mobile. It is almost certainly still a victim cache, but still needs to operate within a power budget. Jaguar, for example, cut some units it didn't much need while beefing up others. I wouldn't be surprised if you're right, but I wouldn't be surprised if you're wrong.BigT383 - Thursday, January 10, 2019 - link
I guess this means AMD brought back the Front Side Bus and Northbridge paradigm... just keeping it all on package.BigDragon - Thursday, January 10, 2019 - link
I was expecting to see 12 and 16 core chips. I hope those are still coming. 8 cores is not enough on desktop anymore and should be the minimum on notebooks and tablets now.If all you're doing is browsing the internet or playing games then, sure, 8 cores is enough for you, today. Me? I do a lot of things simultaneously on my computer (on top of all the crap Windows is doing simultaneously out of view). More cores lets me keep multiple 3D art programs open simultaneously without waiting for loading, for example.
CheapSushi - Thursday, January 10, 2019 - link
Then why aren't you going HEDT with Threadripper? Do you know it exists? Or are you just unwilling to pay for what you're actually doing.PixyMisa - Thursday, January 10, 2019 - link
From the Q&A session after the keynote:Lisa Su: So there is some extra room on that package. And I think you might expect that we will have more than eight cores. I didn’t say how many more.
KOneJ - Thursday, January 10, 2019 - link
This.KOneJ - Thursday, January 10, 2019 - link
If your machine isn't holding up, then you either need to revise your workflow or jump to an HEDT platform. If you really actually need that performance then even if its difficult to swallow the price tag, you can't afford not to. You also didn't indicate what CPU your using now as a basis for 8 is not enough. And while 8 is enough for most people now on mainstream, more at the same price or the same at a lower price is by no means a bad thing. Also, you seem to contradict yourself by calling 8 the minimum for notebooks and tablets while saying that browsing and gaming is served plenty by 8. As that is what the vast majority do, 8 is appropriate for mainstream desktop, and if you're not in that populace, you need HEDT, SHED, or server parts. This is not to say that I don't hope and expect still to see 12 & 16 parts.KOneJ - Thursday, January 10, 2019 - link
If your machine isn't holding up, then you either need to revise your workflow or jump to an HEDT platform. If you really actually need that performance then even if its difficult to swallow the price tag, you can't afford not to. You also didn't indicate what CPU your using now as a basis for 8 is not enough. And while 8 is enough for most people now on mainstream, more at the same price or the same at a lower price is by no means a bad thing. Also, you seem to contradict yourself by calling 8 the minimum for notebooks and tablets while saying that browsing and gaming is served plenty by 8. As that is what the vast majority do, 8 is appropriate for mainstream desktop, and if you're not in that populace, you need HEDT, SHED, or server parts. This is not to say that I don't hope and expect still to see 12 & 16 parts.Arbie - Friday, January 11, 2019 - link
This subject was beaten into the ground in the first comment pages. Back from the dead...nemi2 - Thursday, January 10, 2019 - link
"there’s just enough space for another CPU chiplet (or a GPU chiplet) on this package"*OR* a huge chunk of level 3/4 cache.
I'd prefer to stick with 8 cores + HT and get 128 Mb or more of high speed Level 3/4 cache on the package. That could give some great improvements for certain work loads....
KOneJ - Thursday, January 10, 2019 - link
That's not possible as SRAM that large (128MB(Think you meant MB, not Mb)) would fit in that gap even at 7nm. Furthermore, copying data around is hardly power efficient, and that wouldn't work either. L4 might help justifiably with server workloads and could be used to help with power efficiency by reducing bandwidth constraints by having to copy out to DRAM. But not in the way that you're suggesting.GreenReaper - Friday, January 11, 2019 - link
It would probably be eDRAM rather than SRAM, like the Iris Pro.KOneJ - Saturday, January 12, 2019 - link
Possibly (Probably at that size.), but even still CW had huge die-space dedicated to that. This isn't happening here at that quantity. There are several other things they could try to alleviate these issues such as ChargeCache.gglaw - Thursday, January 10, 2019 - link
With the extra space, a "3400G" with 4GB of HBM2 and a newer GPU would be an amazing mid-tier product for gamers wouldn't it? It would cost less money and power than buying a separate video card and since Kaby-G Intel was already able to squeeze on a GPU solution that sits in between a GTX 1050 and 1060. For the same size/power, Navi should be a major leap over this into GTX 1070 territory if it used HBM2. This type of custom chip could have applications for consoles as well, just swapping out which chiplets are popped in and for consoles the HBM2 could be used as the sole memory. Using system RAM at current DDR4 speeds seems to be the major crippling factor for APU's.I don't have any verified sources for current HBM2 costs, but posts from 2017 indicate it was around $75 per 4GB module. Assuming this has gone down some, for home use settling for a 6c/12t CPU and paying maybe $50 premium to include a gigantic GPU performance boost would be very enticing to me. And it isn't a true $50 (or whatever the current price is) since this also means you need less system memory that isn't shared. For a mid-grade system could easily get by with 8GB DDR4 instead of 16GB with dedicated GPU HBM2 replacing the cost of more system RAM. A 3400G with 4GB HBM2 and 8GB of system DDR4 would cost very similar to one with no HBM2 and 16GB of system RAM and perform WAYYYY better.
KOneJ - Thursday, January 10, 2019 - link
Doubt there's enough space on the package for HBM2 and a decent number of CUs on a GPU die, even at 7nm. Not to mention the niche demand as the whole upgrade, sell, buy, replace dynamic is different with integrated than discrete.gglaw - Friday, January 11, 2019 - link
It's definitely a niche among hardcore ennthusiasts but I think we underestimate the market for people who buy whole systems and upgrade every 3 or so years by replacing the system. I would bet that this number eclipses the every 3-6 month upgrade 1 component cycle most of us live by. Is there a reason the Kaby-G can fit 8GB HBM2 and a nearly RX570 GPU on their package and Ryzen 3 couldn't fit 4GB HBM2 (1 less module) and a smaller Navi chiplet (my terminology is probably all off, I have no experience with chip design lol)?Again not a huge market but the NUC concept has been successful enough to carry on for many years now. AMD could definitely claim a chunk of this with how good Ryzen/Navi APU combos could perform.
gglaw - Friday, January 11, 2019 - link
Also as far as sales/marketing for the very large population of whole system buyers, I believe the Kaby-G model can legally be sold as "discrete Vega graphics" products. Some of these products list in specs: Processor: Intel 8th Generation Core Processor, "Graphics Card": RX Vega M.Not sure what the distinction is that allows a company to call the GPU a "graphics card" or "dGPU", but the average consumer would never know the difference in these types of systems. And they are in fact getting discrete graphics card performance although there isn't actually a card lol.
KOneJ - Saturday, January 12, 2019 - link
Problem is that for HBM2 to make sense, it needs a GPU that needs it. And even at 7nm, there doesn't seem to be enough space for a meaningfully large Navi chip AND an HBM2 stack on the AM4 package along side the I/O die and CPU die.https://hexus.net/media/uploaded/2018/6/5a1a21b1-a... for reference.
Also, I don't think most people live by the cycle of a component every 3-6 months, even amongst PC gamers, even if factoring in peripherals. What will eventually happen is having dGPUs plug in to desktop boards via a physical interface more compact than a huge PCIe x16 card. Gen-Z or OpenCAPI and the like may well bring that.
KOneJ - Saturday, January 12, 2019 - link
Also, the niche covers Kaby Lake-G designs. AMD might want to hit those because of space, cooling, and power-delivery advantages versus a dGPU in a notebook that'll never be upgraded. It's more likely these are the target than the desktop chips that come on the side. This seems more likely to be their focus if/when they go this route.quadibloc - Friday, January 11, 2019 - link
Initially, my reaction was that it is very likely there will be a 16-core Ryzen, since the technique for doing that was pioneered on the 32-core Threadripper, so AMD knows how to do it. But the 32-core Threadripper served a purpose, because EPYC motherboards are expensive and hard to get. If you want 16 cores, why not get full performance, and get a Threadripper board? So AMD may have the ability to make a 16-core Ryzen, but they may be undecided as to whether it's really a worthwhile thing to make.SaturnusDK - Sunday, January 13, 2019 - link
Threadripper is a different market segment. It's not only about the cores, it's also just as importantly the PCIe lanes, total memory bandwidth and maximum supported memory. A 12/16 core Ryzen will have very minor impact on the lowest end of the Threadripper line up, if any.Cooe - Friday, January 11, 2019 - link
"The 8-core AMD processor scored 2023, and the Intel Core i9-9900K scored 2042."Uhhh Ian? You've got those two Cinebench scores backwards. It was the AMD chip that scored 2042, with the Intel i9-9900K pulling down 2023.
silverblue - Friday, January 11, 2019 - link
"We had a pre-briefing and the scores I published were the ones we saw during that prebriefing."Santoval - Friday, January 11, 2019 - link
If AMD maxes out at 8 cores in mainstream (at least at first) then they must be very confident about Zen 2. Well, they did say they designed Zen 2 to compete with Ice Lake, din't they? If they do not need more cores to compete with the best 14nm based mainstream CPU from Intel why would they increase the cores? It might be best to reserve that little space in the corner for when Ice Lake / Sunny Cove is released, which would be 5 to 6 months later (if Intel does not screw up again).ionut - Saturday, January 12, 2019 - link
Intel CPU has integrated graphics. AMD CPU consumes less power. But Intel without graphics what TDP has?Haawser - Saturday, January 12, 2019 - link
They used a Vega64 on both systems, they didn't use the 9900Ks iGPU. https://youtu.be/g39dpcdzTvk?t=1025csell - Saturday, January 12, 2019 - link
Hi.At the end of the 'Attacking the Mainstream CPU Market: Toe to Toe with Core i9-9900K' paragraph do I read
QUOTE: 'so it would appear that a lot of current 300 and 400 series motherboards, assuming the traces adhere to signal integrity specifications, could have their first PCIe slot rated at PCIe 4.0 with new firmware.'
My questen is how do you understand this. Will it be possible to have dual Graphics Cards, One using PCIe 4.0 and the other using PCIe 3.0 both running x8?
And will it then be possible to swap one of then out with a two or four way M.2 PCIe riser card?
as i am looking into a system with two or tree M.2 NVMe x4 SSD's.
What do you think?
FXi - Sunday, January 13, 2019 - link
I can't believe that Intel is going to let AMD be the first to offer pci-e 4.0. Lost the nm race and now this too...azrael- - Tuesday, January 15, 2019 - link
Haven't trawled through all 300+ comments, so someone perhaps already brought this up.I *really* hope that this new chiplet approach doesn't mean that ECC support will be gone from the standard Ryzen CPUs. If there's anything I've always liked about AMD it is their lack of need to cripple their products.
FWIW I see a Ryzen 7 3xxx in my future ...provided it supports ECC memory, of course.
@IanCutress, any insights into that at this point?
IUU - Thursday, January 24, 2019 - link
Good to see AMD catching up with Intel at absolute performance numbers. Still sad though, because this is done at 2 about generations ahead in terms of node size. Well of course at some point , if you do no other significant improvements, but still improve your manufacturing process you will catch up, but this is no real catching up , right? And I don't think that it is so difficult for AMD to improve its performance per node process. I just can't believe this is due to an intrinsic disability of their engineers. The same way I can't believe Intel really encountered any obstacles in going from 22 to 7 nm as they have been claiming for a while now. Which means all this is set up somehow and for some reason. Personally, I like the model where "computing" is more important than "gaming" , because actual gaming (and not FPS or camera moving games only) really requires the "computing" philosophy, and because I like to do other things than gaming only.deksman2 - Thursday, February 28, 2019 - link
Really?And the fact that AMD demo-ed a mid-range Zen 2 part CPU with 8 cores and 16 threads which slightly beat out the i9 9900K at half the power draw means nothing?
Or the fact that Zen 1 and Zen+ already closed a significant gap with Intel and that majority of industry developers code for Intel in the first place (and not AMD)?
AMD did good considering what kind of brute force approach they need to take to appear 'good' in people's eyes'.
Once the industry is optimizing more for AMD products in general, the landscape will probably change even more.
mito0815 - Thursday, January 24, 2019 - link
Looks good so far. A few months of actual AMD x86 end user/server space performance crown might shake Intel up a bit more than already the case.Bill The Cat - Thursday, January 31, 2019 - link
I've been doing good with a 6/12 core/thread first gen Ryzen but what the hey, I want at least 8/16 and for my other computer I want 64/128.And hold on, who told everyone about my Saturn V addon.. Who told? It was going to be my best computer ever that would plaster me into the moon at 186K miles per decade.. LOL... Gotta have cores and more cores... But really, 8/16 should last a long time.
Heilwiga - Friday, March 1, 2019 - link
The Specs are just amazing. I love the new <a href="https://www.linkedin.com/company/seo-company-in-gr... Ryzen. AMD is doing fine work!Dragonstongue - Sunday, May 26, 2019 - link
People seemingly complete discount/dismiss the impact that transitioning from Bulldozer through to First gen Ryzen/ThreadRipper/EPYC had to the global tech industry, it shot a "smart shot"AMD could not compete on speed, raw performance etc etc etc, what they could however compete on is loading a single chip with numerous cores and/or split up a motherboard in it's entirety to slap upon a single processor (AMD was the first to a true dual core etc etc etc)
Point is, Intel was far too dedicated to optimizing power use (when not in turbo or overclocking it in any way) as well as performance everywhere they could though slapping more cores as well as more threads was not as interesting in getting something to run mach 20 and sip power while doing so (how many years did they mange to do exactly that)
problems of course become magnitudes more difficult the more crap you cram under that tiny little hood, so I suppose making a single wicked core "makes sense" a single anything no matter how large cannot compete vs many many little guys running a bit slower (reducing heat, power, complexity, wafer yields, keep all features available to every chip you put out for that generation etc)
GPU sped things up, then did FPGA, then did ASIC (which GPU "use" to be a completed "board")
anyways....long and short of it..AMD expertise in shrinking things, reverse engineering and the like allowed them to slam a load more everything into the same space, Ryzen 1 was a massive success, it hurt Intel and Nvidia and everyone else in their own fashion,
Ryzen+(12nm) just sped it up and optimized some of the key features ( XFR and Precision boost version 2 etc) made them smack the living crud out of intel, that is a fact, intel is already hurting dearly from their own "bad cake" sort of speak, AMD is just piling the hurt on.
AMD is doing targeted strikes against the weakness in the INDUSTRY not the individuals, I personally believe that, we need MORE to propel the way forward, more for less of a higher quality and reliability/support network backing it.
Ryzen 3 was/is truly the "right place at the right time" unless all of them are buddy buddy and allowing AMD massive "industry wins" ($$$$$$$$$$ sales therefore market and mindshare which are priceless)
Splitting up the I/O from the core, genius, are they the first, no, did they do it the best way thus far, oh hell yeh....my phones CPU/GPU while crazy fast for a phone simply does not stand a chance in the level of "smart" (clock speeds alone, slowest my phones cpu is "allowed" is
1.6Ghz x 4 cores (locked speed) 2.35Ghz on 4 cores (locked)
where even second gen Phenom II are able to drop their clocks to as low as 400Mhz while still being able to autooverclock in excess of 4.3Ghz on up to 6 cores 6 threads.
anyways... AMD seen what the industry needed and has been doing what they could "to be a business" but more than that, in my honest to god opinion, I see Dr Lisa as one of those "rare folks" that see the path that needs to be taken before all should fail, where all the others sit back and are more or less ok to play the same old pissing match.
I suppose 20+ years all the ups and downs with economy is not enough warning for folks, last 3 years has been $%^&$%^ brutal for the tech world, more or less except for AMD that has hit all its targets between the eyes (the only way to take down a bull)
More of everything for less, this way here "simple things" that me and you might like to do, like ripping multiple tracks and such at same time has become (with AMD) much more easy to have, now we are talking 8 core 16 thread at less overall power use than the average single core was many decades prior (125w vs say 45w, ok the new one uses more, but, it can crunch metadata at magnitudes more effective rate as well the old chip was always at its max power use (more or less) the modern ones sip power to max performance back and forth constantly.
That is my story and I am sticking to it, Ryzen to change the world.
Dragonstongue - Sunday, May 26, 2019 - link
I'm 4 Ryzen ......hmmmm AM4 Ryzen...say it twisted tongue or fast.... how unusual is that coinky-dink