DDR5 will be a boon for integrated graphics (such as AMD's APU lineup). DDR4 isn't quite fast enough to provide the Raw B/W for these parts to truly replace low-end dGPUs IMHO. DDR5-6400 dual-channel will provide over 100GB/s of raw bandwidth. But even entry-level DDR5 at around 4Gbps would be sufficient combined with arch and compression improvements in these dGPUs.
By the time DDR5 hits consumer market, ZEN 2 APU's should be available. At least I hope AMD will include new DRAM support. There's no reason to continue with DDR4.
ZEN 2 is socket compatible with ZEN so little chance that it will have DDR5 support. I mean it is not impossible but AMD would have needed to plan that in the pin configuration for AM4 back in 2016 when AMD was on lifesupport.
Yep, DDR5 won't come to AMD consumer platforms until past 2020. OTOH, this aligns with the stated start of mass production from this article, so no worries there. Seems like AMD planned this out very well. The part of me dreaming of a new APU-powered HTPC just wants it to arrive yesterday XD
Assuming AMD will stick to their annual release of CPU generations Zen 3 will be released in 2020 and Zen 4 will be released in 2021. Since Zen 3 will almost certainly be an optimized Zen 2 that will use the same socket, DDR5 will probably have to wait for Zen 4.
It should be a nice boost, otoh IGPUs and bottom end DGPUs will also be growing in size and bandwidth needs. I'd anticipate DDR* versions to remain badly bandwidth constrained for the foreseeable future.
While that's true, iGPUs have no real room to grow with DDR4. This could bring them into current AAAs @1080p60 Ultra (or above) territory, which would then likely mean 2020-2021 AAAs at 1080p60 medium-high or so. That sounds pretty dreamy to me.
DDR5 will presumably have to wait for Zen 4 CPUs, which are to be released in 2021 at the earliest. Zen 2 based ones next year will not support DDR5, Zen 3 in 2020 will merely be an optimized Zen 2 (and thus it's highly doubtful it will have DDR5 controllers and a new socket), while Zen 4 will be the next new design after Zen 2, with 2021 being long overdue for AMD to replace the current sockets.
The above applies to their mainstream and HEDT CPUs. Their server sockets have a zillion pins, many of which are surely reserved for future features (they have extra spare pins to support +32 more cores), so it might be possible to make backwards compatible motherboards with DDR5 support in 2020, with the DDR5 controllers added to the I/O die on the CPU side. The Zen 3 chiplets would probably require only a marginal redesign.
To sum up AMD will introduce DDR5 support in 2021 at the earliest in their Ryzen and TR CPUs and either 2020 or 2021 to their server CPUs.
There's no reason they couldn't build a chiplet + I/O design for AM4 that supports DDR4, and use the same chiplets with a different I/O block for AM5. So it isn't IMPOSSIBLE we'll see it prior to Zen 4. I'm not saying they will do this, but from a technical standpoint they could.
Also, why would they need to redesign the chiplets? The memory controller is in the I/O block.
I'm a bit puzzled. Looking at that I see what appear to be 10 dram chips and 1 something else on the dimm. Normally you'd expect to see 8/16 or 9/18 dram chips depending on if it's ECC or not; and only server ram would have an additional chip as a buffer (to let them put more dimms on the bus). The DDR5 micron demoed (related reading) has a normal looking 8 dram chips; so I'm wondering what's the deal with this Dimm's unusual appearance.
Is it related to "each DDR5 DIMM will feature two independent 32/40-bit channels (without/or with ECC)"?
That is, do you need two sets of (4+1) instead of one set of (8+1) memory chips to support ECC with two channels? I have no idea, but I was wondering the same thing.
That's a plausible theory anyway. And since the article says it's a registered (server class) dimm, it presumably is ECC. Doubling the BoM level ECC tax isn't good, but trying to play games to share a single ECC chip with 2 independent channels would probably have a significant performance impact.
I assume that DDR5 will also need a new chipset and probably a new socket. AMD's Zen 2 and 3 will still be on AM4. This pretty much rules out DDR5 support for Zen 2 and 3. So the earliest we can see DDR5 support is 2021 with Zen 4. At that time we probably also get an updated PCI-Express bus either v.4 or v.5.
With AMD's chiplet design, the microarchitecture of Zen 2 and 3 can be developed independently of the I/O chip that contains the memory controller, therefore all that's needed is a new platform and I/O chip, and Zen 2 could support DDR5, though they will definitely wait until Zen 3 since that will be ready by the time DDR5 is mass produced.
While they could wait until Zen 4, I doubt they will.
Correction from another anad article Zen 3 will use the same sockets as well. So Zen 4 is the earliest.
"IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides? MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change.
IC: So one might assume that an intercept might occur with Zen 4? MP: No comment (!)"
"We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change."~Mark Papermaster so no DDR5 until at least Zen 4.
Probably about the same in nanosecond terms as everything for the last 15+ years (which is to say 2x the bus speed once it matures, 2x the timing numbers). The reason we're beginning a 5th generation of double the read/write parallelism and data bus speeds is that the speed of reading/writing DRAM hit a wall around PC133. DDR4 has bus speeds upto ~30x faster, but the dram itself is only about 2x faster than what you had in your first ~1ghz PC.
I think that DDR2 was the last generation where the actual latency numbers were better than last generation. Since then it has taken longer and longer for the newer D-Rams to reach last generations actual latency. But there must be other benefits with higher total bandwidth? I mean, for non-realtime "predictable" processing where a bunch of numbers have to be crunched one after another, then bandwith must be more important than latency, right?
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AshlayW - Thursday, November 15, 2018 - link
DDR5 will be a boon for integrated graphics (such as AMD's APU lineup). DDR4 isn't quite fast enough to provide the Raw B/W for these parts to truly replace low-end dGPUs IMHO. DDR5-6400 dual-channel will provide over 100GB/s of raw bandwidth. But even entry-level DDR5 at around 4Gbps would be sufficient combined with arch and compression improvements in these dGPUs.Can't wait for DDR5. :D
AshlayW - Thursday, November 15, 2018 - link
fixing typo: in these iGPUs*tommo1982 - Thursday, November 15, 2018 - link
By the time DDR5 hits consumer market, ZEN 2 APU's should be available. At least I hope AMD will include new DRAM support. There's no reason to continue with DDR4.namechamps - Thursday, November 15, 2018 - link
ZEN 2 is socket compatible with ZEN so little chance that it will have DDR5 support. I mean it is not impossible but AMD would have needed to plan that in the pin configuration for AM4 back in 2016 when AMD was on lifesupport.Maybe Zen 3 in 2021 will use DDR5.
Valantar - Thursday, November 15, 2018 - link
Yep, DDR5 won't come to AMD consumer platforms until past 2020. OTOH, this aligns with the stated start of mass production from this article, so no worries there. Seems like AMD planned this out very well. The part of me dreaming of a new APU-powered HTPC just wants it to arrive yesterday XDSantoval - Friday, November 16, 2018 - link
Assuming AMD will stick to their annual release of CPU generations Zen 3 will be released in 2020 and Zen 4 will be released in 2021. Since Zen 3 will almost certainly be an optimized Zen 2 that will use the same socket, DDR5 will probably have to wait for Zen 4.DanNeely - Thursday, November 15, 2018 - link
It should be a nice boost, otoh IGPUs and bottom end DGPUs will also be growing in size and bandwidth needs. I'd anticipate DDR* versions to remain badly bandwidth constrained for the foreseeable future.Valantar - Thursday, November 15, 2018 - link
While that's true, iGPUs have no real room to grow with DDR4. This could bring them into current AAAs @1080p60 Ultra (or above) territory, which would then likely mean 2020-2021 AAAs at 1080p60 medium-high or so. That sounds pretty dreamy to me.Santoval - Thursday, November 15, 2018 - link
DDR5 will presumably have to wait for Zen 4 CPUs, which are to be released in 2021 at the earliest. Zen 2 based ones next year will not support DDR5, Zen 3 in 2020 will merely be an optimized Zen 2 (and thus it's highly doubtful it will have DDR5 controllers and a new socket), while Zen 4 will be the next new design after Zen 2, with 2021 being long overdue for AMD to replace the current sockets.The above applies to their mainstream and HEDT CPUs. Their server sockets have a zillion pins, many of which are surely reserved for future features (they have extra spare pins to support +32 more cores), so it might be possible to make backwards compatible motherboards with DDR5 support in 2020, with the DDR5 controllers added to the I/O die on the CPU side. The Zen 3 chiplets would probably require only a marginal redesign.
To sum up AMD will introduce DDR5 support in 2021 at the earliest in their Ryzen and TR CPUs and either 2020 or 2021 to their server CPUs.
Alexvrb - Thursday, November 15, 2018 - link
There's no reason they couldn't build a chiplet + I/O design for AM4 that supports DDR4, and use the same chiplets with a different I/O block for AM5. So it isn't IMPOSSIBLE we'll see it prior to Zen 4. I'm not saying they will do this, but from a technical standpoint they could.Also, why would they need to redesign the chiplets? The memory controller is in the I/O block.
DanNeely - Thursday, November 15, 2018 - link
I'm a bit puzzled. Looking at that I see what appear to be 10 dram chips and 1 something else on the dimm. Normally you'd expect to see 8/16 or 9/18 dram chips depending on if it's ECC or not; and only server ram would have an additional chip as a buffer (to let them put more dimms on the bus). The DDR5 micron demoed (related reading) has a normal looking 8 dram chips; so I'm wondering what's the deal with this Dimm's unusual appearance.rpg1966 - Thursday, November 15, 2018 - link
Is it related to "each DDR5 DIMM will feature two independent 32/40-bit channels (without/or with ECC)"?That is, do you need two sets of (4+1) instead of one set of (8+1) memory chips to support ECC with two channels? I have no idea, but I was wondering the same thing.
DanNeely - Thursday, November 15, 2018 - link
That's a plausible theory anyway. And since the article says it's a registered (server class) dimm, it presumably is ECC. Doubling the BoM level ECC tax isn't good, but trying to play games to share a single ECC chip with 2 independent channels would probably have a significant performance impact.Cpt.Planet - Thursday, November 15, 2018 - link
There are 10 DRAM ICs and a RCD. 4+1 ECC per channel. The chip in the middle is the RCD (registered clock driver) for RDIMM.5080 - Thursday, November 15, 2018 - link
I assume that DDR5 will also need a new chipset and probably a new socket. AMD's Zen 2 and 3 will still be on AM4. This pretty much rules out DDR5 support for Zen 2 and 3. So the earliest we can see DDR5 support is 2021 with Zen 4. At that time we probably also get an updated PCI-Express bus either v.4 or v.5.AAbattery - Thursday, November 15, 2018 - link
With AMD's chiplet design, the microarchitecture of Zen 2 and 3 can be developed independently of the I/O chip that contains the memory controller, therefore all that's needed is a new platform and I/O chip, and Zen 2 could support DDR5, though they will definitely wait until Zen 3 since that will be ready by the time DDR5 is mass produced.While they could wait until Zen 4, I doubt they will.
namechamps - Thursday, November 15, 2018 - link
AMD has said Zen 2 will use the AM4 socket. That pretty much precludes it from using DDR5. Zen 3 on the other hand may move to a new socket.namechamps - Thursday, November 15, 2018 - link
Correction from another anad article Zen 3 will use the same sockets as well. So Zen 4 is the earliest."IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides?
MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change.
IC: So one might assume that an intercept might occur with Zen 4?
MP: No comment (!)"
Alexvrb - Thursday, November 15, 2018 - link
Support for a socket does not preclude support for that socket plus another socket. Although, this would still mean Zen 3 at the earliest.porcupineLTD - Thursday, November 15, 2018 - link
"We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change."~Mark Papermasterso no DDR5 until at least Zen 4.
phoenix_rizzen - Friday, November 16, 2018 - link
SP3 socket for EPYC supports PCIe 3.0 and PCIe 4. There's an article on here that shows a prelim motherboard for EPYC2 with PCIe 4 slots.That will probably trickle down to TR3 socket for Threadripper. Not sure if it will reach AM4, though.
katsetus - Friday, November 16, 2018 - link
But the latency? Previous articles about DDR5 had appalling latency numbers.DanNeely - Friday, November 16, 2018 - link
Probably about the same in nanosecond terms as everything for the last 15+ years (which is to say 2x the bus speed once it matures, 2x the timing numbers). The reason we're beginning a 5th generation of double the read/write parallelism and data bus speeds is that the speed of reading/writing DRAM hit a wall around PC133. DDR4 has bus speeds upto ~30x faster, but the dram itself is only about 2x faster than what you had in your first ~1ghz PC.Magnus101 - Thursday, February 7, 2019 - link
I think that DDR2 was the last generation where the actual latency numbers were better than last generation. Since then it has taken longer and longer for the newer D-Rams to reach last generations actual latency.But there must be other benefits with higher total bandwidth?
I mean, for non-realtime "predictable" processing where a bunch of numbers have to be crunched one after another, then bandwith must be more important than latency, right?
tech_analyst - Friday, November 16, 2018 - link
Cool that they have some first pre-standard chips and the industry absolutely needs those DDR5 benefits.Still, DDR5 spec is not necessarily done or available yet, so pretty difficult for them to claim JEDEC-compliant. LOL
BurntMyBacon - Monday, November 19, 2018 - link
Not published is not the same as not finished.