If TSMC can be at 5nm before Intel gets to 10nm (which is equivalent sort of to TSMC 7nm) does that mean that Intel has REALLY lost process node advantage for the first time in 20+ years?
I don't think it's that so much as the company completely lost focus after the Haswell/Broadwell generation.
They spent $17B acquiring Altera...money which is effectively completely wasted in this era of customer foundry order ASIC's. They released Optane which so far as I can tell is making exactly zero progress in the market while eating up fab capacity.
The company really seems to be in chaos, which is bizarre for an organization that was the gold standard since basically Fairchild.
I don't believe Intel has lost its edge. I think this is more to do with business people making a decision to not move to 10nm because there is no competition. This allows them to still make their products in 14nm avoiding research cost and make huge profits until the competition catches up. This is terrible for technology but good for Intel's bank accounts
Absolutely not. Intel is a very paranoid business, operationally. They know that part of their leadership comes from having the leading edge nodes.
The fact is that they do not have enough 14nm capacity to satisfy the market demand now, due to not having migrated core products to 10nm already. 10nm is being redesigned to be slightly less dense but working, but it won't be ready until next year, potentially late in the year (or worse).
Intel will still make big profits for now due to also having good designs, but they have lost the manufacturing lead.
As far as I understand Intel is moving to use EUV for there 10nm node which likely won't reduce density like you stated. I suspect Intel's 10nm will land density wise somewhere between TSMC's 5nm and 7nm so really they aren't behind by much but they certainly are no longer leading.
I think you missed the memo. End of August or beginning of September, Intel ceded EUV to TSMC and Samsung fabs, saying they will not introduce EUV until 2021, which roughly coincides with Intel's 7nm time frame. The 10nm, before the gutting and making less dense, would have been only a couple percent over the theoretical density of TSMC. Meanwhile, TSMC put out Apple's 7nm chip, meaning they have the lead. Intel's 14nm++ is NOT more dense than 7nm at TSMC. So, in absolute terms, Intel is not the leading process, and some argue it has not been since the introduction of a TSMC 10nm production, with Intel's 14nm being comparable to other fab's 10nm, generally. Meanwhile, Intel's 10nm won't have products to market on the node until 2H 2019.
Intel's 10nm doesn't use EUV and will have worse density than TSMC 7nm. Originally it would be about the same density, but the feature sizes have been relaxed to get it working. This is like the 14+ and 14++ processes which also have worse density than the original 14nm process.
While it might be true that Intel's 10nm is better than TSMC's 1st 7nm (which I doubt somewhat - I think they're probably roughly comparable in density), the fact of the matter is that Intel was shipping 14nm processors in bulk when TSMC was doing 20nm, and Intel had planned to be at 10nm before TSMC was doing any 7nm.
At this point, TSMC will be on its 2nd gen 7nm before Intel's 10nm moves past a few niche processors.
I don't think Intel is BEHIND in manufacturing by that much, but they're certainly stumbling, and they've lost all, or most of their lead.
Unless Intel has some amazing hat trick, like a new, unannounced, revolutionary architecture right around the corner (it isn't on the roadmaps) then they have lost microarchitecture advantage to AMD (Zen is clearly more power efficient in performance-per-watt while being more scalable) and they have lost manufacturing advantage to TSMC, who is already neck and neck with Intel and next year will surpass them on process node. Neither company accurately discloses yields but it can be assumed TSMC's are better because Intel's prices continue to go up while profit margin's remain static.
TSMC 16nm is slightly less dense than Intel 14nm as you would expect. TSMC 10nm is without a doubt significantly denser than Intel 14nm, like the number suggests. TSMC 7nm will be denser than the Intel 10nm process when it finally goes into volume production.
So yes, the process nm is in fact a reasonable estimate of relative density. That's despite it being a made up number for about a decade... Simply put no company could get away with claiming to have a 1nm process when it's similar to other 10nm processes.
Yes and people find it hard to believe when I do a similar post. Intel's revenue has been the highest ever and their stock price never dropped drastically. Investors know what Intel is doing.
I predicted long ago when they started using TIM on their chips but overclockers get insane results once delidded. It appeared that Intel isn't doing their best and withhold the chips' ability.
So is the rest of the semiconductor industry thanks to the Trump Administration's escalating conflict with China over trade. The semiconductor industry is acting like a bellwether for the conflict in the markets.
Please explain "They released Optane which so far as I can tell is making exactly zero progress in the market while eating up fab capacity" your comment lost all credibility in my eyes unless you have any info on this "Fab" that lost capacity. Last time I checked this product was being made with Micron in a Fab tooled for memory not logic.
There are two (well, lots, but the two biggest) hard problems facing scaling down processes further: patterning small features, and having those small features work. Patterning them is being tackled by EUV. having them work is being tackled with non-copper interconnects. TSMC decided to start with getting EUV online and tweaking Cu as long as they can. Intel decided to get Cobalt working first and leave EUV for later.
So far, Intel have Co interconnects kinda-sorta working but not really ready for volume, and nobody has EUV shipping at all yet. Further scaling is probably going to require both to be ready to really start pushing process scaling down again (and start moving into GAAFETs and the like). Who ends up 'ahead' depends on whether it is faster for Intel to catch up with EUV rollout once the bugs are worked out, or whether it is faster for others to analyses and duplicate Intel's work on Co.
Intel has already lost their historical ~3 year manufacturing advantage. Their 10nm process is similar to TSMC's 7nm which is already shipping and pumping out working silicon (Apple's A12, AMD's Epyc Rome/Zen2, etc).
We'll see what Icelake is capable of when it is released and how well Intel's revised and relaxed 10nm process (original 10nm has been scrapped AFAIK) works.
The i3 8121u in 10nm the first is a disaster of epic proportions (70mm² dual core chip with completely disabled iGPU and worse clocks/TDP than similar 14++ parts) that has not been reviewed at all, anywhere. It only shipped in an obscure Lenovo laptop just to claim 10nm is working and avoiding lawsuits.
Intel is already doing "risk production" with 10 nm but yeah, Intels 10 nm will compete against 7FF+ and at least for a short period against 5FF until Intel goes EUV with 7 nm...
Judging by the big number of EUV machines sold to Intel, TSMC and Samsung none of these will have a big advantage once real EUV( more than one layer) comes into play.
According to a June '18 article at SemiWiki Intel plans to be just as aggressive when they move to 7nm - which I believe is still scheduled for a... 2020 release on their roadmap, which surely requires an update. They plan a further 2.4x increase in transistor density, i.e. about ~250 MTr/mm^2. That density is much higher than TSMC's and Samsung's expected transistor density at 5nm, and it is even slightly higher than TSMC's and Samsung's projected transistor density at 3nm.
What I mean is that Intel still plans to shoot way too far, as if they learnt nothing from the overambitious specs of their 10nm node which resulted in repeated delays. Due to the huge jump in density SemiWiki expects that there is no way they can go so small with FinFet, so they predict a switch to HNS (Horizontal Nanosheets, a form of GAA - Gate All Around). Perhaps HNS, along with EUV on almost the entire stack, will help them achieve this. But even if they do there is no way they manage to do it before 2022 at the earliest, 2023 more realistically.
By that time Samsung and TSMC will have long deployed 5nm, which is going to be much denser than Intel's 10nm (TSMC's anyway, Samsung's is expected to be only slightly denser) and they will either be on the verge of mass releasing 3nm or they will have already released it, depending on how much Intel's 7nm node is delayed and the potential delays of the foundries.
Intel was already left behind the foundries due to the delay of 10nm and TSMC's release of 7nm (the same applied to Intel's 14nm vs the foundries' 10nm, but to a lesser degree), will probably match them for a few quarters when they release 10nm based CPUs in late 2019, and they will again be left behind from around mid 2020 (when TSMC plans to release 5nm in high volume) until 2022 (i.e. 2023), when Intel releases their 7nm node in high volume.
All the above only assume a "quantitative" lead in transistor density, and ignore more complex qualitative metrics like LER (line edge rounghness), transistor materials, leakage, power efficiency etc etc Intel might still lead in some (or all) of these aspects.
"which indicates that N7+ is going to be a “long” node." - I haven't come across that, in spite of being an avid Anand and Ars reader - long life? Google isn't helping much.
"the leading suspects are obvious." - would it have killed you to mention them? Just sounds snobby leaving it hanging like that.
"long node" and "short node" are terms of insult, not terms of information... iwod is correct. Nodes (at least for fabs) last effectively forever. Look at TSMC, they're still offering .13µ if you want that, and terms that were claimed as "short nodes" at the time, like 20nm, are still doing just fine.
To the extent that "short node" means ANYTHING, it means that it won't last long AS THE LEADING EDGE. ie there's a kind of cadence that some nodes stay leading edge for one year (20 nm, 10 nm), some stay leading edge for two years (16nm, 7nm). Does this prove anything other than "three does not divide into two exactly"? Not really. But if you're in the business of trying to talk down the fabs (or their customers), you latch onto whatever nonsense you can. "short node" sounds bad --- must imply a weakness of some sort, no? Hence a whole lot of idiotic chatter around how TSMC 20nm or 10nm (or its client parts, like the relevant Apple chips) were going to suck. Basically exactly the same phenomenon as when people who know nothing about finance feel educated and entitled to an opinion by hearing that an exchange rate is "strong".
TSMC and Apple has been working together on leading node for a few years now. So both Roadmap are perfectly aligned with each other. 7nm+ for 2019 iPhone, and 5nm for 2020 iPhone.
"Long Node" simply means a node./ Fab tech won't be discontinued soon. 10nm are short node. TSMC provides an upgrade path where customer on 28nm can upgrade to 20nm > 12nm > 7nm when they see fits. Long node also usually means they are cost optimised and constantly being refined and improved, for TSMC that is cheaper to produce, and in the long run cheaper for customer to use.
Everything have seen indicates that N7+ is going to be a short node, as its sole purpose is to getting the EUV scanner working for 5nm. And also that Apple is not going to use it, but is going to use 7nm twice and then 5nm
2018 iPhone uses N7, 2019 will use N7+, 2020 will use N5 -- you can see that TSMC's mass production schedules perfectly line up with Apple's. The reason is increasing gate density means cheaper chips, or more functionality/features for the same cost chip -- this is true even with rising wafer cost, gate density still increases faster than wafer cost.
Same as TSMC's 16nm, which was turned into 16FF, 16FF+, 16FFC, 12FFC, and 12FFN over the last 4 years (and you could even call 16nm a varaint of 20nm if you were feeling uncharitable).
It was also reported 5nm EUV needed multipatterning (same as current 7nm). So 7nm+ probably needs same amount of multipatterning as 10nm. It's unlikely there are enough EUV tools for the same volume as before.
Lithography fanboy-ism is an interesting phenomenon. Lots of apples and oranges. Intel certainly does seem to be more confused/distracted than ever. Their marketing, channel support, and product line is frankly all over the place. Get it together Intel!
No, N5 EUV is single-patterned. The colouring is not because of multi-patterning, it's because of the 3:2 pitch ratio between poly (underlying cell) and metal (interconnect), so there are 4 different versions of each cell depending on how they fit on the metal grid and what cell is next to them -- the metal position walks past the poly, and this also depends on the width of the cell. The tools use colouring to sort all this out.
Yes, but not because of multiple EUV exposures, it's because of the mismatched metal/poly pitch. 5nm definitely uses single-exposure EUV on all layers.
Please could you clarify what is meant by "risk production" in the context of chip manufacturing (yes, I've already googled it). Does it mean they're putting real chip designs through the production process as a sort of pipe cleaner?
More useful is to consider the gap between when "risk production" is announced and we see a large volume of chips commercially available.
TSMC 7nm started risk production in April 2017, and we see volume shipments 17 months later. 10nm was about the same. 16nm risk production started Nov 2013, Apple chips were almost 2 years later.
Of course there are issues of schedule alignment and the need to build up a huge stockpile of chips before any company (let alone Apple) can release a product. But judging by history it seems possible that Apple can pick up 7+ in 2019. It would be tight, but assuming the ONLY real changes are the EUV, and that's under control (which may be optimistic...)
5N is more interesting. I had assumed (before I looked at the historical numbers) that this would mean Apple in 2020, with early iPad chips perhaps in Q2 2020. That still seems possible, within the historical bounds (the A10X was released about 14 months after risk 10nm production) but both schedules seem tight, especially if 5nm has a lot of new features. My guess is Apple will still make the iPhone deadline, but an early iPad chip in 2020 might be too much to expect?
If TSMC is the first to successfully use EUV in routine production, before Intel, this indeed will be a major milestone. I've been very reluctant to conclude that Intel has fallen behind because of its apparent 10 nm issues, but now it appears that there may be substance to it. However, there are also recent Intel announcements that imply that 10 nm is now back on track as well.
Both TSMC and Samsung will have EUV in limited use on 7nm+ nodes with production next year, but with EUV only on ~5 layers, mainly for contacts/vias where a pellicle isn't essential. Both are targeting full-EUV for 5nm the year after (2020). Intel are nowhere with EUV because they've been running round like chickens with their heads chopped off trying (and failing) to fix 10nm.
The recent Intel announcements about 10nm are papering over the cracks -- yes they're working on improving things, yes they're still aiming to have IceLake (for laptops) out in late 2019, but the process won't be good enough to yield big server chips until late 2020, which is 18 months after AMD Rome and four years after when this was initially forecast.
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stanleyipkiss - Tuesday, October 9, 2018 - link
If TSMC can be at 5nm before Intel gets to 10nm (which is equivalent sort of to TSMC 7nm) does that mean that Intel has REALLY lost process node advantage for the first time in 20+ years?shabby - Tuesday, October 9, 2018 - link
Looks like, they made a bet and lost.Sahrin - Tuesday, October 9, 2018 - link
I don't think it's that so much as the company completely lost focus after the Haswell/Broadwell generation.They spent $17B acquiring Altera...money which is effectively completely wasted in this era of customer foundry order ASIC's. They released Optane which so far as I can tell is making exactly zero progress in the market while eating up fab capacity.
The company really seems to be in chaos, which is bizarre for an organization that was the gold standard since basically Fairchild.
sharath.naik - Wednesday, October 10, 2018 - link
I don't believe Intel has lost its edge. I think this is more to do with business people making a decision to not move to 10nm because there is no competition. This allows them to still make their products in 14nm avoiding research cost and make huge profits until the competition catches up. This is terrible for technology but good for Intel's bank accountspsychobriggsy - Wednesday, October 10, 2018 - link
Absolutely not. Intel is a very paranoid business, operationally. They know that part of their leadership comes from having the leading edge nodes.The fact is that they do not have enough 14nm capacity to satisfy the market demand now, due to not having migrated core products to 10nm already. 10nm is being redesigned to be slightly less dense but working, but it won't be ready until next year, potentially late in the year (or worse).
Intel will still make big profits for now due to also having good designs, but they have lost the manufacturing lead.
FreckledTrout - Wednesday, October 10, 2018 - link
As far as I understand Intel is moving to use EUV for there 10nm node which likely won't reduce density like you stated. I suspect Intel's 10nm will land density wise somewhere between TSMC's 5nm and 7nm so really they aren't behind by much but they certainly are no longer leading.ajc9988 - Wednesday, October 10, 2018 - link
I think you missed the memo. End of August or beginning of September, Intel ceded EUV to TSMC and Samsung fabs, saying they will not introduce EUV until 2021, which roughly coincides with Intel's 7nm time frame. The 10nm, before the gutting and making less dense, would have been only a couple percent over the theoretical density of TSMC. Meanwhile, TSMC put out Apple's 7nm chip, meaning they have the lead. Intel's 14nm++ is NOT more dense than 7nm at TSMC. So, in absolute terms, Intel is not the leading process, and some argue it has not been since the introduction of a TSMC 10nm production, with Intel's 14nm being comparable to other fab's 10nm, generally. Meanwhile, Intel's 10nm won't have products to market on the node until 2H 2019.FreckledTrout - Thursday, October 11, 2018 - link
I did miss that memo :)Wilco1 - Wednesday, October 10, 2018 - link
Intel's 10nm doesn't use EUV and will have worse density than TSMC 7nm. Originally it would be about the same density, but the feature sizes have been relaxed to get it working. This is like the 14+ and 14++ processes which also have worse density than the original 14nm process.sing_electric - Thursday, October 11, 2018 - link
While it might be true that Intel's 10nm is better than TSMC's 1st 7nm (which I doubt somewhat - I think they're probably roughly comparable in density), the fact of the matter is that Intel was shipping 14nm processors in bulk when TSMC was doing 20nm, and Intel had planned to be at 10nm before TSMC was doing any 7nm.At this point, TSMC will be on its 2nd gen 7nm before Intel's 10nm moves past a few niche processors.
I don't think Intel is BEHIND in manufacturing by that much, but they're certainly stumbling, and they've lost all, or most of their lead.
Samus - Wednesday, October 10, 2018 - link
Unless Intel has some amazing hat trick, like a new, unannounced, revolutionary architecture right around the corner (it isn't on the roadmaps) then they have lost microarchitecture advantage to AMD (Zen is clearly more power efficient in performance-per-watt while being more scalable) and they have lost manufacturing advantage to TSMC, who is already neck and neck with Intel and next year will surpass them on process node. Neither company accurately discloses yields but it can be assumed TSMC's are better because Intel's prices continue to go up while profit margin's remain static.Wilco1 - Wednesday, October 10, 2018 - link
"TSMC, who is already neck and neck with Intel and next year will surpass them on process node"What?!? TSMC surpassed Intel several years ago with 10nm.
Samus - Thursday, October 11, 2018 - link
>>"TSMC, who is already neck and neck with Intel and next year will surpass them on process node">What?!? TSMC surpassed Intel several years ago with 10nm.
TSMC 10nm does not equal Intel 10nm, the gate pitch is closer to Intel's 14nm.
TSMC 7nm is a smaller pitch than Intel 10nm, but both are otherwise very similar.
The process node nm doesn't mean the density of the imaged area is the same, it's simply a definition of lithography.
Wilco1 - Thursday, October 11, 2018 - link
TSMC 16nm is slightly less dense than Intel 14nm as you would expect. TSMC 10nm is without a doubt significantly denser than Intel 14nm, like the number suggests. TSMC 7nm will be denser than the Intel 10nm process when it finally goes into volume production.So yes, the process nm is in fact a reasonable estimate of relative density. That's despite it being a made up number for about a decade... Simply put no company could get away with claiming to have a 1nm process when it's similar to other 10nm processes.
zodiacfml - Wednesday, October 10, 2018 - link
Yes and people find it hard to believe when I do a similar post. Intel's revenue has been the highest ever and their stock price never dropped drastically. Investors know what Intel is doing.I predicted long ago when they started using TIM on their chips but overclockers get insane results once delidded. It appeared that Intel isn't doing their best and withhold the chips' ability.
Samus - Wednesday, October 10, 2018 - link
Intel stock is trading at a 6 month low right now...3DoubleD - Thursday, October 11, 2018 - link
So is the rest of the semiconductor industry thanks to the Trump Administration's escalating conflict with China over trade. The semiconductor industry is acting like a bellwether for the conflict in the markets.[email protected] - Thursday, October 11, 2018 - link
TSMC 7FF is is 2.5X denser than Intel 14nm, and that by Intel owns metric. TMSC 7FF also got a much denser SRAM cell.TSMC 5FF is 1.75X denser than Intel 10nm, SRAM cell density on TSMC 5FF is almost 2x of what you have on Intel 10nm.
That is great competition and what it means for Intel we will see by the following months.
Dariusbird - Wednesday, October 10, 2018 - link
Please explain "They released Optane which so far as I can tell is making exactly zero progress in the market while eating up fab capacity" your comment lost all credibility in my eyes unless you have any info on this "Fab" that lost capacity. Last time I checked this product was being made with Micron in a Fab tooled for memory not logic.edzieba - Wednesday, October 10, 2018 - link
There are two (well, lots, but the two biggest) hard problems facing scaling down processes further: patterning small features, and having those small features work. Patterning them is being tackled by EUV. having them work is being tackled with non-copper interconnects. TSMC decided to start with getting EUV online and tweaking Cu as long as they can. Intel decided to get Cobalt working first and leave EUV for later.So far, Intel have Co interconnects kinda-sorta working but not really ready for volume, and nobody has EUV shipping at all yet. Further scaling is probably going to require both to be ready to really start pushing process scaling down again (and start moving into GAAFETs and the like). Who ends up 'ahead' depends on whether it is faster for Intel to catch up with EUV rollout once the bugs are worked out, or whether it is faster for others to analyses and duplicate Intel's work on Co.
WatcherCK - Tuesday, October 9, 2018 - link
Intel is a "too big to fail" company that can appeal to the power of that white house and its occupants if it really came to that...HighTech4US - Tuesday, October 9, 2018 - link
Yesaj7 - Wednesday, October 10, 2018 - link
Really? What’s their whine line?.vodka - Tuesday, October 9, 2018 - link
Intel has already lost their historical ~3 year manufacturing advantage. Their 10nm process is similar to TSMC's 7nm which is already shipping and pumping out working silicon (Apple's A12, AMD's Epyc Rome/Zen2, etc).We'll see what Icelake is capable of when it is released and how well Intel's revised and relaxed 10nm process (original 10nm has been scrapped AFAIK) works.
The i3 8121u in 10nm the first is a disaster of epic proportions (70mm² dual core chip with completely disabled iGPU and worse clocks/TDP than similar 14++ parts) that has not been reviewed at all, anywhere. It only shipped in an obscure Lenovo laptop just to claim 10nm is working and avoiding lawsuits.
brakdoo - Tuesday, October 9, 2018 - link
Intel is already doing "risk production" with 10 nm but yeah, Intels 10 nm will compete against 7FF+ and at least for a short period against 5FF until Intel goes EUV with 7 nm...Judging by the big number of EUV machines sold to Intel, TSMC and Samsung none of these will have a big advantage once real EUV( more than one layer) comes into play.
Santoval - Wednesday, October 10, 2018 - link
According to a June '18 article at SemiWiki Intel plans to be just as aggressive when they move to 7nm - which I believe is still scheduled for a... 2020 release on their roadmap, which surely requires an update. They plan a further 2.4x increase in transistor density, i.e. about ~250 MTr/mm^2. That density is much higher than TSMC's and Samsung's expected transistor density at 5nm, and it is even slightly higher than TSMC's and Samsung's projected transistor density at 3nm.What I mean is that Intel still plans to shoot way too far, as if they learnt nothing from the overambitious specs of their 10nm node which resulted in repeated delays. Due to the huge jump in density SemiWiki expects that there is no way they can go so small with FinFet, so they predict a switch to HNS (Horizontal Nanosheets, a form of GAA - Gate All Around). Perhaps HNS, along with EUV on almost the entire stack, will help them achieve this. But even if they do there is no way they manage to do it before 2022 at the earliest, 2023 more realistically.
By that time Samsung and TSMC will have long deployed 5nm, which is going to be much denser than Intel's 10nm (TSMC's anyway, Samsung's is expected to be only slightly denser) and they will either be on the verge of mass releasing 3nm or they will have already released it, depending on how much Intel's 7nm node is delayed and the potential delays of the foundries.
Intel was already left behind the foundries due to the delay of 10nm and TSMC's release of 7nm (the same applied to Intel's 14nm vs the foundries' 10nm, but to a lesser degree), will probably match them for a few quarters when they release 10nm based CPUs in late 2019, and they will again be left behind from around mid 2020 (when TSMC plans to release 5nm in high volume) until 2022 (i.e. 2023), when Intel releases their 7nm node in high volume.
All the above only assume a "quantitative" lead in transistor density, and ignore more complex qualitative metrics like LER (line edge rounghness), transistor materials, leakage, power efficiency etc etc Intel might still lead in some (or all) of these aspects.
t_oven - Wednesday, October 10, 2018 - link
TSMC is at 7nm while Intel still at 14nm now, so they already lost in term of process node. Why do you need to wait for 5nm?Wilco1 - Wednesday, October 10, 2018 - link
Indeed. Intel lost its lead years ago - TSMC 10nm was already much denser than Intel 14nm.JKflipflop98 - Saturday, October 13, 2018 - link
Don't worry about good ol' Intel.You're gonna be blown away with what's coming out of their pipe.
Stochastic - Tuesday, October 9, 2018 - link
Is it safe to assume that 7FF+ will form the foundation for next-gen consoles?overseer - Wednesday, October 10, 2018 - link
Very likely, given a rumored 2021 PS5 launch. Even 7FF can be quite durable, and just slightly weaker than 7FF+.gfkBill - Tuesday, October 9, 2018 - link
"which indicates that N7+ is going to be a “long” node." - I haven't come across that, in spite of being an avid Anand and Ars reader - long life? Google isn't helping much."the leading suspects are obvious." - would it have killed you to mention them? Just sounds snobby leaving it hanging like that.
aryonoco - Tuesday, October 9, 2018 - link
Long life, a node that will have a longer lifespan. Compare TSMC's 28nm vs 20nm. Or their 16nm vs their 10nm.Usual suspects are Apple and Huawei (HiSilicon).
name99 - Wednesday, October 10, 2018 - link
"long node" and "short node" are terms of insult, not terms of information...iwod is correct. Nodes (at least for fabs) last effectively forever. Look at TSMC, they're still offering .13µ if you want that, and terms that were claimed as "short nodes" at the time, like 20nm, are still doing just fine.
To the extent that "short node" means ANYTHING, it means that it won't last long AS THE LEADING EDGE. ie there's a kind of cadence that some nodes stay leading edge for one year (20 nm, 10 nm), some stay leading edge for two years (16nm, 7nm).
Does this prove anything other than "three does not divide into two exactly"? Not really. But if you're in the business of trying to talk down the fabs (or their customers), you latch onto whatever nonsense you can. "short node" sounds bad --- must imply a weakness of some sort, no? Hence a whole lot of idiotic chatter around how TSMC 20nm or 10nm (or its client parts, like the relevant Apple chips) were going to suck.
Basically exactly the same phenomenon as when people who know nothing about finance feel educated and entitled to an opinion by hearing that an exchange rate is "strong".
iwod - Tuesday, October 9, 2018 - link
TSMC and Apple has been working together on leading node for a few years now. So both Roadmap are perfectly aligned with each other. 7nm+ for 2019 iPhone, and 5nm for 2020 iPhone."Long Node" simply means a node./ Fab tech won't be discontinued soon. 10nm are short node. TSMC provides an upgrade path where customer on 28nm can upgrade to 20nm > 12nm > 7nm when they see fits. Long node also usually means they are cost optimised and constantly being refined and improved, for TSMC that is cheaper to produce, and in the long run cheaper for customer to use.
Speedfriend - Wednesday, October 10, 2018 - link
Everything have seen indicates that N7+ is going to be a short node, as its sole purpose is to getting the EUV scanner working for 5nm. And also that Apple is not going to use it, but is going to use 7nm twice and then 5nmIJD - Wednesday, October 10, 2018 - link
2018 iPhone uses N7, 2019 will use N7+, 2020 will use N5 -- you can see that TSMC's mass production schedules perfectly line up with Apple's. The reason is increasing gate density means cheaper chips, or more functionality/features for the same cost chip -- this is true even with rising wafer cost, gate density still increases faster than wafer cost.hechacker1 - Thursday, October 11, 2018 - link
Just thinking what a beast of an iPhone or iPad will best at 2020. It absolutely will be able to replace a Mac.edzieba - Wednesday, October 10, 2018 - link
Same as TSMC's 16nm, which was turned into 16FF, 16FF+, 16FFC, 12FFC, and 12FFN over the last 4 years (and you could even call 16nm a varaint of 20nm if you were feeling uncharitable).Anymoore - Tuesday, October 9, 2018 - link
It was also reported 5nm EUV needed multipatterning (same as current 7nm). So 7nm+ probably needs same amount of multipatterning as 10nm. It's unlikely there are enough EUV tools for the same volume as before.RU482 - Wednesday, October 10, 2018 - link
Lithography fanboy-ism is an interesting phenomenon. Lots of apples and oranges.Intel certainly does seem to be more confused/distracted than ever. Their marketing, channel support, and product line is frankly all over the place.
Get it together Intel!
Anymoore - Wednesday, October 10, 2018 - link
5nm uses multipatterning with EUV: https://www.semiwiki.com/forum/content/7759-top-10... look under item (4)IJD - Wednesday, October 10, 2018 - link
No, N5 EUV is single-patterned. The colouring is not because of multi-patterning, it's because of the 3:2 pitch ratio between poly (underlying cell) and metal (interconnect), so there are 4 different versions of each cell depending on how they fit on the metal grid and what cell is next to them -- the metal position walks past the poly, and this also depends on the width of the cell. The tools use colouring to sort all this out.Anymoore - Wednesday, October 10, 2018 - link
That's not what coloring is for. "the M1 layer requires (full) multipatterning color assignment"IJD - Wednesday, October 10, 2018 - link
Yes, but not because of multiple EUV exposures, it's because of the mismatched metal/poly pitch. 5nm definitely uses single-exposure EUV on all layers.Anymoore - Wednesday, October 10, 2018 - link
Did you miss the word "multipatterning"? Single exposure uses no coloring. Color doesn't cross layers.r3loaded - Wednesday, October 10, 2018 - link
Please could you clarify what is meant by "risk production" in the context of chip manufacturing (yes, I've already googled it). Does it mean they're putting real chip designs through the production process as a sort of pipe cleaner?name99 - Wednesday, October 10, 2018 - link
More useful is to consider the gap between when "risk production" is announced and we see a large volume of chips commercially available.TSMC 7nm started risk production in April 2017, and we see volume shipments 17 months later.
10nm was about the same.
16nm risk production started Nov 2013, Apple chips were almost 2 years later.
Of course there are issues of schedule alignment and the need to build up a huge stockpile of chips before any company (let alone Apple) can release a product. But judging by history it seems possible that Apple can pick up 7+ in 2019. It would be tight, but assuming the ONLY real changes are the EUV, and that's under control (which may be optimistic...)
5N is more interesting. I had assumed (before I looked at the historical numbers) that this would mean Apple in 2020, with early iPad chips perhaps in Q2 2020. That still seems possible, within the historical bounds (the A10X was released about 14 months after risk 10nm production) but both schedules seem tight, especially if 5nm has a lot of new features.
My guess is Apple will still make the iPhone deadline, but an early iPad chip in 2020 might be too much to expect?
quadibloc - Sunday, October 14, 2018 - link
If TSMC is the first to successfully use EUV in routine production, before Intel, this indeed will be a major milestone. I've been very reluctant to conclude that Intel has fallen behind because of its apparent 10 nm issues, but now it appears that there may be substance to it. However, there are also recent Intel announcements that imply that 10 nm is now back on track as well.IJD - Friday, October 19, 2018 - link
Both TSMC and Samsung will have EUV in limited use on 7nm+ nodes with production next year, but with EUV only on ~5 layers, mainly for contacts/vias where a pellicle isn't essential. Both are targeting full-EUV for 5nm the year after (2020). Intel are nowhere with EUV because they've been running round like chickens with their heads chopped off trying (and failing) to fix 10nm.The recent Intel announcements about 10nm are papering over the cracks -- yes they're working on improving things, yes they're still aiming to have IceLake (for laptops) out in late 2019, but the process won't be good enough to yield big server chips until late 2020, which is 18 months after AMD Rome and four years after when this was initially forecast.