I agree that the 4x4 10+2+4 layout doesn't make sense if they're going to put 8 cores in next gen mainstream parts. I'm not convinced that Intel will only have a single HEDT/Xeon layout in the future. Instead, I'd expect both the LCC and HCC meshes to grow.
A 5x4 layout for LCC could cover 10/12/14 core options at the lower end of the range.
HCC needs to grow too, a 5x6 layout - up from 4x6 - would add room for 2 more UPI lanes or 16 more PCIe lanes (depending on which Intel judges most needed), and 23 cores. If the odd core count itself is a problem, they could leave connectivity the same and offer 24 cores instead.
XCC would need to grow too, going from 6x6 to 6x8 would let them do 40 cores with IO unchanged, or 36 if they decide to add more ram/PCIe/UPI connections. More memory controllers might be a good option so they could slot in lots of Optane DIMMs while still having having plenty of DRAM available for application code and data that doesn't need to be persisted and which changes too frequently for Optane.
I'm just thankful to AMD for forcing Intel to move from the 4 core BS that intel milked for almost a decade. Competition does wonderful things. Intel needed the kick in the butt.
I doubt AMD had anything to do with that. Where they absolutely had an effect is with pricing, but the existence of the 6 core part was a long time coming. And the "4 core" stuff wasn't BS -- Intel pursued graphics over core count, because it made more sense to them.
It was likely that we'd have seen a 6 core part on 10nm, but due to delays, we saw that come on 14nm so that there was something new to keep OEMs happy.
I hear this argument a lot, that Intel had to plan for it way before now so it could not have been AMD that caused it. If I had to guess Intel had 6-core designs for mainstream CPU's for at least two generations back. It's not like they got a new process node and found all this extra die space, no they are still running on 14nm and have a cheap 6-core CPU now. The fact that we see 6 cores on the mainstream CPU's is directly attributable to AMD aka competition.
They had the configurations "waiting in the wings" but as FreckledTrout points out they had no intention of moving 6+ cores into the mainstream quite this soon. Now they're talking 8 cores on a mainstream platform.
If you buy the official company line, it's all just a big coincidence. Indeed, they ignore products from other companies, plowing ahead with blinders on, totally isolated from the outside world.
Based on the testimonials of former Intel employees the "blinders on" mentality does exist, but it's more of a problem at a higher level of design (see the 10nm debacle due to stubbornness) than consumer facing product segmentation.
"Intel pursued graphics over core count, because it made more sense to them."
What? Intel integrated graphics are like 2 generations behind AMD APUs. If you mean they pursued discrete graphics instead, that commitment of resources happened after ~8 years of 4-core parts being the top of the mainstream offerings.
The point was that their graphics core count (and width) continued to increase as the manufacturing node decreased, even while their mainstream CPU core counts remained constant. So, it looks an awful lot like they spent much of the additional silicon budget afforded by die shrinks to grow their iGPU instead of adding more CPU cores.
In 2010, their 32 nm Nehalem CPUs had Gen5 iGPUs with 12 EUs, each featuring 4-wide SIMD. In 2012, their 22 nm Ivy Bridge CPUs had Gen7 iGPUs with 16 EUs, each featuring 8-wide SIMD. In 2013, Haswell extended the mainstream up to 20 EUs. In 2015, their 14 nm Broadwell CPUs had Gen8 iGPUs with 24 EUs.
Their mainstream CPUs are still at 14 nm and have iGPUs with 24 EUs.
"Intel also uses it in the upcoming Xeon+FPGA products to combine two chips in a single package using an intra-package connection, but it comes at the expense of limiting those Xeon Gold processors down to two sockets rather than four"
Oh yeah, Intel is SO FAR BEHIND AMD because their on-package FPGA products are "cripplingly limited" to the exact same number of sockets that the highest-end AMD Zen2 based Epyc servers will support when they finally launch.
Oh, and those servers won't exactly have FPGAs or anything other than vanilla x86 cores on them either.
Please reread. Ian's statement is completely judgement free. And it's true: this design is "limiting" those Xeons to 2 rather than 4 socket configurations in the truest sense of the word: they simply can't be used for 4 sockets, so they're limited. That's the cost Intel currently has to pay for a multi chip package.
Nowhere does Ian say this would be bad or inferior to AMD.
Ian is certainly no AMD fanboy. Don't forget that he "forgot" to cover the AMD Threadripper/EPYC launch last year for more than 2 weeks. Which is about 2 weeks longer than any other tech website worth mentioning.
And when he finally covered it along with some other AMD review the Anandtech front page was immediately flooded with more than 2 dozen meaningless press releases of random Intel motherboard launches and other such irrelevant news that pushed the AMD articles to the bottom in less than half a day.
So definitely not an AMD fanboy. If anything he's being a little soft on Intel by not pointing out that one of Intel's the marching hymns was that they cater for the 4S market. So not being able to do that leaves them in the unenviable position of being substantially more expensive than AMD while catering to the exact same use cases.
Fortunately there's always some "incentive" program just round the corner to keep OEMs from jumping to quickly on the AMD bandwagon until Intel has something to respond with.
And I'm sure they will. Contrary to what many editors on plenty of tech sites insist on claiming, the "improvement pool" isn't tapped out. Fabrication might be more challenging but on the architecture side there plenty of room to improve. And Intel was always able to do that, just not willing due to lack of competition.
What arguments do you have to support the statement that the improvement pool is not tapped out then?
The reason CPU performance and IPC bumps have stagnated is certainly not because the pool is full and AMD releasing Zen with a very similar IPC supports that idea. So you must have one hell of a source to say otherwise right now.
That's not how the burden of proof works. So I expect all those Ziff Davis "journalists" who claimed "IPC can't improve" or "it's too expensive to put more than 4-6 cores on a die" to support the claims, not for everyone else to try to rebuff them.
Time has proven again and again that the reason for stagnation is almost always lack of competition and insisting on profit margins.
Plus there are fewer physical limitations to how well you can design a CPU architecture than say building atom scale transistors.
That statement had nothing at all to do with AMD though. It was just an observation that Intel sacrificed external communication lanes to set up the intra-package connect with the FPGA, when they had the option of a design tweak to maintain the same count of UPI connections externally.
The closest that ever gets to EPYC is that the 2-core solution for EPYC servers follows a similar mentality of using their infinity fabric lanes for socket-to-socket communication such that single socket and dual socket EPYC platforms have the same number of external lanes exposed to the system.
Thanks Ian, I really liked this article. Intel should have killed LCC on HEDT say 2-3 years ago but then they "should" have also had 6-8 core minatream parts. With no competition the milking of 4 core 14nm mainstream parts persisted way longer than it should have with some healthy competition.
In our datacenter the use of the halo / very large systems is fading away rather quickly. We are moving to cloud native tech where the mantra is lots of smaller commodity machines in clusters for scaling and availability. There are very few use cases anymore for very large single server systems. I think this is going to bode very well for AMD. I suspect when Zen 2 lands the big vendors like Amazon, Microsoft, Google will be all in on AMD especially if they beat Intel to 10nm.
I find your choice of the exculpatory paragraph "*Officially Intel doesn’t consider..." quite interesting. This is an editorial, like any article published on Anandtech, it's your opinion and analysis, so why you felt like you had to placate Intel, by saying that this "response" isn't official to them, tells me a lot of how vulnerable you feel against them.
What does any reader here care about what Intel considers official or not? We care about their hardware, not what they like their PR to look like. You would never say that AMD's Vega was not officially a "response" to the GTX1080, because it's obvious that it is, it's competition. The same situation applies to Intel VS AMD, so your explanatory paragraph comes out as plainly bizarre.
If anything, it points to Intel's menacing position in the market, if it makes you feel like you can't state your opinion on your website without clarifying for them and walking on egg shells. Further, it reinvigorates my preference to buy AMD (and I say that while still annoyed I had to buy a i5-8400 for my last build that I can't wait to replace, and feel stupid I traded my 480 for a 1060 - although I did make money thanks to the mining craze).
To me this read like "they are trying to hide behind such BS, better judge them by what they actually do (and don't do)". I don't think it has to be more obvious than this.
You mentioned the issue and skipped right over it. Traditionally Intel has had higher yields on large die than AMD (lower defect rate). This is not a design flaw on anyone's side, but prioritization. Intel sacrifices performance to get better yields (lower cost). So the cost savings AMD gets with smaller dies is more than Intel would get on comparable process technology (say 14 nm node). The big advantage for Intel is not in single socket systems, but multi-socket systems (high end). AMD has already used up it's socket count by connecting all the chips on a single substrate while Intel can still give you higher multiple socket count. With this Intel can scale to build larger systems. Either way, this is good competition - which is great for everyone!!!
Boritz, that post is confusing. What the heck does AMD has already used up it's socket count" mean? The Intel and AMD server chips you speak of all take up one socket. AMD connected a few chips together it's still a single socket, you can plug in multiple EPYC cpus into multi socket motherboards just like you can with Intel. Sure I can see intels large monolithic CPU's out performing AMD's approach on the high end but for none of the reasons you stated.
More reasons to drop the LLC die or at least increase it's core count significantly:
- at 6 - 10 cores the ring bus is obviously doing well, whereas Skylake-X is loosing performance and power efficiency. The mesh probably only starts to shine at over 20 cores or so. Otherwise they would have introduced it sooner.
- the HCC die at moderate core counts features a lower power density, so it can be cooled easier and hence be driven harder for workstation use.
Competition is not good. I still remember the days of AMD putting out good CPU designs but always come short due to Intel's superior node where AMD is behind by two generations. Lately, Intel is stubbornly waiting it out for 10nm, to save pennies, which makes it appear AMD is competing nicely. No wonder AMD or its CEO has been reserved with their comments for Ryzen, only positive statements that Ryzen will keep improving.
I'm curious as to the use cases for 16 cores on HEDT. If you're doing stuff like video encoding, wouldn't that be better served by GPUs? What desktop tasks are suitable for such high core counts?
I strongly disagree on Intel's need to switch to mesh AMD-like topology. What's more important, they NOW would probably do anything to avoid such a step. They do have access to something much more aggressive: Intel has invested billions in joint-venture with Micron, and they do have access to highly efficient stacking technology. Dropping massive, like 2-4-8k wide ring bus under whole chip would allow Intel to basically rescale current designs, without regards to surface area taken by it. Literally no one else is capable of this approach.
Also top tier for XCC Xeons can be further boosted by sticking few gigabytes of HBM beside it, as LLC.
I highly doubt that FPGA Xeons will hit mass market (or any market, even), first their TDP is obnoxiously high, like 270W+ per socket, and second, there is very high intro cost for usage - experience, tools, etc., so they will probably end up in direct customers' systems only. I guess FPGAs will instead trickle down to other products, like network infrastructure, specialized accelerators, and to some small degree, ML systems.
I think there are some very lucrative FPGA markets available for example in financial industry. Investment banks have the money and willingness to pay for both HW and programming talent if they smell money.
This kind of chips would most likely give super fat margins for Intel and I'm 110% sure that they will want to get them out sooner rather than later.
Intel will continue to offer LCC dies as not every server application scales well with additional core count. In particular, these are also being sold to the markets where higher clock speeds for lower latency transactions are more important than raw throughput per socket (think high frequency trading).
If Intel so desired, they could do a 5x4 mess arrangement to get a 14 core die: simply take the current 10 core schema and put an additional column of cores in the middle. (See the second picture in this article.) The MCC can take over the current XCC chip arrangement (5x6) in the future with the new XCC growing larger (7x6?).
There is another axis in which Intel can distinguish itself is by altering the amount of L3 cache between LCC, HCC and XCC. More cache means larger dies so this path would mean that the larger cache LCC chip would be similiar in size to the HCC chip if Intel were to really focus on this aspect. Say by putting 4 MB of L3 per tile vs the current 1.375 MB. Intel also has the option of introducing a medium core count chip (MCC?) into the mix if it makes sense.
I would also doubt that Intel is going to restrict the FPGA parts to two sockets due to the FPGA wanting a QPI/UPI link. One of the lesser known things is that these Xeon chips actually have controllers for 64 PCIe lanes on-die but the socket itself is only spec'd for 48 lanes externally. The spare 16 lanes go toward the on package Omnipath fabric of some models. If I were a betting man, I'd wager that Intel already has a spare QPI/UPI link on-die that isn't being used. These combo CPU+FPGA parts are something Intel hinted at before they purchased Altera so it has been in the works for sometime. Similarly, Intel at some point in the future is going to offer Nervana IP in the same package just like FPGA options.
Cascade Lake appears to be Sky Lake-SP with some errata fixed for Optane DIMM support. A move from 14+ nm to 14++ nm would also permit a slight clock speed boost but nothing earth shattering. This is what would be considered a new stepping back in the day.
Ice Lake is the design to look forward too. Intel at some point will start to leverage EMIB in the server space to expand their mesh topology. The difference in LCC, HCC and XCC products with EMIB would simply be the number of dies in the package dedicated just to CPU cores. This also permits Intel to expand their on-package options (Omnipath, FPGA, Nervana etc.) to flex EMIB packaging and use the same on-die mesh topology for cache coherency if it makes sense for a product. Lots of potential here but also several years away.
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DanNeely - Friday, June 1, 2018 - link
I agree that the 4x4 10+2+4 layout doesn't make sense if they're going to put 8 cores in next gen mainstream parts. I'm not convinced that Intel will only have a single HEDT/Xeon layout in the future. Instead, I'd expect both the LCC and HCC meshes to grow.A 5x4 layout for LCC could cover 10/12/14 core options at the lower end of the range.
HCC needs to grow too, a 5x6 layout - up from 4x6 - would add room for 2 more UPI lanes or 16 more PCIe lanes (depending on which Intel judges most needed), and 23 cores. If the odd core count itself is a problem, they could leave connectivity the same and offer 24 cores instead.
XCC would need to grow too, going from 6x6 to 6x8 would let them do 40 cores with IO unchanged, or 36 if they decide to add more ram/PCIe/UPI connections. More memory controllers might be a good option so they could slot in lots of Optane DIMMs while still having having plenty of DRAM available for application code and data that doesn't need to be persisted and which changes too frequently for Optane.
milkywayer - Friday, June 1, 2018 - link
I'm just thankful to AMD for forcing Intel to move from the 4 core BS that intel milked for almost a decade. Competition does wonderful things. Intel needed the kick in the butt.III-V - Friday, June 1, 2018 - link
I doubt AMD had anything to do with that. Where they absolutely had an effect is with pricing, but the existence of the 6 core part was a long time coming. And the "4 core" stuff wasn't BS -- Intel pursued graphics over core count, because it made more sense to them.It was likely that we'd have seen a 6 core part on 10nm, but due to delays, we saw that come on 14nm so that there was something new to keep OEMs happy.
Ket_MANIAC - Friday, June 1, 2018 - link
Oh no, it was my pet dog who ordered Intel to release all the products it did in 2017. AMD? What's that?FreckledTrout - Friday, June 1, 2018 - link
I hear this argument a lot, that Intel had to plan for it way before now so it could not have been AMD that caused it. If I had to guess Intel had 6-core designs for mainstream CPU's for at least two generations back. It's not like they got a new process node and found all this extra die space, no they are still running on 14nm and have a cheap 6-core CPU now. The fact that we see 6 cores on the mainstream CPU's is directly attributable to AMD aka competition.Alexvrb - Friday, June 1, 2018 - link
They had the configurations "waiting in the wings" but as FreckledTrout points out they had no intention of moving 6+ cores into the mainstream quite this soon. Now they're talking 8 cores on a mainstream platform.If you buy the official company line, it's all just a big coincidence. Indeed, they ignore products from other companies, plowing ahead with blinders on, totally isolated from the outside world.
FullmetalTitan - Saturday, June 2, 2018 - link
Based on the testimonials of former Intel employees the "blinders on" mentality does exist, but it's more of a problem at a higher level of design (see the 10nm debacle due to stubbornness) than consumer facing product segmentation.FullmetalTitan - Saturday, June 2, 2018 - link
"Intel pursued graphics over core count, because it made more sense to them."What? Intel integrated graphics are like 2 generations behind AMD APUs. If you mean they pursued discrete graphics instead, that commitment of resources happened after ~8 years of 4-core parts being the top of the mainstream offerings.
mode_13h - Sunday, June 3, 2018 - link
The point was that their graphics core count (and width) continued to increase as the manufacturing node decreased, even while their mainstream CPU core counts remained constant. So, it looks an awful lot like they spent much of the additional silicon budget afforded by die shrinks to grow their iGPU instead of adding more CPU cores.In 2010, their 32 nm Nehalem CPUs had Gen5 iGPUs with 12 EUs, each featuring 4-wide SIMD.
In 2012, their 22 nm Ivy Bridge CPUs had Gen7 iGPUs with 16 EUs, each featuring 8-wide SIMD.
In 2013, Haswell extended the mainstream up to 20 EUs.
In 2015, their 14 nm Broadwell CPUs had Gen8 iGPUs with 24 EUs.
Their mainstream CPUs are still at 14 nm and have iGPUs with 24 EUs.
Lolimaster - Friday, June 1, 2018 - link
Then you see how all of that seems idiotic vs AMD's approach.14-12nm
4core CCX, dual-CCX package for HEDT/EPYC (up to 32cores on a single socket)
7-7nm+
6/8core CCX, dual-CCX package for HEDT/EPYC (up to 64cores on a single socket)
HCC/LCC from intel just got OBSOLETE.
Arbie - Friday, June 1, 2018 - link
Isn't the phrase you wanted "cost-no-object"? Or is "money-no-cost" used in Britain?CajunArson - Friday, June 1, 2018 - link
"Intel also uses it in the upcoming Xeon+FPGA products to combine two chips in a single package using an intra-package connection, but it comes at the expense of limiting those Xeon Gold processors down to two sockets rather than four"Oh yeah, Intel is SO FAR BEHIND AMD because their on-package FPGA products are "cripplingly limited" to the exact same number of sockets that the highest-end AMD Zen2 based Epyc servers will support when they finally launch.
Oh, and those servers won't exactly have FPGAs or anything other than vanilla x86 cores on them either.
Your fanboy is showing Cuttress.
MrSpadge - Friday, June 1, 2018 - link
Please reread. Ian's statement is completely judgement free. And it's true: this design is "limiting" those Xeons to 2 rather than 4 socket configurations in the truest sense of the word: they simply can't be used for 4 sockets, so they're limited. That's the cost Intel currently has to pay for a multi chip package.Nowhere does Ian say this would be bad or inferior to AMD.
Alexvrb - Friday, June 1, 2018 - link
You have to lick Intel's boots or else you're an AMD fanboy. PROVE ME WRONG.close - Monday, June 4, 2018 - link
Ian is certainly no AMD fanboy. Don't forget that he "forgot" to cover the AMD Threadripper/EPYC launch last year for more than 2 weeks. Which is about 2 weeks longer than any other tech website worth mentioning.And when he finally covered it along with some other AMD review the Anandtech front page was immediately flooded with more than 2 dozen meaningless press releases of random Intel motherboard launches and other such irrelevant news that pushed the AMD articles to the bottom in less than half a day.
So definitely not an AMD fanboy. If anything he's being a little soft on Intel by not pointing out that one of Intel's the marching hymns was that they cater for the 4S market. So not being able to do that leaves them in the unenviable position of being substantially more expensive than AMD while catering to the exact same use cases.
Fortunately there's always some "incentive" program just round the corner to keep OEMs from jumping to quickly on the AMD bandwagon until Intel has something to respond with.
And I'm sure they will. Contrary to what many editors on plenty of tech sites insist on claiming, the "improvement pool" isn't tapped out. Fabrication might be more challenging but on the architecture side there plenty of room to improve. And Intel was always able to do that, just not willing due to lack of competition.
Vayra - Monday, June 4, 2018 - link
What arguments do you have to support the statement that the improvement pool is not tapped out then?The reason CPU performance and IPC bumps have stagnated is certainly not because the pool is full and AMD releasing Zen with a very similar IPC supports that idea. So you must have one hell of a source to say otherwise right now.
close - Tuesday, June 5, 2018 - link
That's not how the burden of proof works. So I expect all those Ziff Davis "journalists" who claimed "IPC can't improve" or "it's too expensive to put more than 4-6 cores on a die" to support the claims, not for everyone else to try to rebuff them.Time has proven again and again that the reason for stagnation is almost always lack of competition and insisting on profit margins.
Plus there are fewer physical limitations to how well you can design a CPU architecture than say building atom scale transistors.
FullmetalTitan - Saturday, June 2, 2018 - link
That statement had nothing at all to do with AMD though. It was just an observation that Intel sacrificed external communication lanes to set up the intra-package connect with the FPGA, when they had the option of a design tweak to maintain the same count of UPI connections externally.The closest that ever gets to EPYC is that the 2-core solution for EPYC servers follows a similar mentality of using their infinity fabric lanes for socket-to-socket communication such that single socket and dual socket EPYC platforms have the same number of external lanes exposed to the system.
FreckledTrout - Friday, June 1, 2018 - link
Thanks Ian, I really liked this article. Intel should have killed LCC on HEDT say 2-3 years ago but then they "should" have also had 6-8 core minatream parts. With no competition the milking of 4 core 14nm mainstream parts persisted way longer than it should have with some healthy competition.In our datacenter the use of the halo / very large systems is fading away rather quickly. We are moving to cloud native tech where the mantra is lots of smaller commodity machines in clusters for scaling and availability. There are very few use cases anymore for very large single server systems. I think this is going to bode very well for AMD. I suspect when Zen 2 lands the big vendors like Amazon, Microsoft, Google will be all in on AMD especially if they beat Intel to 10nm.
euskalzabe - Friday, June 1, 2018 - link
I find your choice of the exculpatory paragraph "*Officially Intel doesn’t consider..." quite interesting. This is an editorial, like any article published on Anandtech, it's your opinion and analysis, so why you felt like you had to placate Intel, by saying that this "response" isn't official to them, tells me a lot of how vulnerable you feel against them.What does any reader here care about what Intel considers official or not? We care about their hardware, not what they like their PR to look like. You would never say that AMD's Vega was not officially a "response" to the GTX1080, because it's obvious that it is, it's competition. The same situation applies to Intel VS AMD, so your explanatory paragraph comes out as plainly bizarre.
If anything, it points to Intel's menacing position in the market, if it makes you feel like you can't state your opinion on your website without clarifying for them and walking on egg shells. Further, it reinvigorates my preference to buy AMD (and I say that while still annoyed I had to buy a i5-8400 for my last build that I can't wait to replace, and feel stupid I traded my 480 for a 1060 - although I did make money thanks to the mining craze).
MrSpadge - Friday, June 1, 2018 - link
To me this read like "they are trying to hide behind such BS, better judge them by what they actually do (and don't do)". I don't think it has to be more obvious than this.bortiz - Friday, June 1, 2018 - link
You mentioned the issue and skipped right over it. Traditionally Intel has had higher yields on large die than AMD (lower defect rate). This is not a design flaw on anyone's side, but prioritization. Intel sacrifices performance to get better yields (lower cost). So the cost savings AMD gets with smaller dies is more than Intel would get on comparable process technology (say 14 nm node).The big advantage for Intel is not in single socket systems, but multi-socket systems (high end). AMD has already used up it's socket count by connecting all the chips on a single substrate while Intel can still give you higher multiple socket count. With this Intel can scale to build larger systems.
Either way, this is good competition - which is great for everyone!!!
FreckledTrout - Friday, June 1, 2018 - link
Boritz, that post is confusing. What the heck does AMD has already used up it's socket count" mean? The Intel and AMD server chips you speak of all take up one socket. AMD connected a few chips together it's still a single socket, you can plug in multiple EPYC cpus into multi socket motherboards just like you can with Intel. Sure I can see intels large monolithic CPU's out performing AMD's approach on the high end but for none of the reasons you stated.MrSpadge - Friday, June 1, 2018 - link
More reasons to drop the LLC die or at least increase it's core count significantly:- at 6 - 10 cores the ring bus is obviously doing well, whereas Skylake-X is loosing performance and power efficiency. The mesh probably only starts to shine at over 20 cores or so. Otherwise they would have introduced it sooner.
- the HCC die at moderate core counts features a lower power density, so it can be cooled easier and hence be driven harder for workstation use.
zodiacfml - Friday, June 1, 2018 - link
Competition is not good. I still remember the days of AMD putting out good CPU designs but always come short due to Intel's superior node where AMD is behind by two generations. Lately, Intel is stubbornly waiting it out for 10nm, to save pennies, which makes it appear AMD is competing nicely. No wonder AMD or its CEO has been reserved with their comments for Ryzen, only positive statements that Ryzen will keep improving.jjj - Saturday, June 2, 2018 - link
Lisa Su said recently that Zen 2 is first in server and unless she misspoke, that means Zen 2 desktop won't be same die as server anymore.serendip - Sunday, June 3, 2018 - link
I'm curious as to the use cases for 16 cores on HEDT. If you're doing stuff like video encoding, wouldn't that be better served by GPUs? What desktop tasks are suitable for such high core counts?Vatharian - Sunday, June 3, 2018 - link
I strongly disagree on Intel's need to switch to mesh AMD-like topology. What's more important, they NOW would probably do anything to avoid such a step. They do have access to something much more aggressive: Intel has invested billions in joint-venture with Micron, and they do have access to highly efficient stacking technology. Dropping massive, like 2-4-8k wide ring bus under whole chip would allow Intel to basically rescale current designs, without regards to surface area taken by it. Literally no one else is capable of this approach.Also top tier for XCC Xeons can be further boosted by sticking few gigabytes of HBM beside it, as LLC.
I highly doubt that FPGA Xeons will hit mass market (or any market, even), first their TDP is obnoxiously high, like 270W+ per socket, and second, there is very high intro cost for usage - experience, tools, etc., so they will probably end up in direct customers' systems only. I guess FPGAs will instead trickle down to other products, like network infrastructure, specialized accelerators, and to some small degree, ML systems.
zepi - Monday, June 4, 2018 - link
I think there are some very lucrative FPGA markets available for example in financial industry. Investment banks have the money and willingness to pay for both HW and programming talent if they smell money.This kind of chips would most likely give super fat margins for Intel and I'm 110% sure that they will want to get them out sooner rather than later.
Kevin G - Tuesday, June 5, 2018 - link
Intel will continue to offer LCC dies as not every server application scales well with additional core count. In particular, these are also being sold to the markets where higher clock speeds for lower latency transactions are more important than raw throughput per socket (think high frequency trading).If Intel so desired, they could do a 5x4 mess arrangement to get a 14 core die: simply take the current 10 core schema and put an additional column of cores in the middle. (See the second picture in this article.) The MCC can take over the current XCC chip arrangement (5x6) in the future with the new XCC growing larger (7x6?).
There is another axis in which Intel can distinguish itself is by altering the amount of L3 cache between LCC, HCC and XCC. More cache means larger dies so this path would mean that the larger cache LCC chip would be similiar in size to the HCC chip if Intel were to really focus on this aspect. Say by putting 4 MB of L3 per tile vs the current 1.375 MB. Intel also has the option of introducing a medium core count chip (MCC?) into the mix if it makes sense.
I would also doubt that Intel is going to restrict the FPGA parts to two sockets due to the FPGA wanting a QPI/UPI link. One of the lesser known things is that these Xeon chips actually have controllers for 64 PCIe lanes on-die but the socket itself is only spec'd for 48 lanes externally. The spare 16 lanes go toward the on package Omnipath fabric of some models. If I were a betting man, I'd wager that Intel already has a spare QPI/UPI link on-die that isn't being used. These combo CPU+FPGA parts are something Intel hinted at before they purchased Altera so it has been in the works for sometime. Similarly, Intel at some point in the future is going to offer Nervana IP in the same package just like FPGA options.
Cascade Lake appears to be Sky Lake-SP with some errata fixed for Optane DIMM support. A move from 14+ nm to 14++ nm would also permit a slight clock speed boost but nothing earth shattering. This is what would be considered a new stepping back in the day.
Ice Lake is the design to look forward too. Intel at some point will start to leverage EMIB in the server space to expand their mesh topology. The difference in LCC, HCC and XCC products with EMIB would simply be the number of dies in the package dedicated just to CPU cores. This also permits Intel to expand their on-package options (Omnipath, FPGA, Nervana etc.) to flex EMIB packaging and use the same on-die mesh topology for cache coherency if it makes sense for a product. Lots of potential here but also several years away.