I think in general the first designs to tape out on a new process are usually memories (e.g. Flash, DRAM) or an ARM low-power design. In this case, however, Xilinx has already announced plans to manufacture an FPGA/SoC on this node and AMD have announced a 7nm refresh of Vega and EPYC 2 will be on 7nm, so they might well be first.
Memory is not made on cutting edge processes. It's too cost-sensitive. Also, the processes seem to be a little bit different, and all major memory makers operate their own fabs. Both flash and DRAM are currently transitioning from the "1X" to the "1Y" process.
You are right about low-powered devices, though. They are usually the first on a new process. I don't know how much of that is because of the money able to be made in the high-end smartphone business and how much is because it's easier to get good yields on a low-powered device compared to a high-powered one.
As far as who is first for volume production on TSMC's 7nm, I think it is almost certainly Apple's A12.
AMD makes their CPUs at Global Foundries, I believe.
Mobile designs are also smaller and thus more tolerant of the yield issues a new process may have early on. Most of them are on the order of 100mm^2, whereas enthusiast GPUs can push 500mm^2.
Sorry, I should have been clearer: memories are usually produced first as tests because their repeating layouts are a good way to assess the process. Obviously anything the needs to be cost-effective will be done on older processes. Though the delay for adopting new nodes for memories seems to be reducing these days.
To quote Lisa Su from Ian's interview:
"So in 7nm, we will use both TSMC and GlobalFoundries. We are working closely with both foundry partners, and will have different product lines for each. I am very confident that the process technology will be stable and capable for what we’re trying to do."
So yes, the Vega cards are the more likely target for TSMC with EPYC 2 being the likely target for GloFo. I was responding to 7nm in general. I also think that Nvidia will likely wait on 7nm given how much they invested in 12nm to make the dies for the V100 and its derivatives.
Actually per extremetech's tour of goflo, they started that Vega 7nm will be a pipe cleaner for Goflo. Adoredtv said his source is telling him TSMC will get Zen 2 to make sure Epyc 2 is successful.
When you say "memmories" you mean SRAM. SRAM is used early on. DRAM? No. You can't just build DRAM on this process. DRAM is dramatically different than DRAM, and it has hit the scaling wall long ago. just search google. Here is an example article : http://semiengineering.com/1xnm-dram-challenges/ No process that makes cutting edge logic like this one from TSMC makes DRAM.
AMD "generally" makes at GF because of wafer agreement, but they are "allowed" to make them wherever they see fit because of court case they settled with Intel a few years ago where AMD license for x86 is applicable wherever is deemed "permissible"
generally AMD has used GF because of wafer agreement and Ngreedia uses TSMC because they do not want to go out of their way to be involved with anything AMD has a possible hand in ^.^
Everyone uses mature nods for huge prints. AMD has a history of using hi performance SOI node's and by the looks of things TSMC is far behind it's initial projections while Samsung is way ahead meaning they will be available about the same time. Even GF is still behind those two it also has an advantage of being able to provide it on SOI wafers (if costumer demands so). As 7nm FinFET will be a long term node & SOI makes GF one's much more advanced regarding performance while all three use different tools & layed out design aren't cross compatible I am certain AMD will stick with GF and so will IBM which actually mostly developed it. Samsung also may jump in on SOI bandwagon so things does not look good for TSMC.
No, GF hasn't had an in-house SOI process for a long time now. 14 FF+SOI was from IBM and will only be used on POWER9. It's 22FDX hasn't reached production stage yet and is not for general purpose chips.
Memory manufacturers aren't worried about cost sensitivity right now. With the artificial price inflation over the last 1-2 years, they have padding in their bottom line.
The SRAM cells are used for testing new nodes because of their structural simplicity which also lowers the error rate & they future improve the node on it before going in with more complex structures, multi structures... Second phase is smaller complex SoC's then mid size ones & last one is huge GPU's or FPGA's. Think we will see first consumer products by the beginning of the next year certainly from Samsung and Qualcomm and probably from Apple, rest of mobile will kick in in the second half of the year & first GPU's & FPGA's only in 2020.
You can't just use smaller transistors for general memory. DDR4 is 1v-1.4v. 7nm transistors operate around 0.7v. You'd need resistors to drop the voltage to make 7nm work with DDR4.
Or Apple A11X... That's a tricky one because there's no definite schedule for it.
One possibility is that it was scheduled for this sort of time (Q2), to be fabbed on 7FF, and TSMC slipped by a quarter. So we will see new iPads with A11X Q3 (maybe announced at WWDC?)
Another possibility (with all the Spectre/Meltdown stuff) is that Apple decided to treat it as a sacrificial chip --- make various tests to it to see what was safe and could easily be retrofitted to defeat Spectre/Meltdown --- so that those could be added to A12 in time. Meaning a "research" chip with a bunch of weird mods, that can't be sold to end-users. Expensive! But maybe they decided, all things considered and looking at the big picture [which includes getting to desktop CPUs by 2020] it was the best option?
Or perhaps no A11X? Maybe Apple figures iPads are good enough right now, and so all effort is going into A12X (to be their first chip on EUV 7FF+)? Maybe the iPad cadence going forward is to expect new SoCs every two years, not every year?
If Apple survives at all in the mean time which won't happen if China bans them which they should. When things start to go down hill the biggest cuts are in R&D department.
I read an analyst piece recently saying that Apple is using 7nm for both 2018 and 2019, not 7nm+ in 2019 as they are wanting to manufacture early in the year now.
Well you read now how 7nm TSMC is getting ready only now for a mass production meaning in the best bet they will need additional 3 more months to improve yields so that is in uper part of two digits for medium sized SoC's and Apple needs at least 3 more to manufacture them in significant enough amount which makes it on time for traditional holiday season launch, but that's still a best case scenario. Samsung will certainly be ready on spring season with both Exynos and Snapdragon products.
>Taiwan Semiconductor Manufacturing Company (TSMC) is likely to score record profits for 2018 as the company will be gradually ramping up volume production of 7nm process in the second half of the year to fulfill lucrative orders from Apple for fabricating A12 application processors for its 2018 new iPhone models and from Quacomm for processing its new-generation smartphone chips, according to industry sources.
You cant post links properly and you cant even read your own content on which you base your argument Intel's 14nm process is significantly denser than the competing processes from GF/SS and TSMC, >1.5x. It has taken roughly 3 years for SS and TSMC to introduce 10nm processes that are only slightly denser than Intel's 14nm process.
Nope, my link shows clearly that Intel's published 14nm density is 37.5 million transistors/mm^2, while TSMC 10nm does 60.3 mt/mm^2. That's more than 1.6 times as dense. Actual designs achieve close to that density on TSMC, but not on Intel 14nm, so the difference is even larger in real chips.
TSMC 10nm is 60% denser than Intel's 14nm, but Intel's 10nm is 66% denser than TSMC's 10nm.
As for actual production density, it's difficult to compare apples to apples because Intel makes different kinds of chips than TSMC. Chip designs can greatly affect density, plus some high performing chips leave unused space to help with cooling. I'm just saying there could be a bias in chip designs because TSMC fabs and Intel fabs that could easily account for resulting density differences.
Given the delays 10nm may go into volume production as a + or ++ variant, so the final density is unknown. How it compares vs TSMC 10nm no longer matters since it now competes with TSMC's 7nm which does ~116 mt/mm^2.
Yes there are many factors that affect density in real chips, not only the design itself but also all the process details. Historically Intel has used more restrictive design rules and faster cell libraries and that negatively affects density.
Maybe they need to stop with the XXnm and go with mt/mm^2. That would make it more useful, even if not perfect.
I've never been much of an Intel CPU fan boy, but their fab process has historically been the best by a long shot. As fun as it is to cheer for someone that is doing so well that no one can beat them at their game, it is nice to have competition.
Which is what he said, SS/TSMC 10nm is denser than Intel 14nm (and note that each + on that 14nm process trades a little density for higher clocks).
Right now, Intel is on 14nm, and TSMC is starting 7nm, hence his two generations ahead comment (although really it's ~1.1 generations) - although Intel should (but not necessarily will) get to 10nm late this year, catching up to the 7nm.
That'll be 2019 now rather than late this year. And we don't know what it will be like when it finally releases, my guess is they need to relax the "hyperscaling" considerably to get it to work.
The numbers can't be compared literally, they are just labels for the process. However the fabs do use labels that are in the right order, so 7nm is better/smaller/faster than 10nm which again is better than 14nm etc, just like you'd expect.
Well you can to some extent, for example TSMC 16nm is less dense than Intel 14nm, while TSMC and Samsung 10nm are significantly more dense. So calling those nodes 10nm is accurate.
TSMC 12nm is badly named as it is as dense as the other 14nm nodes.
Note however that Intel use 1D routing rules on their 14nm, but SS/GF/TSMC provide 2D routing rules, so whilst the basic transistor density is higher on Intel, the achieved overall density isn't as different. This isn't the only example. However seeing as Intel got there so many years ahead of the others I don't think it's worth an argument. The issue is Intel's 10nm process progress, or lack of, right now.
This isn't a 1:1 comparison; Intel still leads in some metrics and is also building its process with a different (potentially more complicated) design in mind.
I'm by no means a fab expert. Quite the opposite. But I've read that, I believe, the gates in Intel's process are much more advanced than the gates in everyone else's. The transistors may be similar, but the overall density does not correlate because everyone else is behind in other portions of the manufacturing.
This may/may not be correct as my understanding may have been faulty and other fabs may have passed Intel in gate manufacturing by now as well. I don't konw. But I have read that Intel still was more dense overall at 14 than other manufacturers' 10. FWIW
No your understanding is incorrect, and the opposite is true. TSMC 10nm is significantly more dense than Intel 14nm when you compare raw transistor density (see my link above).
In real designs it's even worse. TSMC 20nm chips were found to have a higher density than Intel 14nm chips. This is due to Intel prioritizing performance over density (for example Intel's 14+/++ processes are faster but less dense than the original 14nm process - on the other hand TSMC's 12nm process is both faster and more dense than the original 16nm process on which it is based).
Intel has upped their gate pitch for current 8xxx generation to keep the clock speeds up, but the transistor density is only one part of the "design" Sram (L1-L2-L3 whatever) is also a very distinct Intel has had a historical advantage over other fabs, so they may not have as much density per mm2 now, but, they may still have the raw advantage when all metrics of the die is taken into account.
lost a bit here gain a great deal more there type deal.
I think possibly Intels choice to stick with BULK vs SOI or whatever definitely has some advantages (which has been proven) but the smaller the nm design becomes there will be even more shift of what is possible vs what will no longer be to keep the shrinking happen (least this is what I have read)
AMD stuck with SOI whereas Intel used the "other" this allowed Intel to keep getting ahead year after year where AMD (and others) were stuck with a very low pace of shrinks happening, whereas now it seems that Intel has almost run into a wall because their choice to stick with what they were using becomes ever more complicated if they want to keep density, switching speed, latency etc etc as nice as they can (however you want to word that)
First to the gate does not mean you will always be the leader, last to the pass does not always mean you cannot win the race either.
Seems AMD decision to keep at it instead of folding their operations has borne much fruit even if it has taken longer to harvest it.
the future will be in many many many cores not simple fast ones, like our brain, it relies on insane multi threading much more so than raw mach 20 speeds (for lack of a better explanation) I believe the "old guard" that is Intel and Ngreedia are starting to notice this more and more and AMD is best to keep at it, "mining" and the way they have chosen to build their products is very much starting to come into its own, even if the average person is not using/able to tap into the potential horsepower that is there of course.
Most part I agree with you at least in the first part of the post. The FinFET structure time is at the end & new one's are in late commercial phase of development in order to replace it (gate all around). FinFET never whose suitable for analogue in the first place so we got stuck on that field for a long time (with what's considered as the planar bulk today & seen it's last half & full node's years ago), FD-SOI is addressing that now. Our brain is not a core nor many core's, it's adaptable neutral structure so future doesn't belong to many core nor high parallel systems it belongs to high adaptable one's or better say it belongs to FPGA's. FPGA can be programmed to become what ever suits the best task that needs to be executed. Potential is almost limitless or better say it's limited the same way as we are limited to use our brains but at least the FPGA program library is permanent and can be more perfected true time which is something we can't do regarding the way we use our brain (as we also forget true time and it degrees after certain time & it stays individual to the end)...
All the relevant metrics come together to determine where the customer goes and nobody votes for Intel with their wallet today. It's as simple as that and all else is BS.
The TSMC 12nm is renamed 16nm FinFET, it's not faster than second generation of their second generation 16nm that's made for performance. Utilised rooting libs on 12nm one are 17% denser it's also simplified as it has less layers & this makes it more cost efficient, which translates to 10% more power efficient while being 6~7% slower but you use that 10% power headroom to bump clock's up & anullate performance difference & still have 20~25% cheaper production (size difference combined with less layers). Re introduction of the SOI wafers on FinFET structure from GF will not be a game changer but it will certainly be a turning point defeating Intel in it's own game of high performance node's as 7nm from GF will be denser than Intels 10nm while SOI wafer will bring huge leaking important which will be much more ahead of Intels better fin structural form. I am talking of 20~30% performance difference or 30~50% density difference so 20~25% cheaper chip that performs 20% better & costs 20% less (more tied to CPUs) or same sized one that costs the same & performs 30~35% better (more tied for high parallel structures; GPU's, FPGA's, DSP's).
Intel has a higher aspect ratio FINFET, which allows for higher performance, at the cost of some efficiency (leakage/heat generation). But just looking at density, Samsung and TSMC passed up Intel's current offerings when they started shipping their respective 10nm products.
Intel 10nm has been delayed for YEARS, and will be on roughly the same density tier as TSMC/Samsung 7nm.
Well not yet because They allready have 10nm production. Just not commercial products yet. And Intel 10nm is same or Little bit smaller than thin 7nm... but it is possible that They will lose it if commercial products come out with this 7nm before Intel own 10nm is on the shops.
The best estimate Intel has about it's 10nm is that it is x% of the competitor's 7nm. They probably would have used 'better' or some other adjective if their 10nm was actually ahead.
It lost the process lead in the second half of last year & it lost the quantity lead at the end of last year. Samsung is now largest semiconductor manufacturer with whooping portfolio of products and IP's including third part licensable one's. Samsung retained flexibility & did some clever planing ahead of time so that it can get high profit margins & utilities it's capacities best way possible (last year it whose NAND production now it's SRAM [SDDR, HMB]). Those are two things Intel never had, only X86 monopoly & that space is shrinking for them.
They've existed since 2014 (which was mostly a scam, or at least heavily "tested" before shipping to customers). You can call them "SHA256 accelerators" if you want, but the meaning won't change.
They got the TSMC North America Symposiums on May 1st, there should be some decent amount of info there.
Anyway, so they start to ship 7nm around August and that means Apple and maybe Huawei in retail this year. Nvidia or AMD have little reason to rush 7nm in consumer. Hope ARM has a new core ready for 7nm, last 2 years they announced the new big core in May.
So, this allows Navi to be on a 7nm process in late 2019. If NVIDIA sticks to its 2 year release schedule, there will be a time when NVIDIA's soon-to-be-released architecture (probably on 12 nm FFN) goes up against AMD's Navi on 7 nm. That should be enough for AMD to put up strong competition. It may force NVIDIA into a die shrink refresh or to release gaming cards based on its next generation data center architecture which should be released in 2019 on 7 nm.
Funny how TSMC has failed in putting any comparison (or any mention of it at all) to their 12nm line. Seems to be on purpose to exaggerate the benifits of 7nm.
TSMC 12nmFF is a device scaled version of the 16nm process. It is completely compatible with existing 16nm designs, so pretty much every 16nm client of theirs will be moving their revision of 16nm designs to 12nm. It'll provide like extra 15% power saving and similar amount of performance increase. I guess there is no need to market it because the clients who would use this process was already set.
7nm/7nm++ is a complete new node (unlike 10nm was a mobile only half node), so TSMC focusing on signing up new designs for it by marketing it.
We’ve updated our terms. By continuing to use the site and/or by logging into your account, you agree to the Site’s updated Terms of Use and Privacy Policy.
Facebook
Twitter
RSS
63 Comments
Back to Article
NICOXIS - Tuesday, April 24, 2018 - link
I wonder what the first CPU or GPU on 7nm will be.SaberKOG91 - Tuesday, April 24, 2018 - link
I think in general the first designs to tape out on a new process are usually memories (e.g. Flash, DRAM) or an ARM low-power design. In this case, however, Xilinx has already announced plans to manufacture an FPGA/SoC on this node and AMD have announced a 7nm refresh of Vega and EPYC 2 will be on 7nm, so they might well be first.Yojimbo - Tuesday, April 24, 2018 - link
Memory is not made on cutting edge processes. It's too cost-sensitive. Also, the processes seem to be a little bit different, and all major memory makers operate their own fabs. Both flash and DRAM are currently transitioning from the "1X" to the "1Y" process.You are right about low-powered devices, though. They are usually the first on a new process. I don't know how much of that is because of the money able to be made in the high-end smartphone business and how much is because it's easier to get good yields on a low-powered device compared to a high-powered one.
As far as who is first for volume production on TSMC's 7nm, I think it is almost certainly Apple's A12.
AMD makes their CPUs at Global Foundries, I believe.
anexanhume - Tuesday, April 24, 2018 - link
Mobile designs are also smaller and thus more tolerant of the yield issues a new process may have early on. Most of them are on the order of 100mm^2, whereas enthusiast GPUs can push 500mm^2.SaberKOG91 - Tuesday, April 24, 2018 - link
Sorry, I should have been clearer: memories are usually produced first as tests because their repeating layouts are a good way to assess the process. Obviously anything the needs to be cost-effective will be done on older processes. Though the delay for adopting new nodes for memories seems to be reducing these days.To quote Lisa Su from Ian's interview:
"So in 7nm, we will use both TSMC and GlobalFoundries. We are working closely with both foundry partners, and will have different product lines for each. I am very confident that the process technology will be stable and capable for what we’re trying to do."
So yes, the Vega cards are the more likely target for TSMC with EPYC 2 being the likely target for GloFo. I was responding to 7nm in general. I also think that Nvidia will likely wait on 7nm given how much they invested in 12nm to make the dies for the V100 and its derivatives.
Singuy888 - Tuesday, April 24, 2018 - link
Actually per extremetech's tour of goflo, they started that Vega 7nm will be a pipe cleaner for Goflo. Adoredtv said his source is telling him TSMC will get Zen 2 to make sure Epyc 2 is successful.LurkingSince97 - Wednesday, April 25, 2018 - link
When you say "memmories" you mean SRAM. SRAM is used early on. DRAM? No. You can't just build DRAM on this process. DRAM is dramatically different than DRAM, and it has hit the scaling wall long ago. just search google. Here is an example article : http://semiengineering.com/1xnm-dram-challenges/ No process that makes cutting edge logic like this one from TSMC makes DRAM.LurkingSince97 - Wednesday, April 25, 2018 - link
>>> DRAM is dramatically different than SRAMDragonstongue - Tuesday, April 24, 2018 - link
AMD "generally" makes at GF because of wafer agreement, but they are "allowed" to make them wherever they see fit because of court case they settled with Intel a few years ago where AMD license for x86 is applicable wherever is deemed "permissible"generally AMD has used GF because of wafer agreement and Ngreedia uses TSMC because they do not want to go out of their way to be involved with anything AMD has a possible hand in ^.^
ZolaIII - Wednesday, April 25, 2018 - link
Everyone uses mature nods for huge prints. AMD has a history of using hi performance SOI node's and by the looks of things TSMC is far behind it's initial projections while Samsung is way ahead meaning they will be available about the same time. Even GF is still behind those two it also has an advantage of being able to provide it on SOI wafers (if costumer demands so). As 7nm FinFET will be a long term node & SOI makes GF one's much more advanced regarding performance while all three use different tools & layed out design aren't cross compatible I am certain AMD will stick with GF and so will IBM which actually mostly developed it. Samsung also may jump in on SOI bandwagon so things does not look good for TSMC.levizx - Sunday, May 13, 2018 - link
No, GF hasn't had an in-house SOI process for a long time now. 14 FF+SOI was from IBM and will only be used on POWER9. It's 22FDX hasn't reached production stage yet and is not for general purpose chips.James5mith - Wednesday, April 25, 2018 - link
Memory manufacturers aren't worried about cost sensitivity right now. With the artificial price inflation over the last 1-2 years, they have padding in their bottom line.xidex2 - Wednesday, April 25, 2018 - link
It has been rumored that AMD will actually use GF for its GPU stack and TSMC for Zen 2 and so on.ZolaIII - Wednesday, April 25, 2018 - link
The SRAM cells are used for testing new nodes because of their structural simplicity which also lowers the error rate & they future improve the node on it before going in with more complex structures, multi structures... Second phase is smaller complex SoC's then mid size ones & last one is huge GPU's or FPGA's. Think we will see first consumer products by the beginning of the next year certainly from Samsung and Qualcomm and probably from Apple, rest of mobile will kick in in the second half of the year & first GPU's & FPGA's only in 2020.bcronce - Wednesday, April 25, 2018 - link
You can't just use smaller transistors for general memory. DDR4 is 1v-1.4v. 7nm transistors operate around 0.7v. You'd need resistors to drop the voltage to make 7nm work with DDR4.eSyr - Tuesday, April 24, 2018 - link
Apple A12?name99 - Tuesday, April 24, 2018 - link
Or Apple A11X... That's a tricky one because there's no definite schedule for it.One possibility is that it was scheduled for this sort of time (Q2), to be fabbed on 7FF, and TSMC slipped by a quarter. So we will see new iPads with A11X Q3 (maybe announced at WWDC?)
Another possibility (with all the Spectre/Meltdown stuff) is that Apple decided to treat it as a sacrificial chip --- make various tests to it to see what was safe and could easily be retrofitted to defeat Spectre/Meltdown --- so that those could be added to A12 in time. Meaning a "research" chip with a bunch of weird mods, that can't be sold to end-users. Expensive!
But maybe they decided, all things considered and looking at the big picture [which includes getting to desktop CPUs by 2020] it was the best option?
Or perhaps no A11X? Maybe Apple figures iPads are good enough right now, and so all effort is going into A12X (to be their first chip on EUV 7FF+)? Maybe the iPad cadence going forward is to expect new SoCs every two years, not every year?
ZolaIII - Wednesday, April 25, 2018 - link
If Apple survives at all in the mean time which won't happen if China bans them which they should. When things start to go down hill the biggest cuts are in R&D department.Speedfriend - Wednesday, April 25, 2018 - link
I read an analyst piece recently saying that Apple is using 7nm for both 2018 and 2019, not 7nm+ in 2019 as they are wanting to manufacture early in the year now.ZolaIII - Wednesday, April 25, 2018 - link
Well you read now how 7nm TSMC is getting ready only now for a mass production meaning in the best bet they will need additional 3 more months to improve yields so that is in uper part of two digits for medium sized SoC's and Apple needs at least 3 more to manufacture them in significant enough amount which makes it on time for traditional holiday season launch, but that's still a best case scenario. Samsung will certainly be ready on spring season with both Exynos and Snapdragon products.BillBear - Wednesday, April 25, 2018 - link
>Taiwan Semiconductor Manufacturing Company (TSMC) is likely to score record profits for 2018 as the company will be gradually ramping up volume production of 7nm process in the second half of the year to fulfill lucrative orders from Apple for fabricating A12 application processors for its 2018 new iPhone models and from Quacomm for processing its new-generation smartphone chips, according to industry sources.https://www.digitimes.com/news/a20180423PD209.html
basket687 - Tuesday, April 24, 2018 - link
So Intel has now officially lost its manufacturing lead...Wilco1 - Tuesday, April 24, 2018 - link
Both TSMC and Samsung 10nm are already much denser than Intel 14nm even when using Intel's density metric (https://www.semiwiki.com/forum/content/6713-14nm-1... So Intel is now 2 process generations behind...DeepLake - Wednesday, April 25, 2018 - link
You cant post links properly and you cant even read your own content on which you base your argumentIntel's 14nm process is significantly denser than the competing processes from GF/SS and TSMC, >1.5x. It has taken roughly 3 years for SS and TSMC to introduce 10nm processes that are only slightly denser than Intel's 14nm process.
Wilco1 - Wednesday, April 25, 2018 - link
Nope, my link shows clearly that Intel's published 14nm density is 37.5 million transistors/mm^2, while TSMC 10nm does 60.3 mt/mm^2. That's more than 1.6 times as dense. Actual designs achieve close to that density on TSMC, but not on Intel 14nm, so the difference is even larger in real chips.bcronce - Wednesday, April 25, 2018 - link
Intel's 10nm is 100 mt/mm^2.TSMC 10nm is 60% denser than Intel's 14nm, but Intel's 10nm is 66% denser than TSMC's 10nm.
As for actual production density, it's difficult to compare apples to apples because Intel makes different kinds of chips than TSMC. Chip designs can greatly affect density, plus some high performing chips leave unused space to help with cooling. I'm just saying there could be a bias in chip designs because TSMC fabs and Intel fabs that could easily account for resulting density differences.
Wilco1 - Wednesday, April 25, 2018 - link
Given the delays 10nm may go into volume production as a + or ++ variant, so the final density is unknown. How it compares vs TSMC 10nm no longer matters since it now competes with TSMC's 7nm which does ~116 mt/mm^2.Yes there are many factors that affect density in real chips, not only the design itself but also all the process details. Historically Intel has used more restrictive design rules and faster cell libraries and that negatively affects density.
bcronce - Wednesday, April 25, 2018 - link
Maybe they need to stop with the XXnm and go with mt/mm^2. That would make it more useful, even if not perfect.I've never been much of an Intel CPU fan boy, but their fab process has historically been the best by a long shot. As fun as it is to cheer for someone that is doing so well that no one can beat them at their game, it is nice to have competition.
psychobriggsy - Wednesday, April 25, 2018 - link
Which is what he said, SS/TSMC 10nm is denser than Intel 14nm (and note that each + on that 14nm process trades a little density for higher clocks).Right now, Intel is on 14nm, and TSMC is starting 7nm, hence his two generations ahead comment (although really it's ~1.1 generations) - although Intel should (but not necessarily will) get to 10nm late this year, catching up to the 7nm.
Wilco1 - Saturday, April 28, 2018 - link
That'll be 2019 now rather than late this year. And we don't know what it will be like when it finally releases, my guess is they need to relax the "hyperscaling" considerably to get it to work.ianmills - Tuesday, April 24, 2018 - link
I don't think the 7nm vs 10nm can be directly comparedWilco1 - Tuesday, April 24, 2018 - link
The numbers can't be compared literally, they are just labels for the process. However the fabs do use labels that are in the right order, so 7nm is better/smaller/faster than 10nm which again is better than 14nm etc, just like you'd expect.qap - Wednesday, April 25, 2018 - link
but that only applies within single fab. You can not directly compare processess by using their names between manufacturers.Wilco1 - Wednesday, April 25, 2018 - link
Well you can to some extent, for example TSMC 16nm is less dense than Intel 14nm, while TSMC and Samsung 10nm are significantly more dense. So calling those nodes 10nm is accurate.TSMC 12nm is badly named as it is as dense as the other 14nm nodes.
psychobriggsy - Wednesday, April 25, 2018 - link
Note however that Intel use 1D routing rules on their 14nm, but SS/GF/TSMC provide 2D routing rules, so whilst the basic transistor density is higher on Intel, the achieved overall density isn't as different. This isn't the only example. However seeing as Intel got there so many years ahead of the others I don't think it's worth an argument. The issue is Intel's 10nm process progress, or lack of, right now.Sahrin - Tuesday, April 24, 2018 - link
This isn't a 1:1 comparison; Intel still leads in some metrics and is also building its process with a different (potentially more complicated) design in mind.teldar - Tuesday, April 24, 2018 - link
I'm by no means a fab expert. Quite the opposite. But I've read that, I believe, the gates in Intel's process are much more advanced than the gates in everyone else's. The transistors may be similar, but the overall density does not correlate because everyone else is behind in other portions of the manufacturing.This may/may not be correct as my understanding may have been faulty and other fabs may have passed Intel in gate manufacturing by now as well. I don't konw. But I have read that Intel still was more dense overall at 14 than other manufacturers' 10.
FWIW
Wilco1 - Tuesday, April 24, 2018 - link
No your understanding is incorrect, and the opposite is true. TSMC 10nm is significantly more dense than Intel 14nm when you compare raw transistor density (see my link above).In real designs it's even worse. TSMC 20nm chips were found to have a higher density than Intel 14nm chips. This is due to Intel prioritizing performance over density (for example Intel's 14+/++ processes are faster but less dense than the original 14nm process - on the other hand TSMC's 12nm process is both faster and more dense than the original 16nm process on which it is based).
Dragonstongue - Tuesday, April 24, 2018 - link
Intel has upped their gate pitch for current 8xxx generation to keep the clock speeds up, but the transistor density is only one part of the "design" Sram (L1-L2-L3 whatever) is also a very distinct Intel has had a historical advantage over other fabs, so they may not have as much density per mm2 now, but, they may still have the raw advantage when all metrics of the die is taken into account.lost a bit here gain a great deal more there type deal.
I think possibly Intels choice to stick with BULK vs SOI or whatever definitely has some advantages (which has been proven) but the smaller the nm design becomes there will be even more shift of what is possible vs what will no longer be to keep the shrinking happen (least this is what I have read)
AMD stuck with SOI whereas Intel used the "other" this allowed Intel to keep getting ahead year after year where AMD (and others) were stuck with a very low pace of shrinks happening, whereas now it seems that Intel has almost run into a wall because their choice to stick with what they were using becomes ever more complicated if they want to keep density, switching speed, latency etc etc as nice as they can (however you want to word that)
First to the gate does not mean you will always be the leader, last to the pass does not always mean you cannot win the race either.
Seems AMD decision to keep at it instead of folding their operations has borne much fruit even if it has taken longer to harvest it.
the future will be in many many many cores not simple fast ones, like our brain, it relies on insane multi threading much more so than raw mach 20 speeds (for lack of a better explanation) I believe the "old guard" that is Intel and Ngreedia are starting to notice this more and more and AMD is best to keep at it, "mining" and the way they have chosen to build their products is very much starting to come into its own, even if the average person is not using/able to tap into the potential horsepower that is there of course.
ZolaIII - Wednesday, April 25, 2018 - link
Most part I agree with you at least in the first part of the post. The FinFET structure time is at the end & new one's are in late commercial phase of development in order to replace it (gate all around).FinFET never whose suitable for analogue in the first place so we got stuck on that field for a long time (with what's considered as the planar bulk today & seen it's last half & full node's years ago), FD-SOI is addressing that now.
Our brain is not a core nor many core's, it's adaptable neutral structure so future doesn't belong to many core nor high parallel systems it belongs to high adaptable one's or better say it belongs to FPGA's. FPGA can be programmed to become what ever suits the best task that needs to be executed. Potential is almost limitless or better say it's limited the same way as we are limited to use our brains but at least the FPGA program library is permanent and can be more perfected true time which is something we can't do regarding the way we use our brain (as we also forget true time and it degrees after certain time & it stays individual to the end)...
jjj - Wednesday, April 25, 2018 - link
All the relevant metrics come together to determine where the customer goes and nobody votes for Intel with their wallet today. It's as simple as that and all else is BS.ZolaIII - Wednesday, April 25, 2018 - link
The TSMC 12nm is renamed 16nm FinFET, it's not faster than second generation of their second generation 16nm that's made for performance. Utilised rooting libs on 12nm one are 17% denser it's also simplified as it has less layers & this makes it more cost efficient, which translates to 10% more power efficient while being 6~7% slower but you use that 10% power headroom to bump clock's up & anullate performance difference & still have 20~25% cheaper production (size difference combined with less layers). Re introduction of the SOI wafers on FinFET structure from GF will not be a game changer but it will certainly be a turning point defeating Intel in it's own game of high performance node's as 7nm from GF will be denser than Intels 10nm while SOI wafer will bring huge leaking important which will be much more ahead of Intels better fin structural form. I am talking of 20~30% performance difference or 30~50% density difference so 20~25% cheaper chip that performs 20% better & costs 20% less (more tied to CPUs) or same sized one that costs the same & performs 30~35% better (more tied for high parallel structures; GPU's, FPGA's, DSP's).FullmetalTitan - Wednesday, April 25, 2018 - link
Intel has a higher aspect ratio FINFET, which allows for higher performance, at the cost of some efficiency (leakage/heat generation). But just looking at density, Samsung and TSMC passed up Intel's current offerings when they started shipping their respective 10nm products.Intel 10nm has been delayed for YEARS, and will be on roughly the same density tier as TSMC/Samsung 7nm.
haukionkannel - Wednesday, April 25, 2018 - link
Well not yet because They allready have 10nm production. Just not commercial products yet. And Intel 10nm is same or Little bit smaller than thin 7nm... but it is possible that They will lose it if commercial products come out with this 7nm before Intel own 10nm is on the shops.sgeocla - Wednesday, April 25, 2018 - link
The best estimate Intel has about it's 10nm is that it is x% of the competitor's 7nm. They probably would have used 'better' or some other adjective if their 10nm was actually ahead.Wilco1 - Wednesday, April 25, 2018 - link
Intel 10nm isn't in high volume production. If it was we would know about it given all the delays.Note TSMC 7nm is more dense than Intel 10nm just like TSMC 10nm is more dense than Intel 14nm.
edzieba - Wednesday, April 25, 2018 - link
We know Intel has already shipped 10nm parts (https://www.anandtech.com/show/12271/intel-mention... , https://www.anandtech.com/show/12436/intel-10nm-du... The GPU-less dies seems a good fit for the upcoming Crimson Canyon NUCs (and likely the same package uses in Mac Minis/Macbooks/etc) with a lower power CPU + GPU combo than Kaby Lake G.Wilco1 - Wednesday, April 25, 2018 - link
It's standard practice to ship test chips to customers - not the same as volume production.ZolaIII - Wednesday, April 25, 2018 - link
It lost the process lead in the second half of last year & it lost the quantity lead at the end of last year. Samsung is now largest semiconductor manufacturer with whooping portfolio of products and IP's including third part licensable one's. Samsung retained flexibility & did some clever planing ahead of time so that it can get high profit margins & utilities it's capacities best way possible (last year it whose NAND production now it's SRAM [SDDR, HMB]). Those are two things Intel never had, only X86 monopoly & that space is shrinking for them.Scabies - Tuesday, April 24, 2018 - link
>cryptocurrency mining acceleratorsThis is my first time seeing this term.
I dont like it.
wumpus - Friday, April 27, 2018 - link
They've existed since 2014 (which was mostly a scam, or at least heavily "tested" before shipping to customers). You can call them "SHA256 accelerators" if you want, but the meaning won't change.Lodix - Tuesday, April 24, 2018 - link
You can check TSMC's offical web to get their Performance/Power/Area improvements in their latest nodes.http://www.tsmc.com/english/dedicatedFoundry/techn...
They didn't achieve their targets for 10nm and the improvements are now cited as 15% better performance, 35% lower power and ~X2 density over 16FF+.
For 7FF over 10FF they clain a 20% better performance, 40% lower power and x1'6 logic density.
jjj - Tuesday, April 24, 2018 - link
They got the TSMC North America Symposiums on May 1st, there should be some decent amount of info there.Anyway, so they start to ship 7nm around August and that means Apple and maybe Huawei in retail this year. Nvidia or AMD have little reason to rush 7nm in consumer.
Hope ARM has a new core ready for 7nm, last 2 years they announced the new big core in May.
jjj - Wednesday, April 25, 2018 - link
Edit: AMD confirmed that the machine learning aimed Vega 7nm is made at TSMC and they got it running in the lab with samples later this year,Yojimbo - Tuesday, April 24, 2018 - link
So, this allows Navi to be on a 7nm process in late 2019. If NVIDIA sticks to its 2 year release schedule, there will be a time when NVIDIA's soon-to-be-released architecture (probably on 12 nm FFN) goes up against AMD's Navi on 7 nm. That should be enough for AMD to put up strong competition. It may force NVIDIA into a die shrink refresh or to release gaming cards based on its next generation data center architecture which should be released in 2019 on 7 nm.Santoval - Tuesday, April 24, 2018 - link
Navi will more likely be released in Q2 2019 rather than late 2019. Around May 2019 we should get it.Yojimbo - Tuesday, April 24, 2018 - link
You're basing that prediction on what?brunis.dk - Wednesday, April 25, 2018 - link
Can't wait for Zen2 on 7nmHighTech4US - Wednesday, April 25, 2018 - link
Funny how TSMC has failed in putting any comparison (or any mention of it at all) to their 12nm line. Seems to be on purpose to exaggerate the benifits of 7nm.https://www.fudzilla.com/news/43640-tsmc-lands-chi...
FullmetalTitan - Wednesday, April 25, 2018 - link
It is almost assuredly because the 12nm process is a revamped 14nm process with probably a different back end.Samsung did a similar thing with 12/11nm, by merging their newer 10nm back end design with their stable 14nm front end process.
astroboy888 - Friday, July 20, 2018 - link
TSMC 12nmFF is a device scaled version of the 16nm process. It is completely compatible with existing 16nm designs, so pretty much every 16nm client of theirs will be moving their revision of 16nm designs to 12nm. It'll provide like extra 15% power saving and similar amount of performance increase. I guess there is no need to market it because the clients who would use this process was already set.7nm/7nm++ is a complete new node (unlike 10nm was a mobile only half node), so TSMC focusing on signing up new designs for it by marketing it.
Ananke - Friday, April 27, 2018 - link
Finally, NVidia has 7 nm GPU designs since 2014, waiting in the pipeline. I bet these are the ones that TSMC refers to "entered mass production"....Kedas - Monday, April 30, 2018 - link
Calculations must be difficult at 7nm ;)Power 7FF vs 16FF+ = 60% better or (Power 16FF x0.4)
Power 10FF vs 16FF+ = 40% better or (Power 16FF x0.6)
Power 7FF vs 10FF = <40% ?????? how can you not know if you know both above.
Let me calculate that for you:
Power 7FF / Power 10FF = 0.4/0.6= 2/3 or 33% better !! (sure <40% is also right but <100% also)