That is a top notch article if I ever saw one. Love the talk and I had to look up a bunch of words/acronyms. I have a basic understanding of process nodes, but the more I read the more I realize I don't know jack!
Wish you would have asked about monolithic 3D. Also wish you would have asked about consolidation, UMC is at the right time to be acquired, if someone sees sufficient value in that. He evaded a bit the budget advanced packaging question and maybe you should have pushed and also inquire about MCM as folks like AMD and Marvell seem to like MCM quite a bit. Would have liked to hear something about MRAM or alternatives on future nodes (beyond 7nm) and how does that compare vs SRAM in his view, area and not only. Maybe there should be a conversation around ARM server chips. Assuming rather small cores leading to a very small proportion of the chip used by those cores, how does one take best advantage of the small cores. A single monolithic chip that's mostly SRAM and I/O , seems less than ideal. Can NVM and advanced packaging enable a much cheaper solution with few trade-offs? In auto, what's the focus, autonomy or electrification. Folks are too focused on autonomy and not enough on electrification as the ramp for electrification is underestimated - it will be easier to grab revenue there.
Anyway, feels they might skip the foundry 5nm node and go 3-4nm with nanosheet in 2021-2023. Curious how Vega clocks on 7nm, especially with APUs - assuming AMD uses Vega on 7nm in APU, don't think that's confirmed yet but it makes sense.
I highly doubt they can go directly to ~3.5nm -for a near quadrupling of density- already in 2021 (maybe in 2023+), unless perhaps ASML achieves a huge breakthrough in EUV (like reaching 350 - 400 wafers per hour, all the pellicle issues are resolved etc). To my knowledge, if III-V semiconductors like InGaAs ever replace silicon the approaching density dead-end issue should stop, since the dies can be less dense but be clocked faster - provided the thermal budgets allow this.
So the fact that they appear to be little more than lab curiosities (in the MOSFET space, they are used for things like HEMTs) suggests that their very high clock abilities come with very high power & thermal draws, and/or that mass manufacturing and handling tertiary semiconductors is considered too complex, and/or that the industry still does not want to let go of silicon. That's a shame, because if that happened the multi-core wars would cease and the clock wars would be revived!
"GP: We are working very hard with our partners in Albany, with IBM, and with Samsung, on technology for what is next. We pushed with them on a research paper last year on 5nm - 5nm with nanosheet/gate-all-around technology, and the first demonstration of that on a chip working or a full block of circuits working. So we have worked there on that, and we have worked on vertical transistors. I believe FinFETs are starting to run out of steam, and I think it looks to me that 5nm could end up being a little bit like 10nm and 20nm - maybe a lot like 20nm. It is kind of the end of the road for device structures, but for some foundries you have to get something out for the Christmas season... Q21: So at that point you have to move to gate-all-around? GP: I think to get a real boost off of 7nm, it is going to take a jump to a new device architecture. We would like to do what we did with 7nm, which is come out with a full-on node rather than a half-node. Because the design investment for these things, concerning our customers, it is a big design investment to move to a new technology now, and we want to make sure for the customer base we're interested in, that we're giving them a substantial improvement in density and in performance. So are we going to call the next one 5nm? I'm not going to worry – I’m just going to call it the next node. I can tell you that we will have a significant performance and density improvement."
The naming scheme is relative and they clearly don't think that foundry 5nm offers enough. Samsung already announced its nanosheet node as 4nm with risk production targeted in 2020 I believe. Best case scenario for GloFo, a 7nm generation every year for 3 years and a jump to nanosheet in 2022 (high vol prod) and then, they likely go below 4nm with the naming scheme. If they are a bit slower than that, less than ideal but not a disaster given their lack of scale - buying UMC would help with that so we'll see.
If the naming scheme is relative then their "5nm" should provide double the density of their "7nm" node. Also, don't forget this part: "I think to get a real boost off of 7nm, it is going to take a jump to a new device architecture".
anyone have a link to a generalist description of alternative structures (not just different material) for transistors made from semi-conductors??? and how close are we to non-deterministic behaviour using existing materials and structures? is 5/7 nm the end?
Folks are looking at gare-all-around with horizontal nonowire/nanosheet, vertical nanowires, stacked, CFET, even things like TFET and more. But all of this is a huge effort for less than great gains, to have something out for Xmas. So gonna share this link https://community.cadence.com/cadence_blogs_8/b/br...
I appreciate the gesture but I understood the term from context:) I'm only arguing about gf skipping 5nm. The density gains are good and, as was quoted, progress has been made with towards nanosheet/gate all around with 5nm. It seems to be understood that 5nm won't give you gains commensurate with bring up costs without those new designs.
If their node is better than foundry 5nn and comes 1-2 years later, they would not call it 5nm. He clearly hints at that by saying "So are we going to call the next one 5nm? I'm not going to worry – I’m just going to call it the next node. I can tell you that we will have a significant performance and density improvement." Likely they'll try to avoid SADP with EUV or costs go to hell.
I share your skepticism. I always understood below 7nm was going to take xray lithography and all that technology is still stalled out in R&D and if they want to use it by 2020 they'd already need the lithography machines in production testing right now. Even bumping up the frequency to near xray I think is going to be problematic and the quantum effects become tremendous at less than 7nm as you're down to traces that are only a 35 atoms thick at 7nm and 3.5nm would be 18 silicon atoms (Si atom is approx. 0.2nm). At 7nm you get electron tunneling effects and all sorts of unpredictable quantum effects, and each shrink after that is going to get worse. Unless they can find a way to put graphene in or some other technology I'm skeptical that process tech below 7nm will even work. Until they can get real process tech working and verify they can control the quantum effects at this level I'm going to remain skeptical they'll ever be able to mass produce functional products.
I think we should move away from nm classification of the process - it is so subjected to interpretation. What is really important here is how many transistors can be place in same amount of area and also not sure how calculated - speed of processes on chips and the power draw.
So big question is how many times more dense is this processed than the previous process. For example Intel's 14 nm process is 2.5x more dense than the previous 22nm.
Any set of numbers can be presented or abused in a way that makes it lose valuable meaning to the public unless the requirements are fairly stringent and the group(s) imposing those requirements have the power to penalize mischaracterizations. I don't know of any group that can exercise that sort of authority over companies that develop and produce integrated circuits.
To me it reminds me of Frequency wars back in old Pentium 4 days and the recent CPU core battles
As a customer, there is a lot more to purchase decision than then stated Frequency, number of cores on process the chips.. And to make it more complicated - it depends on what the computer is used for. For a tablet, it more important to have it lower power but for gaming machine or workstation - it usually number of cores, speed of cores and graphics.
Of course over time especially for someone that been using computers for 3 decades or more, the need for graphics goes down and become less important. But I see advance in manufacturing process as a way to give customers more ability in less area and less power. Mean you can have more cores either CPU and/or GPU in less area and using less power.
It also depends on type of customer, I personally is a person that is very technical and even at point I found an erratum in IBM's 486SLC chip during my early days. But my parents on the other hand, don't even care about the internal, just that email comes up and get do banking on the internet - for those type of customers Integrated graphics is fine.
Also what people think as high cost today, is consider lower cost yesterday. I remember purchasing top of line Dell Inspiration 7000 with Mobile Pentium 3 300Mhz for almost $4000 and today a top of line dell XPS is 1/2 that price and extremely increase performance. In fact a Intel Atom chips has more power than the 7000.
I agree. At this point a standard industry benchmark would be better. Like maybe pick some stock chips that everyone in the industry has access to (eg one of arm cpu's) and give metrics, size, yield, clock speed, power etc for them on the new process. Doubt we'd see it but that feels like it would be a much more meaningful comparison.
Benchmarks especially across different architectures is something totally different. It very difficult because different processors are meant for different types of applications.
But this process is referring to how the CPU/GPU or any other device is made - how dense process contains and how fast that it performance. Memory is good example, you would think with more dense material you get more memory
Keep in mind this process is no longer just talking 2 dimensions - I believe we have the 3rd dimension now.
Maybe a nice suggestion, but then you have different players fighting over which transistor mix to use for that benchmark. High frequency CPUs like Intels use on average bigger transistors, so their density seems worse than for e.g. mobile SoCs. But (part of?) that is only a design choice, not a process difference.
Different products (mobile/high performance) use different size transistors and other features (on the same process), so that is not a universal metric.
Just view the nm value as the name or label of the process, not a measurement or competition result, and there is no problem. I doubt there is a metric that could be used to accurately gauge the "advancedness" of a process node across manufacturers, so why even try?
Density is NOT the only important parameter of a PP briefly recognized by a nm number. It is only one of the parameters.
What is important in reality is not how many transistor you can put on a given area (beside, which kind of transistor? They are not all equal) but number one the cost for them and the power needed to make run at a certain frequency. These two parameters can condense al lot of other values: for example, if I want to create an ASIC made of a tot number of transistor I do not really care how you call your PPs, I want to know how much it costs on what you call 28nm or 14nm or 12nm. And the performance (seen as max frequency and power my ASIC can run and must use to get a certain amount of work done) achievable. So, for a mobile chip that is already small (so it is not near maximum tool handling capacities, like for example were GM200, Fiji an is now GV100) and MUST use as less current as possible a process called "12nm" may be perfectly scaled with respect to a process called "16/20/28nm" in term of power consumption and possibly cost (if cost per mm^2 decrease independently of the density, for example for less masks needed). For those chip that are big enough to require a bigger density to grow in power of course density is important, but again it is not the only important parameter. Think for example a so called 7nm PP where real transistor dimension are not much different than those of TMSC 12nm but allow for a great bump in frequencies and power saving, nvidia could still create a chip faster than GV100 (being however different than this) nonetheless maybe at lower cost due to the use of less marks and patterning works.
Density is only a single parameter of a much complex system that is needed to create new and more powerful products each generation (that is, as it is said here, even though 20nm could allow for a smaller die size it was completely useless to improve products and make it an economical advantage for those designing new chips).
I not saying Density is the only parameter, I just say that nm is not the only parameter. I am concern that industry is misleading us with think that because one process has a smaller number (nm) than that means it is better - there are other factors.
Unfortunately as I said the parameters are many and you cannot list them all to describe a PP. As world goes on for and by simplification, an index is needed and that is historically the nm values that have lost their original meaning lots of time ago to just indicate a sort of "features" of the PP. And yes, smaller number means that is better than the previous one. In what and and how much is suggested by the used nm number.
It's like trying to give a description on a car by a single value: how would you compare a Mercedes with a BMW? And a Porche against a Hyundai? What parameters would you use for that? Just the engine power?
"And yes, smaller number means that is better than the previous one. In what and and how much is suggested by the used nm number."
That may be true but per manufacture and also by personal opinion. That last part is very subjective and for some people can be use as trying persuade others. On the latter, people have stated that Intel's 10nm is slower then Intel's 14nm - of course that statement is not valid because Intel has not release such a chip on that process - I would think like software, chips in development are naturally slower than final release product.
Sincerely I can't understand why "people" care about what other "people" say about a particular PP. Unless you work for a foundry or as the one appointed to create the layout of ASICs on those PP, none has real knowledge on what are they exactly, so anything said is a "personal opinion". If you ask for an absolute index that measure performance between different PP of different foundries, well, it is quite an utopia. PP is not only by nanometers and watts, but also lots of other particulars that in the end make values more difficult to interpret. Some PP are good for LP, other for HP, some exceptionally good for low freq, other get better (with respect to the other concurrent ones) at higher freq so you cannot make a single index that describe them as a whole, personal opinion aside.
As I said, try to give a number that identify a Mercedes SLC and one that identify a BMW 730 so that you can compare them. If yo manage to do that, you can come and try to persuade others that there' s away that a simple index can also describe a PP as a whole so that you can compare Intel 10nm to GF 12nm.
So they said that they are not pushing full EUV at beginning as some other competitor will do (TSMC?) So we'll see if they can execute better than the competitors (which could be limited in performance and yields if EUV will not be really ready) with this cautious roadmap or if they will be left in dust by the competition that with full EUV working at the beginning will produce better and cheaper products than they can.
He’s not the guy that determines the future of the industry. He’s the guy that, presently, determines the future of GF. Until he leaves.
I also think it’s a shame that companies like IBM, world leaders in technology over the decades, are giving their most advanced technologies away to companies who mostly belong to not that stable foreign countries who are not exactly our most reliable allies.
If that’s national chauvinism, so be it.
And bringing in Samsung’s 14nm because theirs failed wasn’t brilliant, it was desperatation. They would practically be out of business if they didn’t.
With all due respect to Dr. Patton, I don't believe you can skip pellicles at any time. Otherwise everyone would be skipping pellicles for contacts and vias today. EUV would resolve the smaller particles.
Q28: Would you say that your ASIC partners are a mix of old and new customers? New, as in the last couple of years?
GP: Mixed. Some have been our traditional customers for our ASICS business for many years, and there are some new players that can't be named.
IC: Let's not beat about the bush, I'm trying to get to cryptocurrency related customers!
GP: I think actually some of the existing players who have graphics chips out there, are being pretty public about their success in the ASIC space. You don't need 7nm for that.
Q29: We have cryptocurrency mining businesses building chips on other foundries on leading edge nodes, potentially taking up substantial amounts of capacity, perhaps to the detriment of the consumer business. Regardless, it's still a customer for you if they come to you, but does that factor into your plans at all or you just sell capacity to anybody who needs it?
GP: Obviously we put a high focus on our key partners, but we're not turning anybody away at this point. For some of that market however, they will be looking at our 22FDX technology, not necessarily 14nm or 7nm. Our 22FDX is manufacturing in Dresden, and Cheng-du, our China factory. 12FDX, the next node, is a high volume, high capacity play for us.
This is hilarious. I am not even sure Gary even understood the question and knows what cryptocurrency is about. This is an answer that I can expect of a high-school kid who does not know the answer but does not admit he does not know and starts mumbling and jumbling words.
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WinterCharm - Thursday, February 22, 2018 - link
What an excellent article.I'm really excited to see what 7nm FinFET will enable in terms of CPU, Mobile SoC, and GPU in the coming years :D
Holliday75 - Friday, February 23, 2018 - link
That is a top notch article if I ever saw one. Love the talk and I had to look up a bunch of words/acronyms. I have a basic understanding of process nodes, but the more I read the more I realize I don't know jack!jjj - Thursday, February 22, 2018 - link
Wish you would have asked about monolithic 3D.Also wish you would have asked about consolidation, UMC is at the right time to be acquired, if someone sees sufficient value in that.
He evaded a bit the budget advanced packaging question and maybe you should have pushed and also inquire about MCM as folks like AMD and Marvell seem to like MCM quite a bit.
Would have liked to hear something about MRAM or alternatives on future nodes (beyond 7nm) and how does that compare vs SRAM in his view, area and not only.
Maybe there should be a conversation around ARM server chips. Assuming rather small cores leading to a very small proportion of the chip used by those cores, how does one take best advantage of the small cores. A single monolithic chip that's mostly SRAM and I/O , seems less than ideal. Can NVM and advanced packaging enable a much cheaper solution with few trade-offs?
In auto, what's the focus, autonomy or electrification. Folks are too focused on autonomy and not enough on electrification as the ramp for electrification is underestimated - it will be easier to grab revenue there.
Anyway, feels they might skip the foundry 5nm node and go 3-4nm with nanosheet in 2021-2023.
Curious how Vega clocks on 7nm, especially with APUs - assuming AMD uses Vega on 7nm in APU, don't think that's confirmed yet but it makes sense.
Cellar Door - Thursday, February 22, 2018 - link
Thanks Ian - excellent article!jjj - Dude, you are worse then my mother in law. Complains about every thing - ok we get it, you are the smartest!
Just enjoy this great article.
MrSpadge - Thursday, February 22, 2018 - link
It's definitely hard to please jjj, but in the current post I see no complaining, just some further thoughts.Santoval - Thursday, February 22, 2018 - link
I highly doubt they can go directly to ~3.5nm -for a near quadrupling of density- already in 2021 (maybe in 2023+), unless perhaps ASML achieves a huge breakthrough in EUV (like reaching 350 - 400 wafers per hour, all the pellicle issues are resolved etc). To my knowledge, if III-V semiconductors like InGaAs ever replace silicon the approaching density dead-end issue should stop, since the dies can be less dense but be clocked faster - provided the thermal budgets allow this.So the fact that they appear to be little more than lab curiosities (in the MOSFET space, they are used for things like HEMTs) suggests that their very high clock abilities come with very high power & thermal draws, and/or that mass manufacturing and handling tertiary semiconductors is considered too complex, and/or that the industry still does not want to let go of silicon. That's a shame, because if that happened the multi-core wars would cease and the clock wars would be revived!
jjj - Thursday, February 22, 2018 - link
"GP: We are working very hard with our partners in Albany, with IBM, and with Samsung, on technology for what is next. We pushed with them on a research paper last year on 5nm - 5nm with nanosheet/gate-all-around technology, and the first demonstration of that on a chip working or a full block of circuits working. So we have worked there on that, and we have worked on vertical transistors. I believe FinFETs are starting to run out of steam, and I think it looks to me that 5nm could end up being a little bit like 10nm and 20nm - maybe a lot like 20nm. It is kind of the end of the road for device structures, but for some foundries you have to get something out for the Christmas season...Q21: So at that point you have to move to gate-all-around?
GP: I think to get a real boost off of 7nm, it is going to take a jump to a new device architecture.
We would like to do what we did with 7nm, which is come out with a full-on node rather than a half-node. Because the design investment for these things, concerning our customers, it is a big design investment to move to a new technology now, and we want to make sure for the customer base we're interested in, that we're giving them a substantial improvement in density and in performance.
So are we going to call the next one 5nm? I'm not going to worry – I’m just going to call it the next node. I can tell you that we will have a significant performance and density improvement."
The naming scheme is relative and they clearly don't think that foundry 5nm offers enough. Samsung already announced its nanosheet node as 4nm with risk production targeted in 2020 I believe. Best case scenario for GloFo, a 7nm generation every year for 3 years and a jump to nanosheet in 2022 (high vol prod) and then, they likely go below 4nm with the naming scheme. If they are a bit slower than that, less than ideal but not a disaster given their lack of scale - buying UMC would help with that so we'll see.
tuxRoller - Friday, February 23, 2018 - link
If the naming scheme is relative then their "5nm" should provide double the density of their "7nm" node.Also, don't forget this part: "I think to get a real boost off of 7nm, it is going to take a jump to a new device architecture".
MrSpadge - Friday, February 23, 2018 - link
Here "device" means "transistor", which is what jjj is talking about with nanosheet etc.FunBunny2 - Friday, February 23, 2018 - link
"Here "device" means "transistor" "anyone have a link to a generalist description of alternative structures (not just different material) for transistors made from semi-conductors??? and how close are we to non-deterministic behaviour using existing materials and structures? is 5/7 nm the end?
jjj - Friday, February 23, 2018 - link
Folks are looking at gare-all-around with horizontal nonowire/nanosheet, vertical nanowires, stacked, CFET, even things like TFET and more.But all of this is a huge effort for less than great gains, to have something out for Xmas. So gonna share this link https://community.cadence.com/cadence_blogs_8/b/br...
jjj - Friday, February 23, 2018 - link
Adding this https://community.cadence.com/cadence_blogs_8/b/br...weightloss - Sunday, March 11, 2018 - link
really good pint. thanks. "@tuxRoller" <a href="http://weightlossclues.com/">weight loss tips</a>tuxRoller - Sunday, February 25, 2018 - link
I appreciate the gesture but I understood the term from context:)I'm only arguing about gf skipping 5nm.
The density gains are good and, as was quoted, progress has been made with towards nanosheet/gate all around with 5nm.
It seems to be understood that 5nm won't give you gains commensurate with bring up costs without those new designs.
jjj - Sunday, February 25, 2018 - link
If their node is better than foundry 5nn and comes 1-2 years later, they would not call it 5nm. He clearly hints at that by saying "So are we going to call the next one 5nm? I'm not going to worry – I’m just going to call it the next node. I can tell you that we will have a significant performance and density improvement."Likely they'll try to avoid SADP with EUV or costs go to hell.
weightloss - Sunday, March 11, 2018 - link
thanks for sharing your opinion good comment. http://weightlossclues.com/rahvin - Friday, February 23, 2018 - link
I share your skepticism. I always understood below 7nm was going to take xray lithography and all that technology is still stalled out in R&D and if they want to use it by 2020 they'd already need the lithography machines in production testing right now. Even bumping up the frequency to near xray I think is going to be problematic and the quantum effects become tremendous at less than 7nm as you're down to traces that are only a 35 atoms thick at 7nm and 3.5nm would be 18 silicon atoms (Si atom is approx. 0.2nm). At 7nm you get electron tunneling effects and all sorts of unpredictable quantum effects, and each shrink after that is going to get worse. Unless they can find a way to put graphene in or some other technology I'm skeptical that process tech below 7nm will even work. Until they can get real process tech working and verify they can control the quantum effects at this level I'm going to remain skeptical they'll ever be able to mass produce functional products.FunBunny2 - Friday, February 23, 2018 - link
D'oh!!! your comment was on the next page, so I didn't see it as I typed. didn't know I was stepping on you. :)HStewart - Thursday, February 22, 2018 - link
I think we should move away from nm classification of the process - it is so subjected to interpretation. What is really important here is how many transistors can be place in same amount of area and also not sure how calculated - speed of processes on chips and the power draw.So big question is how many times more dense is this processed than the previous process. For example Intel's 14 nm process is 2.5x more dense than the previous 22nm.
PeachNCream - Thursday, February 22, 2018 - link
Any set of numbers can be presented or abused in a way that makes it lose valuable meaning to the public unless the requirements are fairly stringent and the group(s) imposing those requirements have the power to penalize mischaracterizations. I don't know of any group that can exercise that sort of authority over companies that develop and produce integrated circuits.HStewart - Thursday, February 22, 2018 - link
To me it reminds me of Frequency wars back in old Pentium 4 days and the recent CPU core battlesAs a customer, there is a lot more to purchase decision than then stated Frequency, number of cores on process the chips.. And to make it more complicated - it depends on what the computer is used for. For a tablet, it more important to have it lower power but for gaming machine or workstation - it usually number of cores, speed of cores and graphics.
Of course over time especially for someone that been using computers for 3 decades or more, the need for graphics goes down and become less important. But I see advance in manufacturing process as a way to give customers more ability in less area and less power. Mean you can have more cores either CPU and/or GPU in less area and using less power.
HStewart - Thursday, February 22, 2018 - link
It also depends on type of customer, I personally is a person that is very technical and even at point I found an erratum in IBM's 486SLC chip during my early days. But my parents on the other hand, don't even care about the internal, just that email comes up and get do banking on the internet - for those type of customers Integrated graphics is fine.Also what people think as high cost today, is consider lower cost yesterday. I remember purchasing top of line Dell Inspiration 7000 with Mobile Pentium 3 300Mhz for almost $4000 and today a top of line dell XPS is 1/2 that price and extremely increase performance. In fact a Intel Atom chips has more power than the 7000.
andrewaggb - Thursday, February 22, 2018 - link
I agree. At this point a standard industry benchmark would be better. Like maybe pick some stock chips that everyone in the industry has access to (eg one of arm cpu's) and give metrics, size, yield, clock speed, power etc for them on the new process. Doubt we'd see it but that feels like it would be a much more meaningful comparison.HStewart - Thursday, February 22, 2018 - link
Benchmarks especially across different architectures is something totally different. It very difficult because different processors are meant for different types of applications.But this process is referring to how the CPU/GPU or any other device is made - how dense process contains and how fast that it performance. Memory is good example, you would think with more dense material you get more memory
Keep in mind this process is no longer just talking 2 dimensions - I believe we have the 3rd dimension now.
MrSpadge - Thursday, February 22, 2018 - link
Maybe a nice suggestion, but then you have different players fighting over which transistor mix to use for that benchmark. High frequency CPUs like Intels use on average bigger transistors, so their density seems worse than for e.g. mobile SoCs. But (part of?) that is only a design choice, not a process difference.Hul8 - Thursday, February 22, 2018 - link
Different products (mobile/high performance) use different size transistors and other features (on the same process), so that is not a universal metric.Just view the nm value as the name or label of the process, not a measurement or competition result, and there is no problem. I doubt there is a metric that could be used to accurately gauge the "advancedness" of a process node across manufacturers, so why even try?
CiccioB - Friday, February 23, 2018 - link
Density is NOT the only important parameter of a PP briefly recognized by a nm number.It is only one of the parameters.
What is important in reality is not how many transistor you can put on a given area (beside, which kind of transistor? They are not all equal) but number one the cost for them and the power needed to make run at a certain frequency.
These two parameters can condense al lot of other values: for example, if I want to create an ASIC made of a tot number of transistor I do not really care how you call your PPs, I want to know how much it costs on what you call 28nm or 14nm or 12nm. And the performance (seen as max frequency and power my ASIC can run and must use to get a certain amount of work done) achievable.
So, for a mobile chip that is already small (so it is not near maximum tool handling capacities, like for example were GM200, Fiji an is now GV100) and MUST use as less current as possible a process called "12nm" may be perfectly scaled with respect to a process called "16/20/28nm" in term of power consumption and possibly cost (if cost per mm^2 decrease independently of the density, for example for less masks needed).
For those chip that are big enough to require a bigger density to grow in power of course density is important, but again it is not the only important parameter. Think for example a so called 7nm PP where real transistor dimension are not much different than those of TMSC 12nm but allow for a great bump in frequencies and power saving, nvidia could still create a chip faster than GV100 (being however different than this) nonetheless maybe at lower cost due to the use of less marks and patterning works.
Density is only a single parameter of a much complex system that is needed to create new and more powerful products each generation (that is, as it is said here, even though 20nm could allow for a smaller die size it was completely useless to improve products and make it an economical advantage for those designing new chips).
HStewart - Friday, February 23, 2018 - link
I not saying Density is the only parameter, I just say that nm is not the only parameter. I am concern that industry is misleading us with think that because one process has a smaller number (nm) than that means it is better - there are other factors.CiccioB - Friday, February 23, 2018 - link
Unfortunately as I said the parameters are many and you cannot list them all to describe a PP. As world goes on for and by simplification, an index is needed and that is historically the nm values that have lost their original meaning lots of time ago to just indicate a sort of "features" of the PP.And yes, smaller number means that is better than the previous one. In what and and how much is suggested by the used nm number.
It's like trying to give a description on a car by a single value: how would you compare a Mercedes with a BMW? And a Porche against a Hyundai? What parameters would you use for that? Just the engine power?
HStewart - Friday, February 23, 2018 - link
"And yes, smaller number means that is better than the previous one. In what and and how much is suggested by the used nm number."That may be true but per manufacture and also by personal opinion. That last part is very subjective and for some people can be use as trying persuade others. On the latter, people have stated that Intel's 10nm is slower then Intel's 14nm - of course that statement is not valid because Intel has not release such a chip on that process - I would think like software, chips in development are naturally slower than final release product.
CiccioB - Friday, February 23, 2018 - link
Sincerely I can't understand why "people" care about what other "people" say about a particular PP. Unless you work for a foundry or as the one appointed to create the layout of ASICs on those PP, none has real knowledge on what are they exactly, so anything said is a "personal opinion".If you ask for an absolute index that measure performance between different PP of different foundries, well, it is quite an utopia. PP is not only by nanometers and watts, but also lots of other particulars that in the end make values more difficult to interpret.
Some PP are good for LP, other for HP, some exceptionally good for low freq, other get better (with respect to the other concurrent ones) at higher freq so you cannot make a single index that describe them as a whole, personal opinion aside.
As I said, try to give a number that identify a Mercedes SLC and one that identify a BMW 730 so that you can compare them. If yo manage to do that, you can come and try to persuade others that there' s away that a simple index can also describe a PP as a whole so that you can compare Intel 10nm to GF 12nm.
MananDedhia - Thursday, February 22, 2018 - link
Excellent article. Kudos.Tigacom Group - Thursday, February 22, 2018 - link
An Excellent expression on the Technology prospectus and co - relationship. Thank you.Pork@III - Friday, February 23, 2018 - link
There is a high probability that the first true artificial intelligence will be self-realized on a 7 / 5nm chip.CiccioB - Friday, February 23, 2018 - link
So they said that they are not pushing full EUV at beginning as some other competitor will do (TSMC?)So we'll see if they can execute better than the competitors (which could be limited in performance and yields if EUV will not be really ready) with this cautious roadmap or if they will be left in dust by the competition that with full EUV working at the beginning will produce better and cheaper products than they can.
melgross - Friday, February 23, 2018 - link
He’s not the guy that determines the future of the industry. He’s the guy that, presently, determines the future of GF. Until he leaves.I also think it’s a shame that companies like IBM, world leaders in technology over the decades, are giving their most advanced technologies away to companies who mostly belong to not that stable foreign countries who are not exactly our most reliable allies.
If that’s national chauvinism, so be it.
And bringing in Samsung’s 14nm because theirs failed wasn’t brilliant, it was desperatation. They would practically be out of business if they didn’t.
edzieba - Monday, February 26, 2018 - link
Wow, some professional-grade question-dodging when asked about EMIB!Anymoore - Wednesday, March 14, 2018 - link
With all due respect to Dr. Patton, I don't believe you can skip pellicles at any time. Otherwise everyone would be skipping pellicles for contacts and vias today. EUV would resolve the smaller particles.garypattongf - Wednesday, August 22, 2018 - link
Q28: Would you say that your ASIC partners are a mix of old and new customers? New, as in the last couple of years?GP: Mixed. Some have been our traditional customers for our ASICS business for many years, and there are some new players that can't be named.
IC: Let's not beat about the bush, I'm trying to get to cryptocurrency related customers!
GP: I think actually some of the existing players who have graphics chips out there, are being pretty public about their success in the ASIC space. You don't need 7nm for that.
Q29: We have cryptocurrency mining businesses building chips on other foundries on leading edge nodes, potentially taking up substantial amounts of capacity, perhaps to the detriment of the consumer business. Regardless, it's still a customer for you if they come to you, but does that factor into your plans at all or you just sell capacity to anybody who needs it?
GP: Obviously we put a high focus on our key partners, but we're not turning anybody away at this point. For some of that market however, they will be looking at our 22FDX technology, not necessarily 14nm or 7nm. Our 22FDX is manufacturing in Dresden, and Cheng-du, our China factory. 12FDX, the next node, is a high volume, high capacity play for us.
This is hilarious. I am not even sure Gary even understood the question and knows what cryptocurrency is about. This is an answer that I can expect of a high-school kid who does not know the answer but does not admit he does not know and starts mumbling and jumbling words.