D'oh - Intel 10nm IS probably equivalent to TSMC 5nm, was my typo-ridden point. Everyone other than Intel uses a difference metric, to make themselves sound better than they are basically.
No Intel's 10nm doesn't even use EUV so it's in not nearly as advanced as TSMC 5nm, and can't even beat the density of TSMC 7nm. The world has changed, Intel lost its leadership in chip technology last year.
Intel was way too ambitious with their 10nm node, jumping from 37.5 million transistors per mm^2 at 14nm to ~101 million transistors per mm^2 at 10nm, a 2.7x higher transistor density. It appears that this ambition is one of the reasons of the delay of the 10nm launch, perhaps the primary reason.
TSMC and Samsung at 10nm are at 45 - 53 million transistors per mm^2 (let's assume an average of 50 million), which is barely denser than Intel's 14nm. Do you seriously think that either they or GloFo, EUV or not, will manage to go beyond 100 million transistors at 7nm? Intel was more ambitious with their 10nm node due to the very long delay (they needed to "catch up"), but that reason does not apply to the others.
EUV is not a magic bullet. It merely helps companies reduce the number of steps but its issues have not all yet been resolved. At first it will only be used for some critical layers, with the rest being done by plain old 193nm ArF lithography. There is a reason Intel wants to focus on comparing transistor densities of the FEOL stack while the others insist on quoting meaningless xxnm marketing numbers. Now, if Intel does not release 10nm CPUs in 2018 either (or even if they release the first in Q4 2018) it will surely fall back. But as of yet it hasn't.
Right, Intel was “too ambitious”. This sort of BS excuse may work in American politics, but the rest of the world is not quite as stupid as the average American voter.
This is how the American century ends, as the Americans retreat into an ever more detached fantasyland, spreading from culture to politics, now to business.
This whole nm size stuff reminds me of days of Frequency wars back in Pentium 4 days - but sort of in reverse. We are actually not sure exactly what Intel's 10nm is like - but it like be more dense that other processes significantly. This is why it taking longer get out. I believes Intel's process is 3D process.
In any case, what matters is how many transistors / components can be in square area and not nm metric.
Most exiting thing about Intel's processes is that it can combine multiple processes on the same die. This means important components like CPU / GPU / Memory can be on denser material why the IO and less important components can be done on less denser. I don't believe Intel is using this for combo Intel CPU / AMD GPU component - that things reminds me of last Celeron / Pentium components - which have more in common with Atom that higher level processors. I was frustrated with my Lenovo 100s 14in - I could not update memory.
I hope none of my comments have mistakes - because I wish we could edit comments here.
Well pretty much all of our post is FUD or fake news as it is called nowadays. Combining multiple processes on the same die? 3D process? What pills did you take?
I checked out the article you linked and apparently I was wrong above. It says Samsung's 7nm is going to have 127.3 MTr/mm^2 and TSMC's 7nm will have 116.7 MTr/mm^2. I had no idea they were so ambitious. Since Intel will retain 10nm for at least three CPU generations I will concede that they have fallen behind Samsung and TSMC (and GloFo?) even if the others' 7nm node is released two, three or even four quarters after Intel's 10nm.
" We are actually not sure exactly what Intel's 10nm is like - but it like be more dense that other processes significantly. This is why it taking longer get out. I believes Intel's process is 3D process."
They've published details at conferences. FinFETs (in that sense as 3D as before) with air gaps to reduce capacitance and increase performance, together with a material change for the Vias, if I remember correctly. That's quite ambitous and will give them an advantage over processes without those changes.
Density figures have also been published: more dense than TSMCs & Samsungs 10 nm, but less dense than competing 7 nm processes.
Everyone else covered the wealth of density info released over the last 2 years.
"Most exiting thing about Intel's processes is that it can combine multiple processes on the same die. This means important components like CPU / GPU / Memory can be on denser material why the IO and less important components can be done on less denser."
This is just local pattern density? You can make transistors larger or less dense than the half-pitch node naming implies.
" I don't believe Intel is using this for combo Intel CPU / AMD GPU component..."
No idea what this rambling means, but Intel is just packaging a coffee lake CPU with a custom Vega die and HBM2 for easier integration into ultrabooks and such, there is nothing special about that venture.
TSMS/GF/Samsung/IBM etc all build their wafer much differently than Intel does, so, a problem that affects one does not automatically mean it effects the others.
I have a feeling Intel was "milking it" because for years and years no other fab was close to competing with them being "the most advanced" so they did as little as they possibly could to ensure the lowest cost highest ROI on every chip/product they sold, but since 28nm, now 14-12-7nm soon enough the competition caught up quite quickly.
Intel may be the "leading producer" but, they generally only produce their own chips, so someone like TSMC whos only job is to build for others gets $ from many places and does many different designs as well, so at least in my opinion, this gives them maybe that much more ability to "tweak" their designs going forward, so in theory would mean more flexibility to work through or around kinks that maybe Intel cannot.
Generally because of the way Intel builds their "bulk" transistors it allows them to have far tighter tolerance on gates and the like, so more oft than not means less voltage required for higher speed or at very least more density per die, this is something that gave them a major advantage vs others (generally using SOI or FD-SOI) however, the density, transistor count, leakage and so forth of Intel vs competition (TSMC-Samsung/GF/IBM) has been very much eroding over the last decade.
So just to iterate IMO just because Intel got lazy or screwed up however you want to word it, they still are making $$$$$$$$$ and really only produce chips for their own purpose, so they likely do not have nearly the same motivation at keeping at the absolute bleeding edge when it comes to nm scaling like they once did, am sure they have many other fish in the pot to worry about.
TSMC as an example, only job is to produce the chips they are paid to do, so they have every motivation to keep pushing in lowever nm higher density, if they are not "the best" others will be, means less $$$$ Intel still makes loads of $$$ from being able to produce high density chips AND making the chips as well.
"Intel may be the "leading producer" but, they generally only produce their own chips, so someone like TSMC whos only job is to build for others gets $ from many places and does many different designs as well"
One thing to remember that could be key to future Intel processes is that Intel purchase Altlera which is/was a leader in maker of "Field Programmable Gate Array" which is used to create custom design logic for many different purpose. This was done a while back and I believe a lot of Intel's future designed will benefit from this purchase. This purchase likely means that Intel process will be open to others.
Intel lost their status as "leading producer" last year. They have been floundering for a while. Ask anyone in the mfg environment and they will tell you that Intel talent has been fleeing for greener pastures for a while now
Uhhh, wot? One of these companies has made a habit of lying ever since the 14nm Broadwell delays. And one has delivered on time year after year since at least 28nm. Just because INTC doesn’t know what the hell they are doing doesn’t mean the rest of the world is as incompetent...
Kind of my thought, especially since they haven't secured EUV for use in their 7nm node. Unless ASML is magically doubling scanner production next year, they are currently on a 1 tool per month pace, most of which through 2019 have been pre-purchased by various foundries.
Not your point to worry about right now. They will have some idea and probably data, but won't publish them yet (7 nm production has not even started!).
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soliloquist - Wednesday, January 31, 2018 - link
Given all the trouble that Intel has had with bringing 10nm to market, I will believe those time tables when I see it.FunBunny2 - Wednesday, January 31, 2018 - link
you can't fool Mother Nature, or Heisenberg.gfkBill - Wednesday, January 31, 2018 - link
Intel 10nm != TSMC 5nmgfkBill - Wednesday, January 31, 2018 - link
D'oh - Intel 10nm IS probably equivalent to TSMC 5nm, was my typo-ridden point. Everyone other than Intel uses a difference metric, to make themselves sound better than they are basically.(Dammit, why we can't Edit comments, Anandtech?)
Wilco1 - Wednesday, January 31, 2018 - link
No Intel's 10nm doesn't even use EUV so it's in not nearly as advanced as TSMC 5nm, and can't even beat the density of TSMC 7nm. The world has changed, Intel lost its leadership in chip technology last year.Santoval - Thursday, February 1, 2018 - link
Intel was way too ambitious with their 10nm node, jumping from 37.5 million transistors per mm^2 at 14nm to ~101 million transistors per mm^2 at 10nm, a 2.7x higher transistor density. It appears that this ambition is one of the reasons of the delay of the 10nm launch, perhaps the primary reason.TSMC and Samsung at 10nm are at 45 - 53 million transistors per mm^2 (let's assume an average of 50 million), which is barely denser than Intel's 14nm. Do you seriously think that either they or GloFo, EUV or not, will manage to go beyond 100 million transistors at 7nm? Intel was more ambitious with their 10nm node due to the very long delay (they needed to "catch up"), but that reason does not apply to the others.
EUV is not a magic bullet. It merely helps companies reduce the number of steps but its issues have not all yet been resolved. At first it will only be used for some critical layers, with the rest being done by plain old 193nm ArF lithography. There is a reason Intel wants to focus on comparing transistor densities of the FEOL stack while the others insist on quoting meaningless xxnm marketing numbers.
Now, if Intel does not release 10nm CPUs in 2018 either (or even if they release the first in Q4 2018) it will surely fall back. But as of yet it hasn't.
name99 - Thursday, February 1, 2018 - link
Right, Intel was “too ambitious”.This sort of BS excuse may work in American politics, but the rest of the world is not quite as stupid as the average American voter.
This is how the American century ends, as the Americans retreat into an ever more detached fantasyland, spreading from culture to politics, now to business.
wut - Friday, February 23, 2018 - link
Do you absorb hard numbers or just words? Maybe "270%" would sink in better than "2.7x"?OrbitingCow - Monday, August 13, 2018 - link
LOL what a hot take.mr_fokyou - Friday, January 18, 2019 - link
Oopsm it seems that comment has not aged wellHStewart - Wednesday, January 31, 2018 - link
This whole nm size stuff reminds me of days of Frequency wars back in Pentium 4 days - but sort of in reverse. We are actually not sure exactly what Intel's 10nm is like - but it like be more dense that other processes significantly. This is why it taking longer get out. I believes Intel's process is 3D process.In any case, what matters is how many transistors / components can be in square area and not nm metric.
Most exiting thing about Intel's processes is that it can combine multiple processes on the same die. This means important components like CPU / GPU / Memory can be on denser material why the IO and less important components can be done on less denser. I don't believe Intel is using this for combo Intel CPU / AMD GPU component - that things reminds me of last Celeron / Pentium components - which have more in common with Atom that higher level processors. I was frustrated with my Lenovo 100s 14in - I could not update memory.
I hope none of my comments have mistakes - because I wish we could edit comments here.
Wilco1 - Thursday, February 1, 2018 - link
"In any case, what matters is how many transistors / components can be in square area and not nm metric."7nm TSMC density is 116 million transistors/mm^2, while Intel 7nm does ~100. See https://www.semiwiki.com/forum/content/6713-14nm-1...
"I hope none of my comments have mistakes"
Well pretty much all of our post is FUD or fake news as it is called nowadays. Combining multiple processes on the same die? 3D process? What pills did you take?
Santoval - Thursday, February 1, 2018 - link
I checked out the article you linked and apparently I was wrong above. It says Samsung's 7nm is going to have 127.3 MTr/mm^2 and TSMC's 7nm will have 116.7 MTr/mm^2. I had no idea they were so ambitious. Since Intel will retain 10nm for at least three CPU generations I will concede that they have fallen behind Samsung and TSMC (and GloFo?) even if the others' 7nm node is released two, three or even four quarters after Intel's 10nm.MrSpadge - Thursday, February 1, 2018 - link
" We are actually not sure exactly what Intel's 10nm is like - but it like be more dense that other processes significantly. This is why it taking longer get out. I believes Intel's process is 3D process."They've published details at conferences. FinFETs (in that sense as 3D as before) with air gaps to reduce capacitance and increase performance, together with a material change for the Vias, if I remember correctly. That's quite ambitous and will give them an advantage over processes without those changes.
Density figures have also been published: more dense than TSMCs & Samsungs 10 nm, but less dense than competing 7 nm processes.
FullmetalTitan - Thursday, February 1, 2018 - link
Everyone else covered the wealth of density info released over the last 2 years."Most exiting thing about Intel's processes is that it can combine multiple processes on the same die. This means important components like CPU / GPU / Memory can be on denser material why the IO and less important components can be done on less denser."
This is just local pattern density? You can make transistors larger or less dense than the half-pitch node naming implies.
" I don't believe Intel is using this for combo Intel CPU / AMD GPU component..."
No idea what this rambling means, but Intel is just packaging a coffee lake CPU with a custom Vega die and HBM2 for easier integration into ultrabooks and such, there is nothing special about that venture.
Dragonstongue - Wednesday, January 31, 2018 - link
TSMS/GF/Samsung/IBM etc all build their wafer much differently than Intel does, so, a problem that affects one does not automatically mean it effects the others.I have a feeling Intel was "milking it" because for years and years no other fab was close to competing with them being "the most advanced" so they did as little as they possibly could to ensure the lowest cost highest ROI on every chip/product they sold, but since 28nm, now 14-12-7nm soon enough the competition caught up quite quickly.
Intel may be the "leading producer" but, they generally only produce their own chips, so someone like TSMC whos only job is to build for others gets $ from many places and does many different designs as well, so at least in my opinion, this gives them maybe that much more ability to "tweak" their designs going forward, so in theory would mean more flexibility to work through or around kinks that maybe Intel cannot.
Generally because of the way Intel builds their "bulk" transistors it allows them to have far tighter tolerance on gates and the like, so more oft than not means less voltage required for higher speed or at very least more density per die, this is something that gave them a major advantage vs others (generally using SOI or FD-SOI) however, the density, transistor count, leakage and so forth of Intel vs competition (TSMC-Samsung/GF/IBM) has been very much eroding over the last decade.
So just to iterate IMO just because Intel got lazy or screwed up however you want to word it, they still are making $$$$$$$$$ and really only produce chips for their own purpose, so they likely do not have nearly the same motivation at keeping at the absolute bleeding edge when it comes to nm scaling like they once did, am sure they have many other fish in the pot to worry about.
TSMC as an example, only job is to produce the chips they are paid to do, so they have every motivation to keep pushing in lowever nm higher density, if they are not "the best" others will be, means less $$$$ Intel still makes loads of $$$ from being able to produce high density chips AND making the chips as well.
anyways ^.^
HStewart - Wednesday, January 31, 2018 - link
"Intel may be the "leading producer" but, they generally only produce their own chips, so someone like TSMC whos only job is to build for others gets $ from many places and does many different designs as well"One thing to remember that could be key to future Intel processes is that Intel purchase Altlera which is/was a leader in maker of "Field Programmable Gate Array" which is used to create custom design logic for many different purpose. This was done a while back and I believe a lot of Intel's future designed will benefit from this purchase. This purchase likely means that Intel process will be open to others.
FullmetalTitan - Thursday, February 1, 2018 - link
Intel lost their status as "leading producer" last year. They have been floundering for a while. Ask anyone in the mfg environment and they will tell you that Intel talent has been fleeing for greener pastures for a while nowname99 - Thursday, February 1, 2018 - link
Uhhh, wot?One of these companies has made a habit of lying ever since the 14nm Broadwell delays.
And one has delivered on time year after year since at least 28nm.
Just because INTC doesn’t know what the hell they are doing doesn’t mean the rest of the world is as incompetent...
Lolimaster - Thursday, February 1, 2018 - link
Those are intel problems. global foundries is on track with 7nm.Frenetic Pony - Wednesday, January 31, 2018 - link
Prediction: Production will begin in 2020. Sorry 2021. 2022. 2023, 24, 25, 26...FullmetalTitan - Thursday, February 1, 2018 - link
Kind of my thought, especially since they haven't secured EUV for use in their 7nm node. Unless ASML is magically doubling scanner production next year, they are currently on a 1 tool per month pace, most of which through 2019 have been pre-purchased by various foundries.Speedfriend - Monday, February 5, 2018 - link
FullmetalHas ASML published where their EUV machines are going?
Pork@III - Thursday, February 1, 2018 - link
I seriously worry about the lack of numbers in the row of "Performance"MrSpadge - Thursday, February 1, 2018 - link
Not your point to worry about right now. They will have some idea and probably data, but won't publish them yet (7 nm production has not even started!).Anymoore - Thursday, February 1, 2018 - link
Where has TSMC reported 5nm SRAM results? That should have been big.